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152164dcaf
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10662 Commits

Author SHA1 Message Date
Sebastien Lorquet
152164dcaf commit b2ea300b6f broke the STM32L4 port for people not using the L496xx or L4A6xx. That was because stm32l4_sdmmc.h is included from the stm32l4.h global header, and this header fires an #error for other chips. I see that ALL stm32l4 have the same SDMMC except the stm32l4x2, which has none. 2017-10-02 07:43:39 -06:00
Gregory Nutt
10eed5deef Mostly cosmetic changes from review of last PR. 2017-10-01 12:08:52 -06:00
Mateusz Szafoni
67300e23a0 Merged in raiden00/nuttx (pull request #500) 
stm32_hrtim: add support for capture, chopper, deadtime and dump registers

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-10-01 17:52:39 +00:00
Gregory Nutt
c11345ad4b Squashed commit of the following: 
STM32, STM32 F7:  LTDC and DMA2D drivers are not permitted to set the errno.

    SIM LPC31xx:  Serial and console drivers are not permitted to set the errno.

    SAMv7, STM32, STM32 L4:  DAC and ADC drivers are not permitted to set the errno.
 2017-09-30 11:51:37 -06:00
Gregory Nutt
fa65bad3bf Fix minor spacing issue 2017-09-29 07:34:35 -06:00
Juha Niskanen
e09a31c3b6 Merged in juniskane/nuttx_stm32l4/dfsdm_flash_pr (pull request #497) 
STM32L4 FLASH, DFSDM: option bytes, JEXTSEL bits, ADC1 output to DFSDM chips change

* STM32L4 FLASH: add function for modifying device option bytes

* STM32L4 DFSDM: add JEXTSEL bits, ADC1 output to DFSDM chips change

    ST's documentation hints that ADC output can be routed to DFSDM
    on some STM32L4X3 chips, but I got confirmation from tech support
    that this is just a documentation error so remove this from Kconfig.

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-09-29 13:32:25 +00:00
Oleg Evseev
ef059f78ac STM32 PWR: Adds stm32_pwr_getsbf and stm32_pwr_getwuf functions that return the standby flag and the wakeup flag PWR power control/status register. 2017-09-28 07:50:21 -06:00
Tomasz Wozniak
96d6bc9376 Build break fix: define PWM_TIM2_CH1CFG for channel 1 PWM 2017-09-26 20:55:23 +02:00
Miha Vrhovnik
b2ea300b6f STM32 L4: Add SDMMC driver 2017-09-26 06:22:39 -06:00
Gregory Nutt
b065b1f5df STM32 Serial: Fix some incorrect conditional compilation 2017-09-23 10:58:50 -06:00
David Sidrane
a3364b5bd9 Merged in david_s5/nuttx/master_stm32_f4_i2c (pull request #490) 
stm32:stm32f40xxx I2C ensure proper isr handling

Injecting data errors that causes a STOP to be perceived by the
   driver, will continually re-enter the isr with SB not set and BTF
   and RxNE set.  This changes allows the interrupts to
   be cleared and  propagates a I2C_SR1_TIMEOUT to the waiting task.

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-09-21 20:02:05 +00:00
Juha Niskanen
abcaedb990 Merged in juniskane/nuttx_stm32l4/dfsdm_adc_work_pr (pull request #487) 
STM32L4 ADC, DFSDM: add routing of ADC data to DFSDM filters

* configs/nucleo-l496zg: add DFSDM initialization

* STM32L4 ADC: add option for routing ADC data to DFSDM, fix DFSDM DMA

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-09-20 12:20:45 +00:00
Gregory Nutt
686129bb2e Cosmetic change from review of last PR. 2017-09-19 06:46:20 -06:00
Juha Niskanen
38f44a627b Merged in juniskane/nuttx_stm32l4/stm32l4_dfsdm_pr (pull request #486) 
STM32L4 DFSDM: add peripheral, DAC, TIM: small changes

* STM32L4 DAC: do not configure output pin if it is not used

* STM32L4 TIM: fix compilation of timers with complementary outputs when not PWM_MULTICHAN

* STM32L4 DFSDM: peripheral for digital filters for sigma-delta ADCs

    Initial version. Timer trigger support is not completed and there is
    some issue with DMA.

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-09-19 12:36:19 +00:00
Gregory Nutt
882adb2c82 drivers/video/fb.c: Fix a typo introduced in previous commit. 2017-09-17 14:07:08 -06:00
Gregory Nutt
b90b4d40b6 Fix typos/spelling. SAMV71-XULT: Update README, add support for fb_driver. 2017-09-17 10:38:34 -06:00
Rajan Gill
fd9f67c647 STM32 Tickless: The attached patch removes the restriction to 16bit counts when a 32bit timer is used for the new tickless on the stm32. As it is now, the restriction is very limiting, especially if one wants high granularity and large achievable intervals and has the hardware (namely the 32bit timers) available. 2017-09-16 08:20:07 -06:00
Gregory Nutt
37a29cf3a3 LPC31xx: Change naming of some global variables to match coding standard. 2017-09-14 15:33:28 -06:00
Gregory Nutt
13006ecca9 STM32/STM32 F7: Fix some errors found by Coverity. 2017-09-13 13:05:13 -06:00
Rajan Gill
15784ca46f STM32 Tickless: Fixes compilation error when timer info/debug messages are enabled. 2017-09-13 07:14:13 -06:00
David Sidrane
2bbe389897 stm32:Fix coding standard error 2017-09-12 14:16:46 -10:00
David Sidrane
48f0209b84 stm32f7:I2C fixed typo in comment 2017-09-12 14:16:45 -10:00
David Sidrane
ef411578d5 stm32:stm32 alt I2C ensure proper error handling. 
Injecting data errors would cause the driver to
  continually reenter the isr with BERR an RxNE.
  This fix allows the error to be cleared and
  propagated to the waiting task.
 2017-09-12 14:16:45 -10:00
David Sidrane
617c91b373 stm32:stm32f40xxx I2C ensure proper error handling. 
Injecting data errors would cause the driver to
  continually reenter the isr with BERR an RxNE.
  This fix allows the error to be cleared and
  propagated to the waiting task.
 2017-09-12 14:16:45 -10:00
Jussi Kivilinna
61878848ad net/sock: recvfrom: Fix double leave_cancellation_point on error path 2017-09-12 07:17:53 -06:00
Gregory Nutt
d76a541a57 Trivial, cosmetic 2017-09-11 19:22:49 -06:00
Masayuki Ishikawa
d95153706a Merged in masayuki2009/nuttx.nuttx/lc823450 (pull request #481) 
latest updates on lc823450

* arch/arm/src/lc823450: Conform to the NuttX coding style

    Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>

* arch/arm/src/lc823450: Merge the latest fix in lc823450_rtc.c

    Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>

* arch/arm/src/lc823450: Add ADC driver

    Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>

* arch/arm/src/lc823450: Add watchdog driver

    Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>

* configs/lc823450-xgevk: Enable ADC and watchdog driver

    Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-09-12 01:00:32 +00:00
Mateusz Szafoni
2ffc2ab875 Merged in raiden00/nuttx (pull request #480) 
Master

* smps.c: fix error messages

* stm32f33xxx_hrtim.h: fix definition

* stm32_hrtim: fix pclk calculation

* stm32_hrtim.c: cosmetics

* smps.h: cosmetics

* add upper-half driver for high power LED driver (powerled)

* stm32f334-disco: beginning of lower half driver for high power LED (powerled)

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-09-10 17:43:20 +00:00
Gregory Nutt
435dd39d4c arch/arm/Kconfig: Add more classic ARM11 architecture selections. 2017-09-09 12:44:56 -06:00
Gregory Nutt
3ca3674cca Update/fix last commit: On some STM32's, the CSR regiser is 18 vs. 16 bits wide. Need to use 32-bit register accesses. 2017-09-08 14:21:24 -06:00
Oleg Evseev
3596c75d78 STM32: Add logic for enabling wakeup pins. 2017-09-08 13:23:08 -06:00
Juha Niskanen
3719d0a395 Merged in juniskane/nuttx_stm32l4/stm32l4_adc_kconfig_pr (pull request #478) 
STM32L4: ADC, Kconfig small changes

* STM32L4 ADC: port analog watchdog ioctls from the Motorola MDK

* STM32L4: Kconfig: add some L486 and L496 chips, remove duplicates

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-09-06 22:05:44 +00:00
Jussi Kivilinna
449a891a8e stm32f7: add new configuration option for enabling flash ART Accelerator and flash prefetcher 2017-09-04 07:56:51 -06:00
Mateusz Szafoni
23edfe2557 Merged in raiden00/nuttx (pull request #477) 
Master

* stm32f33xxx_hrtim.h: add some comments

* stm32_hrtim: add burst mode configuration, rename some definitions

* smps.h: add private data to the smps_s structure

* stm32_hrtim: cosmetics

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-09-03 18:46:41 +00:00
Gregory Nutt
860ff78d55 Kinetis: First cut implementation of the alarm read function. Pretty simple because the Kinetis RTC is just a 1Hz counter. 2017-09-03 12:44:45 -06:00
Gregory Nutt
5f67fc8f1b RTC alarms: getalarmdatetime functions are private and should be declared static. 2017-09-03 12:20:13 -06:00
Gregory Nutt
789e204141 Correct naming of fields in struct alm_rdalarm_s. Should not be the same as the corresponding fields of struct alm_setalarm_s. The whole purpose of that naming convention is to keep the field names unique. 2017-09-03 09:51:47 -06:00
Gregory Nutt
f42a8a38eb Add hooks for Boris Astardzhiev's RTC change for STM32L4 to Kinetis. Lower level logic not yet implemented. 2017-09-03 08:39:03 -06:00
Gregory Nutt
9021e1caeb Port Boris Astardzhiev RTC change for STM32L4 to STM32 2017-09-03 08:39:03 -06:00
Gregory Nutt
01fa856f9b Fix warning introduced with PR to STM32L4 RTC. 2017-09-03 08:39:03 -06:00
Gregory Nutt
92b3c9477a Port Boris Astardzhiev RTC change for STM32L4 to STM32F7 2017-09-03 08:39:02 -06:00
Boris Astardzhiev
b1eceb838b Extend the RTC framework with an alarm read ioctl (RTC_RD_ALARM). Through it consumer could get configuration settings about previously scheduled hardware alarms (active status, hours, minutes, seconds). 2017-09-03 08:39:02 -06:00
Mateusz Szafoni
daac3bd7f8 Merged in raiden00/nuttx (pull request #476) 
Master

* stm32_dac.c: fix compilation when DMA disabled for channel

* smps.h: update some comments

* smps.c: more sanity checks

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-09-02 19:52:21 +00:00
Jussi Kivilinna
fe7d8c941c stm32f7: do not enable read-modify-write on DTCM. "AN 4667 - STM32F7 Series system architecture and performance" recommends to disable read-modify-write on DTCM: "If the DTCM-RAM is used as data location and the variables used are byte or/and halfword types, since there is no ECC management in this RAM on the STM32F7 Series, it is recommended to disable the read-modify-write of the DTCM-RAM in the DTCM interface (inthe DTCMCR register) to increase the performance." 2017-09-01 08:01:54 -06:00
Juha Niskanen
258fa08e69 STM32L4 DAC: Fix naming so that DAC1 and DAC2 always refer to channels 1 and 2 
User should not be bothered by details like how many IP blocks there are. As no
current STM32L4 has second DAC block (channel 3), remove support for such
hypothetical hardware. DMA channels corrected.

Change-Id: I2cba7e55803871f1ff945538113f12cf5088f68d
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2017-09-01 10:01:03 +03:00
Juha Niskanen
0003ad171d STM32L4 DAC: separate DMA buffer configuration for channels 
Change-Id: Ibc6dc90b39b784b5534b8908eaf615bf1ddcb7ed
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2017-09-01 10:00:55 +03:00
Juha Niskanen
4025205772 STM32L4 DAC: add option for routing DAC output to ADC 
Actually write something to the DAC DMA buffer.

Change-Id: I1b2516ac26fb17f5242611b56be8926c5f40c2c7
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2017-09-01 10:00:46 +03:00
Gregory Nutt
91d473b816 Revert "stm32 FLASH allow non blocking operation on constrained devices" 
This reverts commit ad2ef95ddf.
 2017-08-31 15:14:26 -06:00
David Sidrane
9fc283526a Merged in david_s5/nuttx/master_stm32_flash (pull request #474) 
stm32 FLASH allow non blocking operation on constrained devices

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-08-31 18:04:07 +00:00
Sergey Ustinov
8c35b2ddca Add the set counter function for stm32 timers 2017-08-31 11:54:00 -06:00