Some fields of mstatus were marked as Reserved Writes Preserve Values, Reads Ignore Values (WPRI),
so we must keep its origin value with addition flags.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
In smp system riscv_cpu_boot run in idle task so there is a overlap with the origin coloration range and in used stack.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Fix EP0 stall and resume properly. EP0 wasn't clearly addressed
on stall / resume operations.
Also fix data reads that provide garbage for the first request.
It has always random data as it's completed prior to any read
operation.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Mux USB IO pins one-by-one using package specific pinmux definitions. This avoids accidentally overwriting IO settings for other pins.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
include theis commit:
commit 6ad8917b7e27e5e80fb9268492b9111b17ed2024
Author: Petro Karashchenko <petro.karashchenko@gmail.com>
Date: Fri Jan 28 09:13:23 2022 +0200
lib: fix compilation when strings.h is included
In a systems that provide strings.h and it is included
together with sbi_bitops.h the compilation error appears.
The ffs() and fls() are provided by strings.h
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
and fix this warning:
Error: include/sbi/sbi_bitops.h:47:19: declaration of 'ffs' shadows a built-in function
static inline int ffs(int x)
^~~
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
PR#5688 review fixes are in this patch. The PR was already
merged so the fixes are addresses here as a separate patch.
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This adds a simple USB device driver for the mpfs. However,
this driver is still at its early phase. Only limited testing
with CDC/ACM has been conducted.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This commit fixes an issue where some peripheral clocks are being
disabled during CPU reset on ESP32-C3.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
They are not really defined and used in any where:
uint32_t up_getmisa(void);
uint32_t up_getarchid(void);
uint32_t up_getimpid(void);
uint32_t up_getvendorid(void);
uint32_t up_gethartid(void);
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
here is the reason:
1.clock_systime_timespec(core function) always exist regardless the setting
2.CLOCK_MONOTONIC is a foundamental clock type required by many places
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
## Summary
A lot of linker scripts were listed twice, once for unix, once for windows.
This PR cleans up the logic so they're only listed once.
## Impact
Any opportunity to use a single source of truth and reduce lines of code is a win!
## Testing
CI will test all build
Fix the CPU1 idle tasks stack corruption since the cpux's idle stack
is loaded from g_cpu_basestack (data section) before, but on this time
it maybe not ready since it is initialized by CPU0, and the value
from g_cpu_basestack is random.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
The image must be placed into:
boards/risc-v/mpfs/icicle/include/boot_romfsimg.h
The image is mounted by mpfs_bringup, which is run by the application
itself, or by board_late_initialize() in the case when
CONFIG_BOARD_LATE_INITIALIZE is defined, e.g. with CONFIG_BUILD_KERNEL
- Add test for mode support, which is architecture dependent
- Add tests for address alignment and region size
- Add option to query for access rights
- The function goes through every PMP entry and tests if an address
range from [base, base+size] has been configured for desired
access rights.
- If several PMP entries match the range and access rights, the
information is combined
- End result is either no access, a partial match was found, or a full
match was found. Details about the partial match are not provided.
The intent for testing access rights and not just blindly applying them
is a case where they are already set in e.g. a bootloader. In this
case, nothing should be done, unless the configuration does not match,
in which case the software must not continue further.
NOTE: THIS ONLY WORKS WHEN KERNEL RUNS IN M-MODE FOR NOW
This frees the PMP for other use, e.g. HART memory separation.
The page tables are statically allocated, 1 per level.
This feature is now behind CONFIG_MPFS_USE_MMU_AS_MPU, because
only the MPFS target supports this (others are not tested).
If the MMU is used for memory separation within a HART, the PMP must
still be configured to allow user access to the memory mapped for the
HART, because PMP *rekoves* access by default. At this point all of
the user memory as well as the kernel RAM are opened.
A more flexible solution for PMP configuration will follow.
The old implementation used the default ld.script for the kernel side
which did not obey the memory.ld limits whatsoever.
Also, provide the user space addresses from the linker script to get rid
of the pre-processor macros that define (incorrect) default values for
the user space composition.
- remove some unneeded includes
- tab/space fixes
- change DEBUGPANIC to PANIC in noreturn function, otherwise it compiles only in DEBUG builds
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
The following options need to be taken in account while determining
the proper hart_index2id -table:
CONFIG_MPFS_HART1_SBI
CONFIG_MPFS_HART1_SBI
CONFIG_MPFS_HART3_SBI
CONFIG_MPFS_HART4_SBI
Unused harts should be marked with -1. Hart0 is never used so it
stays at -1.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Commit 5d1a444812 replaced __attribute__
((unused)) with unused_code but two instances of __attribute__ ((used))
were also incorrectly replaced. Add used_code/used_data and used them
instead.
Some toolchains may be built without libm support, but using
such toochain should not generate any errors in case if math
functions are not used in the program
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Add two config flags for each hart for a bootloader nuttx:
CONFIG_MPFS_HARTx_SBI :
- select whether the hart boots via opensbi or not.
CONFIG_MPFS_HARTx_ENTRYPOINT :
- the target address to jump to, either directly from startup code or
from SBI if CONFIG_MPFS_HARTx_SBI is set
This allows building a nuttx based bootloader application, which can load
different applications/OSs for individual harts and jump to those
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Hart index to hart id table is used to track unused and used harts. This
table is useful when configuring only some of the harts for OpenSBI use.
Mpfs will always have the hart0 unused, so mark it with -1.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
- Define RV_MMU_PT_LEVELS as the arch max
- Add way to find the PPN from a PTE
- Make utility function to create a satp register value, instead of
combining this to mmu_enable
- Add function to read the current satp value
- Add function to write the satp register, also fix the fence instruction
Sv39 is the only mode supported for now. However, it should be trivial
to extend the driver to support the other modes (including Sv32) as well.
The driver is tested with mpfs only, but it should work with any riscv
implementation.
u-boot/kernel may use any uart, not just uart1, depending
on the device tree configuration. They will also reset the
corresponding uarts as well. It doesn't need to be done
here.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This drops the dependency to riscv_internal.h which ensures
less redefinition conflicts. OpenSBI declares some of the
variables again which are spread in many NuttX files.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
There is no such section. Instead, place the object mpfs_head.o at the start of
the text.
Put mpfs_head.o directly into the arch library; there is no need to define
it separately in HEAD_ASRC.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Add a new configuration for CONFIG_N_IRQ_STACKS, whcih defaults to
CONFIG_SMP_NCPUS or 1
- this allows configuring multiple IRQ stacks also in the case where SMP
support is not needed
- this is specifically needed in mpfs target, where "bootloader" build boots
only on one hart, but the startup code executes on all harts and handles SW IRQs
Also don't store/restore GP if RISCV_SAVE_GP is not defined. If the GP is not
stored in fork, it can't be restored for new tasks
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Some SoC like bl602 require the exception entry 8 byte align, it should
be safe for other chips so we can apply it globally.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
fw_start and fw_size were miscalculated. What was needed
was the pointed values of the offsets __mpfs_nuttx_start
and __mpfs_nuttx_end, not the values they had in place.
Also add the next_arg1 initialization.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
For example, task is blocked by nxsem_wait(sem1), use nxsem_wait(sem2)
in signal handler, and take sem2 successfully, after exit from signal
handler to task, nxsem_wait(sem1) returns OK, but the correct result
should be -EINTR.
Signed-off-by: Zeng Zhaoxiu <zhaoxiu.zeng@gmail.com>
It can provide better auto complete experience for modern code editor,
since they use clang/gcc based parser to analyze code but lacks some
target dependent info such as __LP64__ for riscv64.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Add a pinmap header for mpfs to be able to configure MSSIO GPIOs
This also adds Kconfigs for some different chip/package types of the PolarFire SOC
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
commit 2889315c20 added support for pwm
but didn't read the channel numbers provided by user-space. They should
be, otherwise it's not possible to start a sub-set of channels that are
not the first "n" channels.
commit 7354ab187e added an option to break
the loops when using multiple PWM channels to arm pwm drivers. This adds
the same support to the risc-v pwm drivers.
The source directory contents of the OpenSBI directory lib/sbi may be
listed with a one-line wildcard. This makes the Make.defs file look
simpler. The rest of the files need to be picked one at a time.
Co-authored-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
OpenSBI may be compiled as an external library. OpenSBI commit d249d65
(Dec. 11, 2021) needs to be reverted as it causes memcpy / memcmp to
end up in the wrong section. That issue has yet no known workaround.
OpenSBI may be lauched from the hart0 (e51). It will start the U-Boot
and eventually the Linux kernel on harts 1-4.
OpenSBI, once initialized properly, will trap and handle illegal
instructions (for example, CSR time) and unaligned address accesses
among other things.
Due to size size limitations for the mpfs eNVM area where the NuttX
is located, we actually set up the OpenSBI on its own section which
is in the bottom of the DDR memory. Special care must be taken so that
the kernel doesn't override the OpenSBI. For example, the Linux device
tree may reserve some space from the beginning:
opensbi_reserved: opensbi@80000000 {
reg = <0x80000000 0x200000>;
label = "opensbi-reserved";
};
The resulting nuttx.bin file is very large, but objcopy is used to
create the final binary images for the regions (eNVM and DDR) using
the nuttx elf file.
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Assign ways to L2 zerodevice. L2 zero device is used for
the scratchpad functionality. The area may be used for the
harts communicating to each other.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
- Add defconfig and board specific files
- Create mpfs/common for code which is shared between MPFS boards.
- Add support for GPIO driven EMMCSD mux.
- Move DDR Libero definitions from arch to boards.
Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
When waiting for a response to a sent command, the command
complete bit (MPFS_EMMCSD_SRS12_CC) should always guarantee
the completion of that particular command. There's no need
to have some combinations skipping the check of the command
complete bit. Thus, remove the 'waitbits' parameter as it's
unnecessary.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
script.
These functions are strongly declared and thus will be used instead of
any other implementation. Furthermore, necessary Kconfig options are
selected to avoid building those function from NuttX's C library.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Currently configuring the uart3/4 as the serial console
doesn't work. Apply proper changes in mpfs_config.h that
enables the following configuration options:
- CONFIG_UART3_SERIAL_CONSOLE
- CONFIG_UART4_SERIAL_CONSOLE
Also, fix a typo in mpfs_lowputc.c that gives a compile
error if defined.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
When enable DEBUG_TCBINFO config, a global struct will
provide, then debuggers can aware nuttx task infomation.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
cppcheck reports the following:
arch/risc-v/src/mpfs/mpfs_emmcsd.c:2375:22: error: Uninitialized variable: waitbits [uninitvar]
while (!(status & (waitbits | MPFS_EMMCSD_SRS12_EINT))
The finding is positive and this patch initializes it to
zero properly.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
1. Wi-Fi and BLE use common PHY functions.
2. Fix Wi-Fi & BLE coexist adapter error.
3. Update esp-wireless-drivers-3rdparty, provide coexist protection for connection.
1. Fix the issue that Wi-Fi can't connect to some special routers occasionally.
2. Support Wi-Fi 12/13 channel active scanning by default.
3. Update Wi-Fi driver code to fix issue of failure to send pkt.
4. Replace software random with hardware random
5. Fix Wi-Fi mode start error
E51 may configure the L1 and L2 caches. Once configured,
no reconfiguration is possible after hardware reset is
issued.
L2 is 16-way set associative with write-back policy. The
size 2 MB, from which 1 MB is utilized with the values
provided here. That's a total of 8 ways. The rest of the
L2 is left out for the bootloader usage.
mpfs_enable_cache() first checks the bootloader usage
doesn't overlap with the cache itself, thus providing a
set of functional values.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
So far the SD-card functionality has been tested with
the driver. Now, also the internal eMMC has been tested
working with this patch. This patch applies IOMUX and
clock settings that have been tested working with the
internal eMMC in the Polarfire Icicle kit.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This adds the proper flag for introducing the DDR
support. Also call the mpfs_ddr_init() at the
proper location.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This adds DDR training. The training has a small chance of failing,
and then the training is restarted.
DDR training cannot be done meaningfully while the software is
in DDR. If the system is intended to run from eNVM, like a
bootloader, the linker script should be tuned to utilize the envm
region as follows:
envm (rx) : ORIGIN = 0x20220100, LENGTH = 128K - 256
l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 1024k
256 bytes are reserved for the system; The fixed block may be
installed from the 'hart-software-services' -repository:
https://github.com/polarfire-soc/hart-software-services.git
For example, the 256-byte image: hss-envm-wrapper-bm1-dummySbic.bin
may be prepended on the nuttx bootloader image in the following
manner:
cat hss-envm-wrapper-bm1-dummySbic.bin > nuttx_bootloader.bin
cat nuttx.bin >> nuttx_bootloader.bin
riscv64-unknown-elf-objcopy -I binary -O ihex --change-section-lma
*+0x20220000 nuttx_bootloader.bin flashable_image.hex
This provides an image 'flashable_image.hex' that may be flashed on
the eNVM region via Microsemi Libero tool.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
- Fix the FPU enabling code
- If booting from eNVM, all harts start booting. With CONFIG_MPFS_BOOTLOADER,
one can allow just one hart booting and rest are stuck in wfi.
- Check that mtvec is actually updated before continuing the boot
- Create 5 IRQ stacks, one for each hart
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
- Jump to mpfs_start with mhartid in a0 as the comment says
- Don't invalidate mmu tlb on e51 (it doesn't have mmu)
- Fix FPU initialization flags on e54 (it fires IRQ5 and crashes)
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
If we repeatedly call up_cpu_pause and up_cpu_resume, there would be
cases where the next call to up_cpu_pause happens while the other CPU is
still responding to the previous resume request. In this case the
DEBUGASSERT will trigger. We should allow the first CPU to wait until the
other CPU has finished responding to the resume request.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Gregory Nutt has submitted the SGA
Omni Hoverboards has submitted the SGA
David Sidrane has submitted the ICLA
Mateusz Szafoni has submitted the ICLA
Sebastien Lorquet has submitted the ICLA
Paul Alexander Patience has submitted the ICLA
as a result we can migrate the licenses to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
pid variable was initialized to -EINVAL to prevent rt_timer_deinit
from delete an invalid kthread. But priv->pid was being overwritten in the
rt_timer_init, so in case of failure to create a kthread, it would
call rt_timer_deinit with a non expected initialization value.
