Commit Graph

19357 Commits

Author SHA1 Message Date
Gustavo Henrique Nihei
f3e8decad2 xtensa: Build sources required for supporting CONFIG_BUILD_PROTECTED
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-05 23:07:00 +08:00
Gustavo Henrique Nihei
cd1ed92844 xtensa: Build sources for supporting CONFIG_SCHED_BACKTRACE
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-05 23:07:00 +08:00
Gustavo Henrique Nihei
b9703619b5 xtensa: Unify common options within a single Make.defs
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-05 23:07:00 +08:00
Huang Qi
a4e867b8d4 arch/arm/Kconfig: Add description for ARM_THUMB to make it configurable
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-07-05 19:34:18 +08:00
Xiang Xiao
fcc48c2254 arch/arm: Don't include arch/arch.h in include/irq.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-04 13:25:56 +03:00
Xiang Xiao
9ab3417882 arch/risc-v: Move __XSTR, FLOAD/FSTORE and REGLOAD/REGSTORE to the right place
1.Move __XSTR from include/arch.h to include/irq.h
2.Move  FLOAD/FSTORE and REGLOAD/REGSTORE from include/arch.h to src/common/riscv_internal.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-04 13:25:56 +03:00
Xiang Xiao
c20ed58879 arch: Remove the inclusion of arch/irq.h from chip/irq.h
since arch/irq.h will include chip/irq.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-04 13:03:47 +03:00
Alan Carvalho de Assis
922ebe5b96 Fix IOMUX function number 2022-07-01 23:34:21 +08:00
Xiang Xiao
3d1ce144df arch: Move up_getsp from arch.h to irq.h
since all other special register operation in irq.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-01 10:44:55 -03:00
curuvar
0c3db448bb Added Adafruit Feather RP2040, Adafruit KB2040 and Added neopixel driver to support RP2040 2022-06-30 22:13:49 -07:00
Sergey Nikitenko
4285274c31 New stm32wb chip family 2022-07-01 12:13:58 +08:00
Nathan Hartman
a3688b0c3b tiva: Add UART CTS/RTS support
* arch/arm/src/tiva/common/tiva_lowputc.c
  (tiva_lowsetup):
    For each UART, if Kconfig enables RTS/CTS (e.g.,
    CONFIG_UART0_IFLOWCONTROL and/or CONFIG_UART0_OFLOWCONTROL),
    configure the corresponding GPIO(s).

* arch/arm/src/tiva/common/tiva_serial.c:
  (struct up_dev_s):
    If CONFIG_SERIAL_IFLOWCONTROL, add a bool field 'iflow'. If
    CONFIG_SERIAL_OFLOWCONTROL, add a bool field 'oflow'. This is
    inspired by the implementation for kinetis.
  (g_uart0priv, g_uart1priv, g_uart2priv, g_uart3priv, g_uart4priv,
   g_uart5priv, g_uart6priv, g_uart7priv):
    If Kconfig enables RTS/CTS for a UART (e.g.,
    CONFIG_UART0_IFLOWCONTROL thru CONFIG_UART7_OFLOWCONTROL), set
    the corresponding iflow and/or oflow flag(s).
  (up_setup):
    Check the above-mentioned iflow and oflow flags and set or unset
    the RTSEN and/or CTSEN bits in the UART's CTL register to enable
    the feature.
2022-07-01 11:52:02 +08:00
Gustavo Henrique Nihei
5ce77fad1b arch: Remove "0x" prefix preceding "%p" specifier on format string
The "p" format specifier already prepends the pointer address with "0x"
when printing.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-06-30 22:08:58 +03:00
Gustavo Henrique Nihei
ea829cf7d5 xtensa/esp32s3: Add driver for I2C peripheral in Master mode
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-06-30 00:32:17 +03:00
Gustavo Henrique Nihei
0657621848 xtensa/esp32s2: Add driver for I2C peripheral in Master mode
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-06-30 00:32:02 +03:00
Gustavo Henrique Nihei
31cddc922c xtensa/esp32s2: Sync GPIO driver implementation with ESP32-S3
Sync driver interfaces, also fixes the handling of special pin value for
esp32s2_gpio_matrix_in and esp32s2_gpio_matrix_out functions

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-06-30 00:10:41 +08:00
Gustavo Henrique Nihei
2d6cd7e580 xtensa/esp32s2: Fix the number of GPIO IRQs
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-06-30 00:10:41 +08:00
Eero Nurkkala
ef28d915fe risc-v/mpfs: ihc: don't start rptun automatically
Starting the rptun with the autostart flag set will cause significant
delays at the boot, as it will wait for the master to be up. U-boot/linux
combination may take more than 10 seconds to boot to the point where the
rpmsg bus is initialized.

For now, the user needs to initialize the rptun separately, for example,
by issuing the following command:

  rptun start /dev/rptun/mpfs-ihc

This command will also block if started before the rpmsg bus master is up.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-06-28 11:34:38 -03:00
Ville Juven
cfebb5a5c1 risc-v: Move common memory map to its own file from riscv_internal
Move the linker defined symbols to a separate file, so they can be
accessed without pulling in everything from riscv_internal.h and
whatever it includes (e.g. syscall.h drags in a lot).
2022-06-28 14:41:56 +03:00
Huang Qi
bc8cf2c501 arch/arm/armv7-m: Fix error link argument for compiler-rt
Fix:
```
ld.lld: error: unknown argument '-/home/huang/Work/vwear/prebuilts/clang/linux/arm/bin/../lib/clang-runtimes/armv7em_hard_fpv4_sp_d16/lib/libclang_rt.builtins-armv7em.a'
```

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-06-28 12:38:36 +03:00
dependabot[bot]
4f8c8815d6 Spi driver for Stm32wl55
IRQ and DMA mode is not implemented
2022-06-28 10:38:03 +08:00
zouboan
fd8eaf4f42 arch/stm32_capture_lowerhalf.c: add lower half support of capture 2022-06-28 10:35:43 +08:00
Nimish Telang
4afd25b567 this flag is meaningless for the linker 2022-06-27 20:03:03 -03:00
Ville Juven
77a01cfe52 mpfs: Fix IHC memory locations to native width type
Ne numeric type defaults to u32 which is not enough to represent a
native memory location

This fixes build error:
https://github.com/apache/incubator-nuttx/runs/7067877053?check_suite_focus=true
2022-06-27 20:49:00 +08:00
zouboan
78535d0123 arch/stm32_capture: completion other slave mode selection 2022-06-25 14:35:17 +08:00
zouboan
20cd657a65 arch/stm32_capture: fix offset address of slave mode control register 2022-06-25 14:35:17 +08:00
Satoshi Togawa
667afb3b91 sama5: add config SAMA5_SYSTEMRESET in arch/arm/src/Kconfig
SAMA5D2 and SAMA5D4 does not support external reset.
Some SAMA5 board's Kconfig contain item SAMA5_SYSTEMRESET, but it is better in arch/arm/src/Kconfig.
2022-06-25 12:03:15 +08:00
Jukka Laitinen
ba1b8d0712 arch/risc-v/src/mpfs: Add mpfs_gpiosetevent and gpio irq handling functions
Add a function to easily enable event handling on fabric and mss gpios. This
is similar to what exists e.g. for stm32 arm chips.

Also fix some small bugs in mpfs_configgpio related to IRQ bits configuration

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-06-23 21:45:15 +08:00
curuvar
412539e66c Added PWM support to rp2040 2022-06-23 10:17:40 -03:00
curuvar
75facdee72 Added PWM support for rp2040 2022-06-23 10:17:40 -03:00
Simon Filgis
cd1f90c25b Fix can buffer calculaiton. Add two words to every msg buffer 2022-06-23 00:07:42 +08:00
Eero Nurkkala
92760f89eb risc-v/mpfs: emmcsd: fix two issues
This patch fixes the following issues:
  1. MPFS_EMMCSD_HRS06_EMM bitmask had to be 0x7, not 0x03
  2. putreg32() caused outright memory corruption as the
     arguments were in wrong order

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-06-22 09:50:33 +03:00
Alan Carvalho de Assis
19fd0a5587 stm32xx: Fix RTC drift when using HSE
When using HSE to clock RTC NuttX internal time is gaining 5.5 second per
minute. Problem was NuttX using 7182 for one of the RTC division factors,
it should have been 7812. The incorrect factors used are 7182 and 0xff.

These are used in 3-4 places within Nuttx and other places as 7812 and 0xff.
However, the STMicro app note AN4759 suggests using 7999 and 124, which is
what I've used.

Explanation: These 2 factors are used to divide the HSE clock (which at this
point is 1 MHz) to 1 Hz for the RTC hardware.
To test the 2 factors, add 1 to both numbers and multiply them together.
The result needs to be as close as possible to 1 MHz.
The suggested values of 7999 and 124 => 8000*125 = 1,000,000, the prime
factors. So, the best fix for Nuttx would be these values.

Issue discovered and fixed by Peter Moody
2022-06-21 17:58:10 +03:00
Huang Qi
9481456fde risc-v/esp32c3: Implement up_perf_xxx API
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-06-21 21:35:22 +08:00
Michael Jung
9140693567 Add lcd_dev_s pointer to lcd_planeinfo_s
In order to support multiple LCD instances per board, add a pointer from
lcd_planeinfo_s to the lcd_dev_s which it belongs to.  Also enhance the
putrun, getrun, putarea and getarea methods to pass through the
lcd_dev_s pointer to the respective device driver.

Port all LCD device drivers to this lcd_planeinfo_s extension.

Enhance SSD1306 driver to support multiple LCDs.

Signed-off-by: Michael Jung <michael.jung@secore.ly>
2022-06-21 21:33:23 +08:00
Richard Tucker
8f36649aad arch/risc-v/src/litex/litex_emac: add liteeth peripheral driver
See the following for details on the pepheral:
https://github.com/enjoy-digital/liteeth
2022-06-21 12:06:37 +03:00
AuroraRAS
0fe219a8c9 Add I2C_M_NOSTART and I2C_M_NOSTOP support in esp32c3_i2c
Signed-off-by: AuroraRAS <chplee@gmail.com>
2022-06-20 10:34:22 -03:00
Ville Juven
6cb77a8d84 mpfs: Allow mapping of RAM/ROM regions from different memory areas
The old implementation needed a contiguous memory block for user
ROM/RAM. This is because there was only 1 L3 page table which can only
map a contiguous memory area.

Also, remove the PMP configuration which just complicates things,
rely on the MMU mappings instead.
2022-06-20 21:24:18 +08:00
Alan Carvalho de Assis
4eddde90b0 esp32s3: Add support to USBSERIAL to use as console 2022-06-16 17:20:32 +03:00
Satoshi Togawa
9f4691603f sama5: Fix wrong comments. 2022-06-16 17:04:37 +03:00
Jukka Laitinen
d8cc1fd76d arch/riscv/mpfs: Add a config flag to select SD mux state
This has been previously hard-coded to SD-card. Make it build time configurable.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-06-16 09:17:30 -03:00
chao.an
7790839eb0 arch/backtrace: correct the skip counter
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-06-16 21:09:14 +09:00
Abdelatif Guettouche
996995245d xtensa: Remove old references to co-processors.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-06-15 22:06:08 +03:00
Abdelatif Guettouche
9bac291236 arch/xtensa/*.S: Remove some old comments and fix others.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-06-15 18:07:51 +03:00
Abdelatif Guettouche
fe8fa4ff75 arch/xtensa: Move the new saving area directly to A2.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-06-15 18:07:51 +03:00
Abdelatif Guettouche
5ab888692e arch/xtensa/xtensa_context: Place the functions in EXCEPTION_HANDLER
section (IRAM for ESP32xx chips).

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-06-15 18:07:51 +03:00
Abdelatif Guettouche
73a1e0fc58 arch/xtensa: Refactor exceptions' entry and exit.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-06-15 18:07:51 +03:00
Abdelatif Guettouche
1c94cb5324 arch/xtensa: Refactor the differences in ABI calls.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-06-15 18:07:51 +03:00
Abdelatif Guettouche
48f20af8bc arch/xtensa/xtensa_int_handlers.S: Remove unused macro.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-06-15 18:07:51 +03:00
Abdelatif Guettouche
fc22eddc38 arch/xtensa: Refactor the code that's used to get the pre-exception
backtrace.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-06-15 18:07:51 +03:00