Commit Graph

16409 Commits

Author SHA1 Message Date
Matias N
18be4198e1 Revert "nrf52_spi: support not defining MISO/MOSI pins"
This reverts commit e91a806ab6.
2020-11-12 08:01:25 +01:00
YAMAMOTO Takashi
c79bda6e4f sim inttypes.h: Remove PRI/SCN macros for fast and least types
I forgot to remove some of them
in https://github.com/apache/incubator-nuttx/pull/2227 .
This commit removes them.
2020-11-10 00:03:35 -08:00
Matias N
f55a2879ca nrf52 GPIO/GPIOTE: better expose pin interrupt capability
This change improves upon current support for pin interrupts. Before,
a pin interrupt was handled (with nrf52_gpiote_setevent) using one
of the eight available GPIOTE channels. Moreover, it didn't event let
the user specify which channel to use (simply tried to get a free one).
Also, it was buggy since it did not consider unsetting the callback.

Besides GPIOTE channels, there is another way to deal with pin interrupts.
The GPIO peripheral is capable of generating a PORT event
(for the whole GPIO port) depending on the pin SENSE configuration
(HIGH or LOW, or NONE) and GPIO DETECTMODE register
(latching or non-latching).

This change then renames nrf52_gpiote_setevent into nrf52_gpiote_set_ch_event,
maintaining functionality of original function, but now allows specifying
channel (and correctly handles unsetting the callback). Then, a
new nrf52_gpiote_set_pin_event is added, which allows to set a callback
for a given pin. During initialization, interrupt for the PORT event is
enabled and handled in such way that for each pin whose corresponding
bit in LATCH register (indicates the result of pin SENSEing) the
callback for this pin will be invoked. This mechanism means that
every pin can get an ISR. It also avoids using GPIOTE channels for this
purpose which carry higher current consumption.

This new per-pin callback mechanism has some added memory requirement
so it can be disabled and its default is dependant on DEFAULT_SMALL.
When disabled, a callback for the PORT event can be set directly
with nrf52_gpiote_set_port_event

There was only one use of nrf52_gpio_setevent() which was migrated
into nrf52_gpio_set_ch_event() passing channel zero.
2020-11-09 20:23:29 +01:00
chao.an
182507f325 boards/sim: add atexit(2) into naming list
(gdb) b longjmp
Breakpoint 1 at 0x8270
(gdb) r
Starting program: /home/chao/code/m3/nuttx/nuttx
[    0.000000] Assertion failed at file:task/task_onexit.c line: 99

Breakpoint 1, 0xf7b905e0 in siglongjmp () from /lib/i386-linux-gnu/libc.so.6
(gdb)
(gdb) bt
|#0  0xf7b905e0 in siglongjmp () from /lib/i386-linux-gnu/libc.so.6
|#1  0xf7f9c3dc in siglongjmp_alias () from /lib/i386-linux-gnu/libpthread.so.0
|#2  0x5655d668 in up_assert (filename=0x56641018 "task/task_onexit.c", line=99) at sim/up_head.c:132
|#3  0x56567413 in _assert (filename=0x56641018 "task/task_onexit.c", linenum=99) at assert/lib_assert.c:36
|#4  0x565f8cfd in on_exit (func=0x565f8c12 <exitfunc>, arg=0x565fd780 <simuart_restoremode>) at task/task_onexit.c:99
|#5  0x565f8c89 in atexit (func=0x565fd780 <simuart_restoremode>) at task/task_atexit.c:109
|#6  0x565fd819 in simuart_start () at sim/up_simuart.c:112
|#7  0x5656c844 in up_uartinit () at sim/up_uart.c:496
|#8  0x5656ba7a in up_initialize () at sim/up_initialize.c:234
|#9  0x5655da56 in nx_start () at init/nx_start.c:701
|#10 0x5655d5e9 in main (argc=1, argv=0xffffd6f4, envp=0xffffd6fc) at sim/up_head.c:96

Change-Id: Ifd7196b2de7bf9fc7cea764c19a5c0eacf08fdb6
Signed-off-by: chao.an <anchao@xiaomi.com>
2020-11-09 09:08:03 -03:00
Nathan Hartman
8e00110449 tiva/cc13x2_cc26x2: Merge related comments
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_flash.h:

    * Merge comments when they are section separators for
      similar/related registers:

      - TIVA_FLASH_FWPWRITE*
      - TIVA_FLASH_FSM_SECTOR1*
      - TIVA_FLASH_FSM_BSLE*
      - TIVA_FLASH_FSM_BSLP*
2020-11-08 13:39:56 -08:00
Juha Niskanen
ca7a7ccbeb Fix some typos in comments
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
2020-11-08 18:58:20 +01:00
Nathan Hartman
350309856d tiva/cc13x2_cc26x2: Fix nxstyle errors
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_flash.h:

    * Fix nxstyle errors.
2020-11-08 18:56:55 +01:00
Sara Souza
b9d44017cf xtensa/esp32: Watchdog support (MWDTs) 2020-11-08 13:05:24 -03:00
Nathan Hartman
94a10033e0 tiva/cc13x2_cc26x2: Fix nxstyle errors
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_fcfg1.h:

    * Fix nxstyle errors.
2020-11-06 20:47:01 -03:00
Abdelatif Guettouche
2ac2ce55d2 arch/xtensa/src/esp32/esp32_allocateheap.c: Fix the memory regions with
regards to the data used by the ROM.
Static alloaction sections should end at the begining of the ROM data.
The rest of memory (End of ROM data --> End of DRAM) is added to the
heap.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-11-06 18:36:41 -03:00
Nicholas Chin
c7a9b66833 arch/arm/src/imxrt: adds support for WDOG1
Based on work done by Jake Choy.
2020-11-06 18:33:34 -03:00
Daniel P. Carvalho
a5d340a5df Add injected channel support. 2020-11-06 18:31:32 -03:00
Abdelatif Guettouche
5adcdcdc15 arch/arm/src/stm32l4/stm32l4_can.c: Fix nxstyle issues. 2020-11-06 18:28:27 -03:00
Pavel Pisa
be1496b40d stm32l4: correct build of stm32l4_can.c to respect L4 variant.
Signed-off-by: Pavel Pisa<ppisa@pikron.com>
2020-11-06 18:28:27 -03:00
Alan C. Assis
2f612a2077 xtensa/esp32: Move #if defined(SPIRAM) to inside function 2020-11-06 16:19:48 +01:00
Alan C. Assis
d11f02d772 xtensa/esp32: Fix remaining SEPARATE typo 2020-11-06 16:19:48 +01:00
Alan C. Assis
6c37d9ff80 xtensa/esp32: Avoid init PSRAM when SPIRAM is not enabled 2020-11-06 16:19:48 +01:00
YAMAMOTO Takashi
713a21e57c or1k inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
YAMAMOTO Takashi
6062b9f7fc z180 inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
YAMAMOTO Takashi
13f469304c z80 inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
YAMAMOTO Takashi
509a190be2 i486 inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
YAMAMOTO Takashi
c8f3abd910 misoc inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
YAMAMOTO Takashi
f752b360f6 risc-v inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
YAMAMOTO Takashi
4b382c6bab intel64 inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
YAMAMOTO Takashi
64280ad7d9 sh1 inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
YAMAMOTO Takashi
178815ea34 arm inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
YAMAMOTO Takashi
1d4610060d rx65n inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
YAMAMOTO Takashi
7c642466c6 z16 inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
YAMAMOTO Takashi
6bc93b87b0 xtensa inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
YAMAMOTO Takashi
093662bc99 z8 inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
YAMAMOTO Takashi
7f442a6641 mips inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
YAMAMOTO Takashi
5300106428 m16c inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
YAMAMOTO Takashi
58320341f7 avr inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
YAMAMOTO Takashi
49008b5862 hc inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
YAMAMOTO Takashi
dc54af1bf2 avr32 inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
YAMAMOTO Takashi
88489a512d ez80 inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
YAMAMOTO Takashi
577d72258a sim inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
YAMAMOTO Takashi
53256bdaa7 sim: inttypes.h: Make the #ifdef block minimum 2020-11-05 18:49:22 -08:00
Daniel P. Carvalho
e73e03a33f Add fuction to set timer frequency. 2020-11-05 11:36:40 -03:00
Daniel P. Carvalho
3f6157001a Change SPWM example to enable timer after configure timer clock. 2020-11-05 11:36:40 -03:00
Daniel P. Carvalho
d1057403c6 Add helper functions to:
enable/disable timer
  dump timer registers
The timer is no longer enabled at the end of stm32l4_tim_setclock().
2020-11-05 11:36:40 -03:00
Brennan Ashton
54832f37f2 sim: Initial Linux i2c bus support
This adds the inital wiring for i2c bus support in the sim target
and for Linux host adds the lower half that uses the i2c chardev.

Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
2020-11-04 23:51:09 -08:00
ligd
73282fe2d8 arch/sim: add sim alsa support
Squashed commit of the following:

sim audio: call alsa to playback/capture data
sim/audio: correct the format capability
sim/audio: add pause/resume support
sim/audio: add auto stop when meet AUDIO_APB_FINAL
sim/audio: fix abort when set small buffer_size
sim/audio: move sim_audio.c to sim_alsa.c

Change-Id: I8e00ece79159e844ca17fd4c363480b985ee0490
Signed-off-by: ligd <liguiding1@xiaomi.com>
2020-11-04 05:48:14 -08:00
Dong Heng
483b145f3b xtensa/esp32: Fix rt-timer issues
1. function "stop" should really stop repeat timer
2. delete timer really in rt-timer task to avoid resource being broken
3. timer triggers when stopping/deleting it and skip it in ISR
2020-11-04 09:24:59 -03:00
Matias N
9266c54bc2 lcd: add optional putarea()/getarea() operations 2020-11-04 04:00:22 -08:00
Dong Heng
b54f0edff4 xtensa/esp32: Add Partition and OTA device 2020-11-03 21:54:07 +01:00
Oleg Evseev
9dadfc5cc3 stm32f7/stm32_serial.c: fix console re-initialisation if DMA enabled 2020-11-03 11:33:13 -08:00
Juha Niskanen
1ce75cc7c6 arch/arm/src/stm32/stm32_adc.c: do not allow negative ref count
When HAVE_HSI_CONTROL, adc_reset_hsi_disable() calls adc_reset()
followed by adc_shutdown() and this combination is called before
adc_setup() by upper level ADC driver. Without this patch,
priv->initialized wraps from 0 to 255 in this case.

Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
2020-11-03 16:25:03 -03:00
Matias N
2395258486 nrf52: add POWER register definitions; support enabling DC/DC regulator 2020-11-03 08:43:43 -08:00
Frank-Christian Kruegel
168c14bb9d nxstyle errors fixed 2020-11-03 08:07:24 -08:00