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Author SHA1 Message Date
Matthew Trescott
bc80bbddc7 Add Tiva CAN driver 2022-03-15 11:32:31 -04:00
Petro Karashchenko
0df313974c drivers/timers: rename oneshot to periodic notification parameter 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-15 22:27:15 +08:00
chao.an
40f056e92c net/local: correct the socket flags from server socket 
newsock = accept(server, &addr, &addrlen);

replace the socket flags from newsock to server to ensure that
the nonblock flags is handled correctly

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-15 23:04:59 +09:00
chao.an
81130bc692 arch/arm: remove unused arm_copyfullstate/arm_copyarmstate 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-15 23:03:51 +09:00
chao.an
7b9978883c arch/arm: optimize context switch speed 
The current context save implementation saves registers of each task
to xcp context, which is unnecessary because most of the arm registers are
already saved in the task stack, this commit replace the xcp context with
stack context to improve context switching performance and reduce the tcb
space occupation of tcb instance.

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-15 23:03:51 +09:00
Petro Karashchenko
f30fa2fe57 drivers/timers/timer: Add option for non-periodic notification 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-15 11:39:12 +08:00
Petro Karashchenko
b04447d066 timer_lowerhalf: minor improvements 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-15 10:30:48 +08:00
Xiang Xiao
b6bc460b2c arch: Make the comment and definition of CONFIG_SYS_RESERVED correctly 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-14 22:51:00 +02:00
chao.an
ea42981cc6 syscall/names: export the syscall name in STUB module 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-14 21:37:53 +02:00
chao.an
d398ffb930 arm/armv7-a/r: unified syscall registers dump 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-14 21:37:53 +02:00
chao.an
22e71e2d71 board/sim: add support of custom optimization level 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-14 23:25:26 +08:00
Abdelatif Guettouche
d21d02c65d xtensa_panic.S: Save exception cause and vaddr into the user frame. 
This area is what's passed later to assert and be used to dump the
state.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 19:54:30 +08:00
Abdelatif Guettouche
a9e3b5ae37 xtensa_panic.S: A2 is already saved by the caller, no need to save it 
here again.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 19:54:30 +08:00
chao.an
7c02432f0e arm/armv7-a/r: set the default CPU mode to System 
In SVC mode, the banked register will be inconsistent with the user mode register:

arch/arm/src/armv7-a/arm_vectors.S

 276   .globl  arm_syscall
 277   .globl  arm_vectorsvc
 278   .type arm_vectorsvc, %function
 279
 280 arm_vectorsvc:
...
 286   sub   sp, sp, #XCPTCONTEXT_SIZE        // < SVC mode SP
...
 308   stmia   r0, {r13, r14}^                // < USR mode SP/LR
...

[    2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 4
[    2.200000] [ 4] [ ALERT]   R0: 00000004 80001229 00000001 80202018 00000000 00000000 00000000 802027d0
[    2.200000] [ 4] [ ALERT]   R8: 00000000 00000000 00000000 00000000 00000000 802027d0 1080f710 1080f710
[    2.200000] [ 4] [ ALERT] CPSR: 00000073
[    2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708
[    2.200000] [ 4] [ ALERT]   R0: 1 80202018 1 80202018 0 0 0 802027d0
[    2.200000] [ 4] [ ALERT]   R8: 0 0 0 0 0 802027d0 1080f710 80001229
[    2.200000] [ 4] [ ALERT] CPSR: 00000070

SVC SP is 0x80202708
USR SP is 0x802027d0
0x802027d0 - 0x80202708 should be XCPTCONTEXT_SIZE

[    2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 51
[    2.200000] [ 4] [ ALERT]   R0: 00000033 00000000 80202780 00000000 00000000 00000000 00000000 80202710
[    2.200000] [ 4] [ ALERT]   R8: 00000000 00000000 00000000 00000000 00000000 80202710 800039d5 800039b2
[    2.200000] [ 4] [ ALERT] CPSR: 00000070
[    2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708
[    2.200000] [ 4] [ ALERT]   R0: 2b 0 80202780 0 0 0 0 80202710
[    2.200000] [ 4] [ ALERT]   R8: 0 0 0 0 0 10843d80 800039d5 10801425
[    2.200000] [ 4] [ ALERT] CPSR: 00000073

SVC SP is 0x80202708
USR SP is 0x80202710
SP overlap in SVC and USR mode

This commit change the default CPU mode to System and ensure the consistency of SP/LR in USR/SYS mode during syscall.

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-14 19:54:53 +09:00
Xiang Xiao
54e630e14d arch: Merge up_arch.h into up_internal.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-14 09:32:17 +02:00
Xiang Xiao
e800f54bfd arch/mpfs: Don't include nuttx header file in mpfs_opensbi.c 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-14 09:32:17 +02:00
chao.an
4e08b1df93 drviers/syslog: correct the return value of default channel write 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-14 08:59:34 +02:00
Abdelatif Guettouche
cff3d9df7b arch/xtensa: Fix some indentations. 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
6fa4a42e34 xtensa/: Save A3 as part of the regular context saving. 
It was separate because the syscal handler was using it before calling
_xtensa_context_save.  The order of operations has now changed and we
can save A3 with the rest of the context.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
4d1bb20f8c xtensa_user_handler.S: In syscall handler store context before 
continuing the rest of the syscall handling.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
5305f76b1d xtensa_context.S: Use Zephyr's version of spilling the window register 
file.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
2445de173d xtensa_dumpstate.c: Don't dump temporary registers. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
4786963ee2 xtensa_context.S: No need to save A2 before calling 
_xtensa_save_context.  It uses CALL0, in this case A1 is callee saved
and we can it directly.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
2dcbf28f15 xtensa_context.S: A1 should be restored by the caller not 
xtensa_context_resotred. Here it was being restored twice.
Remove the one in xtensa_context_restore.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
5bd2e97a27 xtensa_context.S: Fix the type of _xtensa_context_restore. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
e9018b29bf xtensa_context.S: Remove the CALL0 ABI version of xtensa_context_switch 
as it's the same as the Window ABI now.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Huang Qi
7d58e6263f drivers/note: Add macro guard for instrumention switch 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-14 10:52:48 +08:00
Xiang Xiao
c96c96a399 drivers: Merge the common driver initialization into one place 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-13 11:24:48 -03:00
Xiang Xiao
ea614090cd arch/risc-v: Change hex number to low case in csr.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-13 10:17:25 +02:00
Xiang Xiao
f94093bc2e arch/ceva: Move the idle stack initialization to up_initial_state 
to follow other arch's implementation

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-13 00:28:05 +02:00
Xiang Xiao
4cc28882f9 sched/init: Don't call sq_init/dq_init on global link list 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-12 15:06:39 -03:00
Xiang Xiao
ab872b0199 sched/init: Move binfmt_initialize before hardware initialization 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-12 15:06:39 -03:00
Xiang Xiao
2ce62bb583 sched/irq: Remove the code which zero out g_irqvector fields 
since the boot up code already do it

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-12 15:06:39 -03:00
Xiang Xiao
d9a442a859 mm/iob: Remove initialized static variable inside iob_initialize 
since it's impossible to call iob_initialize twice

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-12 15:06:39 -03:00
Xiang Xiao
b0786606fc sched/wdog: Remove wd_initialize which isn't really used anymore 
since g_wdactivelist is already set to zero by the boot code

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-12 15:06:39 -03:00
Xiang Xiao
cf2538c277 mm/shm: Initialize shm_info_s at the definition place 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-12 15:06:39 -03:00
Xiang Xiao
dfb9a763a7 fs: Initialize g_inode_sem at the definition place 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-12 15:06:39 -03:00
Xiang Xiao
8b7d08f59a net: Reoder the initialize sequence(mac->ip->tcp/udp) 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-12 19:24:17 +02:00
Xiang Xiao
7598070508 net: Remove the unnecessary initialization code 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-12 19:24:17 +02:00
Xiang Xiao
4d0fcc2526 net/igmp: Remove igmp_initialize 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-12 19:24:17 +02:00
Xiang Xiao
19ec0b4fe3 net/route: Remove net_init_fileroute 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-12 19:24:17 +02:00
Xiang Xiao
7028531e74 net/tcp: Remove tcp_listen_initialize 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-12 19:24:17 +02:00
Xiang Xiao
716e27cbeb net/local: Remove local_initialize 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-12 19:24:17 +02:00
Xiang Xiao
9c1fc8da4e net: Remove net_lockinitialize 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-12 19:24:17 +02:00
Xiang Xiao
1a7f49eeb3 arch/z[80|16]: Move up_getsp declaration to arch.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-12 19:21:59 +02:00
Petro Karashchenko
e8213b9ae5 tools: define BOARD_COMMON_DIR only if ARCH_BOARD_COMMON is set 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-12 22:12:44 +08:00
Gustavo Henrique Nihei
d7364a6506 esp32s3-devkit: Enable RT-Timer on board bringup 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-12 15:27:30 +02:00
Gustavo Henrique Nihei
7ede285cfe xtensa/esp32s3: Add support for RT-Timer based on Systimer peripheral 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-12 15:27:30 +02:00
Gustavo Henrique Nihei
86b18bd6e9 xtensa/esp32s3: Move code documentation to the correct place 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-12 11:53:14 +08:00
Gustavo Henrique Nihei
a4db4031c9 xtensa/esp32s3: Stall Systimer when core 1 is temporarily stalled 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-12 11:53:14 +08:00