it doesn't make sense that iob initialization is in up_initialize
but other memory components initialization is called in nx_start
Change-Id: Id43aeaa995f340c5943f59a0067a483ff3ac34a2
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Currently up_allocate_heap() assumes that g_idle_topstack points
top of the heap memory. However, g_idle_topstack pointed incorrect
address in SMP mode which resulted in heap corruption. This PR
moves g_idle_topstack at the end of .noinit to avoid this issue.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Call xxx_timer_initialize from clock subsystem to make timer ready for use as soon as possiblei and revert the workaround:
commit 0863e771a9
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Fri Apr 26 07:24:57 2019 -0600
Revert "sched/clock/clock_initialize.c: clock_inittime() needs to be done with CONFIG_SCHED_TICKLESS and clock_initialize should skip clock_inittime() for external RTC case since the RTC isn't ready yet."
This reverts commit 2bc709d4b9.
Commit 2bc709d4b9 was intended to handle the case where up_timer_gettime may not start from zero case. However, this change has the side-effect of breaking every implementation of tickless mode: After this change the tickless timer structures are used before they are initialized in clock_inittime(). Initialization happens later when up_initialize is called() when arm_timer_initialize().
Since the tickless mode timer is very special, one solution might be to
1. Rename xxx_timer_initialize to up_timer_initialize
2 Move up_timer_initialize to include/nuttx/arch.h
3. Call it from clock subsystem instead up_initialize
Basically, this change make timer initialization almost same as rtc initialization(up_rtc_initialize).
For now, however, we just need to revert the change.
* S32K add support for Nxp drone boards
* Update arch/arm/src/s32k1xx/hardware/s32k1xx_rtc.h codestyle
Co-Authored-By: David Sidrane <David.Sidrane@Nscdg.com>
Co-authored-by: Jari van Ewijk <jari.vanewijk@nxp.com>
Co-authored-by: David Sidrane <David.Sidrane@Nscdg.com>
* Serial Fixed interrupt storm
The target would randomly hang in the serial isr.
The priv->ie and the hardware were inconsistent.
The isr used the priv->ie to gate offloading
the RX data. Bang! Hung.
imxrt_disableuartint(priv, &ie);
ret = imxrt_setup(dev);
/* Restore the interrupt state */
imxrt_restoreuartint(priv, ie);
interrupt-> Of no return
priv->ie = ie;
On a fast cpu with FIFO, this will not work
with out proper protections.
* Serial: Conditionally enable 9 bit mode
* armv7-mi/mpu.hi: Restructure API
Preserve the existing API and enabled better granualriy on
setting.
* Enable MPU for non protected builds to set cache
* mpuinit use symbolic values for addresses
* Allow DTCM on HEAP
* allocateheap Fix Coding style
All STM32L4 MPUs have FLASH_CR_PNB bits (8 bits), and some MPUs have FLASH_CR_BKER bit to change bank if page >= 256.
The code wasn't setting or clearing FLASH_CR_BKER correctly.
Author: Gregory Nutt <gnutt@nuttx.org>
Run .c modified by the PR through tools/nxstyle and correct all reporting coding style problems noted in the file.
Author: Satoshi Togawa <togawa@develcb210.centurysys.co.jp>
STM32L4: Add workaround of data cache corruption on RWW.
Some STM32L4 chips has eratta "Data cache might be corrupted during Flash Read While Write operation". This is also in STM32, and arch/arm/src/stm32/stm32f20xxf40xx_flash.c has workaround.
To enable this workaround, define CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW.
Recent changes removed CONFIG_TIME_ENHANCED and unmasked some warnings. These warnings were caused by nuttx/time.h not being included by files that now referenced clock_daysbeforemonth() and clock_isleapyear().
This commit adds those missing inclusions and eliminates the warnings.
Co-authored-by: Gregory Nutt <gnutt@nuttx.org>
Fix these build errors which occurred if there was no PHY:
chip/lpc17_40_ethernet.c:1643:31: error: expected expression before ';' token
ret lpc17_40_phyinit();
chip/lpc17_40_ethernet.c:3941:1: error: expected identifier or '(' before '{' token
{
chip/lpc17_40_ethernet.c:448:13: warning: 'lpc17_40_macmode' used but never defined
static void lpc17_40_macmode(uint8_t mode);
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
Fix warning: selects SDIO_DMA or SDIO_BLOCKSETUP which has unmet direct dependencies (MMCSD)
Fix warning: selects NETDEV_TELNET which has unmet direct dependencies (NETDEVICES && NET && NET_TCP)
Fix warning: selects ARCH_PHY_INTERRUPT which has unmet direct dependencies (NETDEVICES && ARCH_HAVE_PHY)
Fix warning: selects USBHOST_HAVE_ASYNCH which has unmet direct dependencies (USBHOST)
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Gregory Nutt <gnutt@nuttx.org>
Run all .c and .h files modified in this PR through nxstyle and correct all coding standard problems.
Xiang Xiao <xiaoxiang@xiaomi.com>
Remove TIME_EXTENDED option to more conform C standard
Note: the code/data size increment is small
Fix warning found in build testing: "warning: 'dac_interrupt' defined but not used [-Wunused-function]. The compiler is right, dac_interrupt is not used. It is, apparently, a placeholder for future interrupt support. Now conditioned out with #if 0 to suppress build test warnings.
Co-authored-by: Gregory Nutt <gnutt@nuttx.org>
sama5d3-xplained:ethernet-over-phy configuration found in build testing:
arch/arm/src/sama5/sam_irq.c: Fix "Control reaches end of non-void function " warning
arch/arm/src/sama5/sam_udphs.c: Fix "unused variable 'epno'" warning
boards/arm/sama5/sama5d*-*/src/sam_usb.c: Fix "warning 'HAVE_USBHOST' not defined" warnings
Author: Alan Carvalho de Assis <acassis@gmail.com>
Run nxstyle against .c and .h files and fix it
Author: Juha Niskanen <juha.niskanen@haltian.com>
Fix typos and some incorrect comments
* arch/arm/src/nrf52/hardware/nrf52_twi.h: fix typo
* arch/arm/src/nrf52/nrf52_i2c.c: add interrupts support and some debug messages
* boards/arm/nrf52/nrf52840-dk: add support for hts221 and lsm303agr; boards/arm/nrf52/nrf52840-dk: fix issues noted by nxstyle
Author: Alan Carvalho de Assis <acassis@gmail.com>
Run nxstyle on .c and .h files and fix it
Author: raiden00pl <raiden00pl@gmail.com>
arch/arm/src/nrf52: use the same naming convention for register defs
arch/arm/src/nrf52/hardware/nrf52_ficr.h: remove invalid defs
arch/arm/src/nrf52/hardware: add TIMER register defs
Author: Alan Carvalho de Assis <acassis@gmail.com>
Run nxstyle again .c file and fix error message
Author: Daniel P. Carvalho <danieloak@gmail.com>
Add SPWM example to test STM32L4 PWM driver low level operations.
Fix BUGs.
1. No .c file should include a "Public Types" section. Only a header file can define a public type. A .c file can only define a private type. Several files contained private type definitions. The section that they were defined in, however, was incorrectly named "Public Types." Those were easilty changed to "Private Types" which is what they are.
2. No .c file should include a "Public Function Prototypes" section. All global function prototypes should be provided via a header file and never declared with a .c file.
For No. 2, I corrected as many cases as was reasonable for the time that I had available. But there are still a dozen or so .c files that declare "Public Function Prototypes" within a .c file. This is bad programming style. These declarations should all be moved to the proper header files.
Author: Alan Carvalho de Assis <acassis@gmail.com>
Run nxstyle on .c files and fix the issues
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
arch/stm32 ensure all spi dma handler check the result
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Author: Alan Carvalho de Assis <acassis@gmail.com>
Run nxstyle against .c .h files and fix it
Author: Adam Feuer <adam@starcat.io>
Summary
Adds CDC ECM Ethernet over USB High Speed for SAMA5D36-Xplained
(and maybe other boards) (most of the code was there already,
but didn't work out of the box for the SAMA5D36-Xplained)
Only SAMA5D36-Xplained has been tested so far
Impact
None if you don't use the CDC ECM Ethernet driver
On SAMA5D36-Xplained, this adds high-speed Internet connectivity
over USB 2.0 High Speed. via the USB CDC ECM Gadget driver.
It may work on other boards too.
This also fixed full-speed (low-speed) mode for the board too.
Limitations
Hasn't been tested on anything other than SAMA5D36-Xplained board.
TODO
Ideally this would include a composite RNDIS device so it would
also work seamlessly on Windows. That is for a future PR
Ideally this would include software to help configuration via
mDNS/DNS-SD for plug and play compatibility with Linux and macOS.
That is for a future PR.
Detail
Only a few lines of C driver code needed to be changed, since the
capability was there already. The rest is config and documentation.
Changes the SAMA5D3-Xplained board bringup to match the SAMA5D3-EK
board bringup
A helper script to configure Linux routing and iptables NAT is also
provided, along with documentation on how to use it.
Testing
Manual, on a Ubuntu Linux 19.10 system and MacOS 10.14.6 Mojave
MacBook Pro.
How To Verify
Follow the new CDC ECM Ethernet over USB instructions in the board
README.txt file
Commits:
remove non-UTF-8 chars in comment and reformat
removed unneeded comment markers
instructions for using the defconfigs
removed EMAC from config
- to prove this example only needs the CDC ECM Ethernet over USB to work
added CDC-ECM Ethernet over USB info to README
added U-Boot image
added netusb helper script
- this can configure the Linux network interface and routes
so you can ping or access the NuttX system via TCP/IP.
renamed defconfig dirs to be ethernet-over-usb
- was usb-over-ethernet which is not right
added USB DMA to defconfigs
updated readme with autoboot and debugging info
bringing ethernet-over-usb examples into parity
added cdc ecm ethernet over usb with telnetd config
added defconfig
only use phy interrupt if netdevices is ethernet
- because now netdevice could be CDC ECM ethernet over usb
which has no PHY interrupt
add bringup to Makefile
add bringup
app init cleanup
init cdc ecm driver and rndis driver; some cleanup
fixed some typos and odd characters
usb over ethernet working over usb 2.0 hs
Author: Alan Carvalho de Assis <acassis@gmail.com>
Run nxstyle to check .c and .h files and fix reported issues
Author: liuzhao <happypapa@yeah.net>
Add Quectel EC20 4G LTE Module USB CDC/ACM support
nrf52: add support for GPIO interrupts
nrf52: add macros to decode GPIO PIN and GPIO PORT
nrf52: various cosmetic changes
nrf52: fix GPIO P1 memory address
boards/nrf52840-dk: add support for SPI
boards/nrf52840-dk: add support for LSM6DSL sensor
boards/nrf52840-dk: add support for SX127X radio
Author: Alan Carvalho de Assis <acassis@gmail.com>
Check all .c and .h against nxstyle and fix it.
Author: Alin Jerpelea <alin.jerpelea@sony.com>
fs: smartfs: Fix over capacity write
When the remaining capacity of flash is one sector, if a new root
directory is created by file open, then the root directory's chain is
broken and it causes to SmartFS filesystem crash. Once this fatal
problem occurs, it's impossible to recover even if the system reboot.
Fix it by finally update link of root directory.
fs: smartfs: Fix buffer overrun
fs: smartfs: Fix uninitialized variable warnings
fs: smartfs: Memory leak fix
boards: cxd56xx: Update spresense board.h
- Fix PMIC assignment
- Add specific pin configurations for spresense
- Remove unnecessary definitions
arch: cxd56xx: Add ITM syslog init at startup
arch: cxd56xx: Enable DMA settings dynamically
Author: Alan Carvalho de Assis <acassis@gmail.com>
Verify all .c and .h against nxstyle, fixed the Mixed cases
Author: Alin Jerpelea <alin.jerpelea@sony.com>
cxd56xx improvements (#48)
* arch: cxd56xx: Add size limitation for I2C SCU xfer
This is a fw restriction, unroll loop because it can be transfer
up to 16 bytes.
* arch: cxd56xx: Fix lack of leave_critical_section
add the missing leave_critical_section
* arch: cxd56xx: Remove unnecessary file
this header is duplicate and we can remove it
* arch: cxd56xx: Cosmetic change
remove space after function
* arch: cxd56xx: update topreg registers
the topreg registers are updated to match the cxd5602 HW
* arch: cxd56xx: Add voltage setting for low battery notification
Add voltage setting for low battery notification
* arch: cxd56xx: Improve perfomance of SD card
Improve a problem that the clock of SD Host Controller is lower than the
expected value in SDR25 transfer mode.
* arch: cxd56xx: Cosmetic changes
cleanup to comply with coding standard
* boards: cxd56xx: Cosmetic changes
updates to comply with coding standard
* boards: cxd56xx: Fix SD card cannot mount issue
SD card cannot mount when connecting and disconnecting three times
or more due to wrong state of parameter 'initialized'.
This change enables to skip swtching initialized state when mount
failed.
* arch: cxd56xx: Add size limitation for I2C SCU xfer
This is a fw restriction, unroll loop because it can be transfer
up to 16 bytes.
* arch: cxd56xx: Fix lack of leave_critical_section
add the missing leave_critical_section
* arch: cxd56xx: Remove unnecessary file
this header is duplicate and we can remove it
* arch: cxd56xx: Cosmetic change
remove space after function
* arch: cxd56xx: update topreg registers
the topreg registers are updated to match the cxd5602 HW
* arch: cxd56xx: Add voltage setting for low battery notification
Add voltage setting for low battery notification
* arch: cxd56xx: Improve perfomance of SD card
Improve a problem that the clock of SD Host Controller is lower than the
expected value in SDR25 transfer mode.
* arch: cxd56xx: Cosmetic changes
cleanup to comply with coding standard
* boards: cxd56xx: Cosmetic changes
updates to comply with coding standard
* boards: cxd56xx: Fix SD card cannot mount issue
SD card cannot mount when connecting and disconnecting three times
or more due to wrong state of parameter 'initialized'.
This change enables to skip swtching initialized state when mount
failed.
Run all .c and .h files in last PR through nxstyle.
Author: 脚蹬破拖鞋 <happypapa@yeah.net>
Add Imxrt usdhc insert or remove detection (#43)
* Add usdhc card insertion and removal detection using interrupt for imxrt.
* Add interrupt handle when usdhc insert or remove.
This commit fixes a compilation error that occurs when enabling the
following configuration items for stm32f7 and stm32h7 architectures:
CONFIG_DEBUG_FEATURES=y
CONFIG_DEBUG_ERROR=y
CONFIG_DEBUG_WARN=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_IRQ=y
CONFIG_DEBUG_IRQ_ERROR=y
CONFIG_DEBUG_IRQ_WARN=y
CONFIG_DEBUG_IRQ_INFO=y
The compiler error for stm32f7:
make[1]: Entering directory '/home/pdupreez/dev/wingunder/nuttx/arch/arm/src'
CC: chip/stm32_irq.c
chip/stm32_irq.c: In function 'up_irqinitialize':
chip/stm32_irq.c:497:29: error: 'STM32_IRQ_NIRQS' undeclared (first use in this function); did you mean 'STM32_IRQ_FIRST'?
stm32_dumpnvic("initial", STM32_IRQ_NIRQS);
^~~~~~~~~~~~~~~
STM32_IRQ_FIRST
chip/stm32_irq.c:497:29: note: each undeclared identifier is reported only once for each function it appears in
make[1]: *** [Makefile:172: stm32_irq.o] Error 1
make[1]: Leaving directory '/home/pdupreez/dev/wingunder/nuttx/arch/arm/src'
And the compiler error for stm32h7:
make[1]: Entering directory '/home/pdupreez/dev/wingunder/nuttx/arch/arm/src'
CC: chip/stm32_irq.c
chip/stm32_irq.c: In function 'stm32_dumpnvic':
chip/stm32_irq.c:164:4: warning: #warning Missing logic [-Wcpp]
# warning Missing logic
^~~~~~~
chip/stm32_irq.c: In function 'up_irqinitialize':
chip/stm32_irq.c:522:29: error: 'STM32_IRQ_NIRQS' undeclared (first use in this function); did you mean 'STM32_IRQ_CRS'?
stm32_dumpnvic("initial", STM32_IRQ_NIRQS);
^~~~~~~~~~~~~~~
STM32_IRQ_CRS
chip/stm32_irq.c:522:29: note: each undeclared identifier is reported only once for each function it appears in
make[1]: *** [Makefile:172: stm32_irq.o] Error 1
make[1]: Leaving directory '/home/pdupreez/dev/wingunder/nuttx/arch/arm/src'
This commit replaces all STM32_IRQ_NIRQS defines with the NR_IRQS
define, which seems to be consistent with the rest of the code in
Nuttx.
Author: Alan Carvalho de Assis <acassis@gmail.com>
Fix long line comments in the header files
Author: Mateusz Szafoni <raiden00pl@users.noreply.github.com>
* arch/arm/src/nrf52: add GPIOTE and SAADC registers definitions
* arch/arm/src/nrf52: update some registers definitions
* arch/arm/src/nrf52: add basic I2C support
* arch/arm/src/nrf52: add function to unconfigure GPIO
* arch/arm/src/nrf52/nrf52_lowputc: add missing FAR
Author: Alan Carvalho de Assis <acassis@gmail.com>
Run all .h and .c files modified in last PR through nxstyle.
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
Fix stm32l4_otgfshost.c: error: 'ret' undeclared (#32)
result by commit 6a3c2aded6
Change-Id: I68ba79417d8da102da8d91c74496961aef242dd9
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Run all .c and .h files in last PR through tools/nxstyle and fix all complaints.
Author: macman88 <jjlange91@gmail.com>
LPC17xx serial updates (#29)
* Save CONFIG_ARCH_BOARD_CUSTOM when running 'make savedefconfig'
* Don't compile up_earlyserialinit if USE_EARLYSERIALINIT is not defined
* Added support for RS485 direction control on LPC17xx UART1
* First pass at fractional baud rate divider on LPC17xx/40xx
* Added support for fractional divider to console UART
Author: patacongo <spudarnia@yahoo.com>
arch/arm/src/imxrt/imxrt_enet.c: Fix some warnings found in build testing.
Also fix coding standard problems reported by nxstyle. (#26)
Co-authored-by: Gregory Nutt <gnutt@nuttx.org>
Run all .c and .h files in last PR through nxstyle.
Author: macman88 <jjlange91@gmail.com>
SAME5x Ethernet Support (#25)
boards/arm/samd5e5/same54-xplained-pro/: Adds basic support for Microchip SAM E54 Xplained Pro board.
arch/arm/src/samd5e5/: Adds an Ethernet driver for the SAME5x family (based on the SAMA5 GMAC driver).
* Simplify EINTR/ECANCEL error handling
1. Add semaphore uninterruptible wait function
2 .Replace semaphore wait loop with a single uninterruptible wait
3. Replace all sem_xxx to nxsem_xxx
* Unify the void cast usage
1. Remove void cast for function because many place ignore the returned value witout cast
2. Replace void cast for variable with UNUSED macro
Author: Alan Carvalho de Assis <acassis@gmail.com>
Run all .h and .c files modified in last PR through nxstyle.
Author: Minamiya_Natsuki <yukihiratype2@gmail.com>
Add FMC SDRAM for STM32H7x3 chip (#22)
* Add FMC SDRAM for STM32H7x3 chip
* Add FMC SDRAM for STM32H7x7
* Nuttx Coding Standard requires one declaration per line
* should be __ARCH_ARM_SRC_STM32H7_STM32_FMC_H
* fix bad alignment
* fix typo
* fix typo
* people can't live in furture
* fix comment line length
* fix more comment line length
* fix aligenment
* fix typo
arch/arm/src/sama5/sam_serial.c: uart2port in sam_serial, fix the rest of the uarts in sam_serial
boards/arm/sama5/sama5d2-xult/README.txt: Fix some minor typos
boards/arm/sama5/sama5d2-xult/include/board.h: Update UART pin disambiguation with default UARTn_RXD, _TXD
Code was flawed in that the Pins are defined with the
pullups in the definition. Since there are no alterntes pins
there is no way to remove them. So not enabling the CONFIG
pull up did nothing as did enabling them.
Code also ignored the use of D0 for ready detection causing
3X+ the chatter.
This is now a compile time feature as there was no reason for
it to be a run time. It wasted both flash and ram.
Squashed commit of the following:
Author: Gregory Nutt <gnutt@nuttx.org>
Ran nxstyle against many of the affected files. But this job was too big for today. Many of the network drivers under arch are highly non-compiant and generate many, many faults from nxstyle. Those will have to be visited again another day.
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
This effects all network drivers as well as timing related portions of net/: devif_poll_tcp_timer shouldn't be skipped in the multiple card case. devif_timer will be called multiple time in one period if the multiple card exist, the elapsed time calculated for the first callback is right, but the flowing callback in the same period is wrong(very short) because the global variable g_polltimer is used in the calculation. So let's pass the delay time to devif_timer and remove g_polltimer.
nrf52 updates
board/arm/nrf52/nrf52832-dk: use the on-board virtual COM pins as default UART0 configuration
board/arm/nrf52: initial support for the nrf52840-dk board
board/arm/nrf52: initial support for the nrf52840-dk dongle board
arch/arm/src/nrf52: add support for port 1 GPIO
arch/arm/src/nrf52: initial support for UART1
arch/arm/src/nrf52: add UICR definitions
Approved-by: Gregory Nutt <gnutt@nuttx.org>
STM23L4 LPTIM PWM support with multi-channel
* arch/arm/src/stm32l4/stm32l4_pwm.c:
fixed some bugs
arch/arm/src/stm32l4/stm32l4_pwm.h:
support LPTIM PWM if PWM multi-channel is selected
Channel mode for LPTIM are not available
* arch/arm/src/stm32l4/Kconfig: add new configuration for STM32L4 LPTIM support
* arch/arm/src/stm32l4/stm32l4_pwm.c: fix warning: resetbit may be used uninitialized
Approved-by: Gregory Nutt <gnutt@nuttx.org>
I did suspect that it was just about possible that there's a use for this check (specifically, when you're changing serial the clock immediately after the character is sent) but since we're only testing that the character has left the holding register and not that it's actually been sent to line I don't think it's valid even for this case.
Driver update
* drivers/mtd/Make.defs: Add MTD driver for QuadSPI-based Winbond NOR FLASH
* stm32l4/stm32l4_qspi.c: the "QSPI_DMA_PRIO" has been defined above
Approved-by: Gregory Nutt <gnutt@nuttx.org>
boards/arm/stm32h7/stm32h747i-disco: Remove references to nucleo in the stm32h747i-disco board.
arch/arm/include/stm32h7, arch/arm/src/stm32h7, and boards/arm/stm32h7/stm32h747i-disco: Add support for the STM32H747I-DISCO board.
1) Operational issue
TC (Transmission complete) and TDRE (TX Buffer Empty) were transposed in imxrt_serial.c. The end result was that for unoptimised code everything worked fine, but optimised code got itself into a real mess and continually fired interrupts. The patch attached fixes this. This one would have been found much more quickly if this particular board had supported SWO :-/
2) Startup issue
There are a number of chip errata that apply to the 1052 first revision (A-suffix) that don't apply to the second (B-suffix). Those got me for a while and it's important to use an EVK_B_ dev board if you're suffering stability problems with this particular chip. However, even with that resolved with either optimised or unoptimised code when there is no SNVS (Battery Backup) power and the power is switched on the CPU appears to boot but gets stuck with timer interrupts not being generated. The CPU is running and it will execute linear code. I have determined this by putting an 'imxrt_lowputc('A'+irq)' into up_doirq. For the non-running case the output looks like this;
LLLL
this implies 4 0x0b interrupts have been generated, and nothing else. If I hit keys on the keyboard I get 'e' in the flow. 0x0b is the SVC instruction and is the mechanism by which NuttX handles task switching. 'e' is 0x24, which corresponds to the LPUART1 interrupt. Other than these, the system does not respond further but is happily in the idle loop. In this circumstance if you hit SW2 on the EVKB board though the logjam 'unjams' and normal service is established, output now looks like;
LLLLPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPLPP ...etc.
Where 'P' is 0x0f (the SYSTICK interrupt)....this is what _should_ be happening so; SYSTICK starts up after SW2 has been pressed.
From this point on everything works correctly and you can reboot the CPU, put new code into it or do whatever you wish, **provided power is not cycled off**. If power is cycled off then return to the top and go through the process again.
When there is SNVS power to the CPU then power can be switched on and off as you wish, and the CPU will boot correctly. This has been determined by putting 3V onto J6.
I think we are probably doing something naughty with the way we are starting the clocks to the timers. There are certainly some restrictions on imxrt clock manipulation which we have studiously avoided. I am investigating further and have some potential patches but even if I find the root cause it should not be included in 8.2 as the change could be disruptive.
https://github.com/zephyrproject-rtos/zephyr/pull/8535/commits: "The imxrt1050 is configured to use SYSTICK for the kernel timer, but SYSTICK cannot wake up the soc from low-power modes. Disable low-power modes on this soc until we have support for an alternative timer."
"This fixes k_sleep on the EVKB version of the mimxrt1050_evk board. An earlier version of the board (EVK, not EVKB), had A0 silicon which by default did not enter low-power mode on a wfi."
This patch reverts the WFI enable for further investigation post 8.2. With this patch in place together with the previous one my system is fully stable(*), just drinking a bit more power than I'd like.
(1) unifies the iomux definitions - previously some pins had them, and some didn't. This effectively made it impossible to use the pinmuxes without editing the header file in the standard distribution tree.
(2) unifies the pin definitions so that every pin now has a suffix. This makes it *much* easier to see when a pin is in use in your code, because it will always have a definition in your board.h file.
For anyone who is already using this CPU, a couple of small changes are needed to existing code;
In respect of (1) add IOMUX decorators to your pin definitions. You will find defaults in haardware/imxrt_iomux.h. Every pin should have a IOMUX decorator and in general the defaults should be OK. So while previously in your board.h file you might have had;
You will now have;
In respect of (2) you will need to add selectors for any function that previously only had one pinning option. There aren't many of those but LPUART1 is a good example. That just means adding into your board.h something like;
STM32H7:Set the BBSRAM memory range to non-cacheable.
* armv7-m:mpu add user peripheral helper
* stm32h7:BBSRAM Exclude BBSRAM from cacheable when CONFIG_ARMV7M_DCACHE
ST placed the STM32H7 BBSRAM in the SRAM default memory region
which is cacheable. This commit sets the BBSRAM memory range
to non-cacheable.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/tiva/common/tiva_flash.c: Fix several mistakes in
tiva_write() but note that this function needs more work. (1) Fix wrong
use of && when & was intended. (2) Add compile- time warning directive
because according to this function's interface, it is supposed to
support unaligned writes and/or writes of arbitrary numbers of bytes to
FLASH. However, this function does NOT support that at this time. This
needs to be fixed. (3) Fix wrong preprocessor conditional. Was written
to use the 32-word write buffer only for TM4C1294NCPDT. This buffer is
available on all TM4C123 and TM4C129 parts. Now conditioned upon
CONFIG_ARCH_CHIP_TM4C123 or CONFIG_ARCH_CHIP_TM4C129. (4) Add comments
to document the intent of the above preprocessor logic.
stm32l4_otgfs: enable OTGFS for STM32L4+ series
The OTGFS peripheral on stm32l4x6 and stm32l4rxxx reference manual is
exactly the same. This patch also adds missing bits and fixes errors in
stm32l4x5xx and stm32l4x6xx OTGFS register maps.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Add DMA support for STM32L4+ series
* Add DMA support for STM32L4+
* stm32l4xrxx_rcc: enable "Range 1 boost" mode if any PLL freq above 80 Mhz
Approved-by: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/stm32f0l0g0: Pinmap TIM1 GPIOs available for STM32G0
arch/arm/src/stm32f0l0g0: Add TIM driver lowerhalf
arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c: Handle 32-bit overflow on some calculations.
arch: armv7-m: Fix a deadlock in up_sigdeliver() in SMP mode.
In previous implementation, up_disable_irq() was called before
recovering local context. However, I noticed a deadlock happens
in the following situation. For example, if up_sigdevliver() is
in progress on CPU0 and CPU1 has called up_cpu_paused to CPU0,
hence g_cpu_irqlock has been locked by CPU1, in this case,
we would see a deadlock in later call of enter_critical_section()
to restore irqcount.
To avoid this situation, we need to call enter_critical_section()
to break the deadlock.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Spresense smp
* arch: arm: Add ARCH_GLOBAL_IRQDISABLE to ARCH_CHIP_CXD56XX in Kconfig
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch: arm: cxd56xx: Make fpuconfg() public in cxd56_start.c
NOTE: fpuconfig() is called in both cxd56_start.c and cxd56_cpustart.c
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch: arm: cxd56xx: Add support for SMP
NOTE: To run cxd56xx in SMP mode, new boot loader which will be
released later must be used.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch: arm: cxd56xx: Add irq routing for SMP in cxd56_irq.c
NOTE: In cxd56xx, each external interrupt controller can be
accessed from a local APP_DSP (Cortex-M4F) only. This commit
supports IRQ routing for SMP by calling up_send_irqreq() in
both up_enable_irq() and up_disable_irq().
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* boards: spresense: Add smp configuration
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
cxd56xx: various fixes
* arch: arm: cxd56xx: Support to set any i2c frequency
This commit supports to be able to set the i2c frequency other than just
100 or 400 Hz.
* arch: arm: cxd56xx: Enable SD clock during access to SD card
- Improve GNSS low sensitivity with SD card inserted
- Reduce power consumption by stopping SD clock
* arch: arm: cxd56xx: Do PANIC() when cpu rx fifo is overflow
If CPU Rx FIFO is overflow, it's fatal error for system. In such a case,
this commit changes to allow the user to notice by calling PANIC() for
debuggability enhancement.
* arch: arm: cxd56xx: Fix compile error in sdhci debug code
* arch: arm: cxd56xx: Remove assertion in cpu tx queue
When CPU Tx queue is overflow, it returns -EAGAIN instead of assertion
to be able to retry.
* arch: arm: cxd56xx: Add configurations for cpu fifo elements
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: Fix LPADC configuration
LPADC options defined in the same symbol name, so kconfig tool
couldn't process them correctly.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: Update loader and gnssfw ver.17660
* arch: arm: cxd56xx: Fix hang-up when error interrupt occurs
Fix a problem that error interrupts are not cleared.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: Fix sdhci semaphore
Fix inital value of semaphore in sdhci drive.r
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: Treat the initial value of LNA power as off
LNA is always turned power on when GNSS is started. So it is desirable
that the initial value of the LNA power is off by default.
* boards: cxd56xx: Remove initial setting of PIN_AP_CLK
PIN_AP_CLK is used as a port selector of SDIO expander on the extension
board, and is set output low in initalizing. Therefore, this pin cannot
be used for other board. To avoid this restriction, remove this initial
operation because this pin is pulled down by default on the extension
board.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Most of the bluetooth and wifi chips appear to need external firmware, and the 43438 is no exception. Fortunately, since Cypress got involved, these are much more straightforward to obtain and are shipped as part of their SDK, which is downloadable from their website. Those firmwares are already provided as C arrays, so their names just need updating to;
const unsigned char bt_firmware_hcd -> The bt firmware array.
const int bt_firmware_len = sizeof(bt_firmware_hcd);
arch/arm/src/stm32f0l0g0/stm32g0_rcc.c: Set VOS and flash wait states properly
arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c: Renamed from arch/arm/src/stm32f0l0g0/stm32_pwr.c
arch/arm/src/stm32f0l0g0/stm32g0_pwr.c: Preliminary implementation of PWR module for STM32G0 (stm32_pwr_setvos() only)
arch/arm/include/stm32f0l0g0: add support for STM32G070CB, STM32G070KB, STM32G070RB
arch/arm/src/stm32f0l0g0: add support for STM32G070CB, STM32G070KB, STM32G070RB
stm32h7: bbsram issues causing no writes and hardfaults
* stm32_pwr:Ensure data is flushed on backup domain access changes
* stm32h7:bbsram convince compiler to perform 32 bit write
Approved-by: Gregory Nutt <gnutt@nuttx.org>
noards: arm: cxd56xx: migrate common code
* boards: arm: cxd56xx: common: move boot to common
This is a common function and can be reused by all boards.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: common: move flash to common
This is a common function and can be reused by all boards.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: common: move I2C driver to common
This is a common function and can be reused by all boards.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: common: move uid to common
This is a common function and can be reused by all boards.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: common: move usbmsc to common
This is a common function and can be reused by all boards.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56: add SPH
The SPH is used by the ASMP implementation from the SDK.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
boards: cxd56xx: add SCU sensors (2/2)
* boards: cxd56xx: add cxd56_bh1721fvc initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_bh1745nuc initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_bm1383glv initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_bm1422gmv initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_bmi160 initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_bmp280 initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_kx022 initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_lt1pa01 initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_rpr0521rs initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_sensors initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56: add Backup Log driver
The driver will be used to backup logs on crash.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: common: add crashlog driver
Add Crashlog driver with support for reset on crash
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: move gs2200m initialization
Move the board gs2200m initalization to the common board folder
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: move ili9340 initialization
Move the board ili9340 initalization to the common board folder
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: move lpm013m091a initialization
Move the board lpm013m091a initalization to the common board folder
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: common: typo fixes
HEADER: Updates on file location
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
