Commit Graph

1718 Commits

Author SHA1 Message Date
Gregory Nutt
1c5ec07414 arch/: Remove dangling space at the end of lines. 2017-06-28 13:16:48 -06:00
Gregory Nutt
aa1708e7c0 6LoWPAN: Update README; fix duplicate and bad memcpy in loopback driver. 2017-06-26 10:53:57 -06:00
raiden00pl
715d6fa9ff stm32f33xxx_rcc: cleanup + move hrtim clock source selection 2017-06-26 18:30:10 +02:00
raiden00pl
aead2b2afd stm32f33xxx_rcc.h: fix typo 2017-06-26 18:26:59 +02:00
Sebastien Lorquet
0bf4893b2c STM32: Allow clock frequencies > 168 Mhz on stm32f427/429. We need to enable the power overdrive for this case. This patch allows the required bits to be set in proper sequence. It also modifies the local register access operations to allow more than 16-bit registers. 2017-06-20 11:56:54 -06:00
Gregory Nutt
47ad81b3e5 Trivial spelling fix 2017-06-20 08:02:42 -06:00
raiden00pl
c29c4e2ec2 stm32_hrtim: remove unneeded definitions 2017-06-18 18:08:25 +02:00
raiden00pl
4e0f45f252 stm32_hrtim: fix initialization bug, minor changes 2017-06-18 18:06:37 +02:00
raiden00pl
cd30545cd9 stm32_hrtim: ADC triggering and DAC synch events 2017-06-18 15:26:39 +02:00
raiden00pl
96e639262a stm32_hrtim: add hrtim ops 2017-06-18 11:01:36 +02:00
raiden00pl
797e286cb0 stm32_hrtim: timers mode configuration 2017-06-18 09:28:05 +02:00
raiden00pl
dfeffefa69 stm32_hrtim: typo 2017-06-18 08:02:15 +02:00
Gregory Nutt
0024840f7d Trivial, cosmetic changes from review of last PR 2017-06-17 14:44:11 -06:00
raiden00pl
b48a86ee33 Merge remote-tracking branch 'upstream/master' 2017-06-17 22:18:03 +02:00
raiden00pl
4d9d3c4a9c stm32_hrtim: cosmetics 2017-06-17 22:12:56 +02:00
raiden00pl
5e3360b8b9 stm32_hrtim: faults and events configuration 2017-06-17 21:56:11 +02:00
David Sidrane
c79d4d1988 stm32:flash add CONFIG_STM32_STM32F469 to list defining OPTCR1 2017-06-16 14:16:32 -10:00
Gregory Nutt
5245cbc6f5 STM32 SPI/I2S: Back out a bad pin mapping change from 4ab2a3661e. Try to staighten out some I2C3 and SPI3 pin configuration stuff. 2017-06-16 09:34:22 -06:00
Sebastien Lorquet
4d9be9bc20 STM32 F4 FLASH: Enable/disable the flash write protection on any sector. I have verified it to work on the stm32f427. 2017-06-16 08:46:57 -06:00
raiden00pl
bd7bee5db0 stm32_hrtim: structures for deadtime and chopper, cosmetics 2017-06-16 11:36:23 +02:00
raiden00pl
268c6d0b7d stm32_hrtim: outputs enable, period and compare functions, cosmetics 2017-06-15 16:45:21 +02:00
Gregory Nutt
d958cec7a4 Cosmetic changes from review of last PR 2017-06-15 06:58:55 -06:00
raiden00pl
96d40dec40 stm32_hrtim: cosmetic 2017-06-15 11:20:40 +02:00
Leif Jakob
4a79547fb8 multiple fixes for stm32f1xx RTC clock
- compile issues because of missing RTC_MAGIC #defines
- missing functionality based on RTC_MAGIC in RTC based on stm32_rtcounter.c
- IRQ setup from up_rtc_initialize was later reset in up_irqinitialize
- write access to backup registers without enabling access to backup domain
- possible races in set/cancel alarm
tested with STM32F103C8 only
device now wakes up from forced STANDBY mode by alarm
2017-06-14 22:36:40 +02:00
Gregory Nutt
e379491d13 STM32/STM32L4: Review of last commit -- Eliminate possible underflow 2017-06-13 07:05:46 -06:00
JM
7903a8a46c stm32/stm32l4 PWM: While attempting to output a 70 MHz square wave from the timer output of a STM32 clocked at 140 MHz (which works fine in baremetal C), I stumbled on what I believe to be an error in arch/arm/src/stm32/stm32_pwm.c. Line 1304 we are told that
reload = timclk / info->frequency;

which I belive to be incorrect, it should be

reload = timclk / info->frequency - 1;

since starting to count from 0, if I want to output half of the TIM clock, I must count to 1 and not to 2.

Surely enough, the original code did output 140/3=47 MHz, while this correction does allow the output up to 70 MHz.

I am not sure this affects most users generating slow PWM (e.g. PX4) but for frequencies
close to the PCLK, indeed the difference becomes significant.
2017-06-13 06:01:13 -06:00
raiden00pl
f6ba4642a3 stm32_hrtim: GPIOs configuration + EEV and FAULT strucutres 2017-06-12 18:45:58 +02:00
raiden00pl
de8cd6c870 stm32_hrtim: add character driver 2017-06-11 20:51:23 +02:00
Gregory Nutt
fe813545e8 STM32F33: Forgot to add new files that were a part of the last patch before committing. 2017-06-11 11:00:29 -06:00
Mateusz Szafoni
437ad3ccb2 STM32F33: Fix hrtim definitions, Add beginning of HRTIM driver 2017-06-11 10:49:20 -06:00
Juha Niskanen
0c9abbfe67 STM32L4: Add IWDG peripheral. This is the same as for STM32 except that prescale and reload can be
changed after watchdog has been started, as this seems to work on L4.
2017-05-23 07:02:36 -06:00
Gregory Nutt
7ffbb704d6 This is based on a patch by Taras Drozdovsky. Basically, the delay that was added during the integration of the CDC/ACM host driver was interfering with streaming audio. That delay was put there to prevent build endpoints from hogging the system bandwidth. So what do we do? Do we hog the bandwidth or do we insert arbitrarity delays. I think both ideas such. 2017-05-21 14:28:29 -06:00
Taras Drozdovsky
4ab2a3661e STM32F4: add cs43l22 audio driver and i2s driver 2017-05-21 14:14:09 -06:00
Juha Niskanen
819a6e049e stm32_i2c: make private symbols static 2017-05-19 07:16:01 -06:00
Gregory Nutt
989195cec8 STM32 Ethernet: Last patch breaks every board that does not use the KSZ80801 PHY. 2017-05-17 15:36:57 -06:00
Gregory Nutt
aac3a3df8e STM32 Ethernet: Should not stm32_phyintenable() return a failure if it could not enable the PHY interrupt? 2017-05-17 10:07:09 -06:00
Sebastien Lorquet
2c6ea23aee STM32 Ethernet: Add support for KSZ8081 PHY interrupts. 2017-05-17 10:04:49 -06:00
Jussi Kivilinna
9169ff6a15 stm32_serial: fix freezing serial port. Serial interrupt enable/disable functions do not disable interrupts and can freeze device when serial interrupt is received while execution is at those functions.
Trivially triggered with two or more threads write to regular syslog stream and to emergency stream. In this case, freeze happens because of mismatch of priv->ie (TXEIE == 0) and actually enabled interrupts in USART registers (TXEIE == 1), which leads to unhandled TXE interrupt
and causes interrupt storm for USART.
2017-05-17 06:50:46 -06:00
Lederhilger Martin
b8e7d5c455 I had the problem that the transmit FIFO size (= actual elements in FIFO) was slowly increasing over time, and was full after a few hours.
The reason was that the code hit the line "canerr("ERROR: No available mailbox\n");" in stm32_cansend, so can_xmit thinks it has sent the packet to the hardware, but actually has not. Therefore the transmit interrupt never happens which would call can_txdone, and so the size of the FIFO size does not decrease.

The reason why the code actually hit the mentioned line above, is because stm32can_txready uses a different (incomplete) condition than stm32can_send to determine if the mailbox can be used for sending, and thus can_xmit forwards the packet to stm32can_send. stm32can_txready considered mailboxes OK for sending if the mailbox was empty, but did not consider that mailboxes may not yet be used if the request completed bit is set - stm32can_txinterrupt has to process these mailboxes first.

Note that I have also modified stm32can_txinterrupt - I removed the if condition, because the CAN controller retries to send the packet until it succeeds. Also if the condition would not evaluate to true, can_txdone would not be called and the FIFO size would not decrease also.
2017-05-16 07:47:18 -06:00
Gwenhael Goavec-Merou
02535be36a STM32F410. Add support for STM32Fr10. STM32F410 is a version of STM32F4 with 32 KB of RAM and 62 or 128 KB of flash. 2017-05-13 08:40:09 -06:00
Alan Carvalho de Assis
853d332b6c Move CAN subsystem to its own directory and put device drivers there
Signed-off-by: Alan Carvalho de Assis <acassis@gmail.com>
2017-05-12 11:48:47 -03:00
Gregory Nutt
0de294a586 Fix lots of occurrences of 'the the', 'the there', 'the these', 'the then', 'the they. 2017-05-11 13:35:56 -06:00
David Sidrane
014b69e120 removed stray paren. 2017-05-08 22:56:05 +00:00
David Sidrane
8406b40baa Merged in david_s5/nuttx-16/david_s5/stm32serial-dma-buffer-round-off-not-up-1494258804216 (pull request #357)
stm32:Serial DMA buffer round off not up

Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-05-08 20:32:44 +00:00
Gregory Nutt
aa11d637a8 STM32 TIM: Add method to get timer width. Freerun timer: Use timer width to get the correct clock rollover point. 2017-05-08 12:33:15 -06:00
David Sidrane
546e7acb99 stm32:Serial DMA buffer round off not up 2017-05-08 15:54:03 +00:00
David Sidrane
b8ef079951 stm32:stm32_serial Forgot the -1 on mask 2017-05-08 03:43:36 +00:00
David Sidrane
b62ef579c8 stm32: serial Allow configuring Rx DMA buffer size 2017-05-06 05:16:21 -10:00
Gregory Nutt
b0e880b04c Revert "STM32 I2C: More backward tests of CONFIG_I2C_POLLED. Needs to be reviewed."
This reverts commit 1e054a2d3b.
2017-05-03 18:26:24 -06:00
Gregory Nutt
11c14470c3 Merge remote-tracking branch 'origin/master' into photon 2017-05-03 17:36:52 -06:00