Commit Graph

962 Commits

Author SHA1 Message Date
Gustavo Henrique Nihei
5e32aa14bf risc-v/esp32c3: Fix verification of ROM function return values
cache_dbus_mmu_set and cache_ibus_mmu_set return positive values in case
of errors, so DEBUVERIFY could never detect them since this macro checks
for negative values.
Besides, the successful execution of those functions is mandatory for
the reliable operation under Protected Mode, so the verification is
always performed, even when DEBUG is not enabled.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-12 10:56:59 +08:00
Nathan Hartman
849f760b77 Fix various typos 2022-07-08 02:15:54 +08:00
Abdelatif Guettouche
0bdf713df0 risc-v/esp32c3: Add the rest of the reset causes.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-07-08 01:06:35 +08:00
Xiang Xiao
3daa18b661 arch: Remove the unnecessary #if/#endif in assert
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-07 19:25:47 +03:00
Xiang Xiao
9ff0971d3f arch: Correct the order of stack related information in assert
forget to update in this patch:
commit b02db04e00
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
Date:   Sun Jun 5 17:10:19 2022 +0800

    arch/assert: Keep the thread dump column order same as ps

    Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-07 19:25:47 +03:00
Xiang Xiao
9ab3417882 arch/risc-v: Move __XSTR, FLOAD/FSTORE and REGLOAD/REGSTORE to the right place
1.Move __XSTR from include/arch.h to include/irq.h
2.Move  FLOAD/FSTORE and REGLOAD/REGSTORE from include/arch.h to src/common/riscv_internal.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-04 13:25:56 +03:00
Xiang Xiao
c20ed58879 arch: Remove the inclusion of arch/irq.h from chip/irq.h
since arch/irq.h will include chip/irq.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-04 13:03:47 +03:00
Xiang Xiao
3d1ce144df arch: Move up_getsp from arch.h to irq.h
since all other special register operation in irq.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-01 10:44:55 -03:00
Gustavo Henrique Nihei
5ce77fad1b arch: Remove "0x" prefix preceding "%p" specifier on format string
The "p" format specifier already prepends the pointer address with "0x"
when printing.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-06-30 22:08:58 +03:00
Eero Nurkkala
ef28d915fe risc-v/mpfs: ihc: don't start rptun automatically
Starting the rptun with the autostart flag set will cause significant
delays at the boot, as it will wait for the master to be up. U-boot/linux
combination may take more than 10 seconds to boot to the point where the
rpmsg bus is initialized.

For now, the user needs to initialize the rptun separately, for example,
by issuing the following command:

  rptun start /dev/rptun/mpfs-ihc

This command will also block if started before the rpmsg bus master is up.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-06-28 11:34:38 -03:00
Ville Juven
cfebb5a5c1 risc-v: Move common memory map to its own file from riscv_internal
Move the linker defined symbols to a separate file, so they can be
accessed without pulling in everything from riscv_internal.h and
whatever it includes (e.g. syscall.h drags in a lot).
2022-06-28 14:41:56 +03:00
Nimish Telang
4afd25b567 this flag is meaningless for the linker 2022-06-27 20:03:03 -03:00
Ville Juven
77a01cfe52 mpfs: Fix IHC memory locations to native width type
Ne numeric type defaults to u32 which is not enough to represent a
native memory location

This fixes build error:
https://github.com/apache/incubator-nuttx/runs/7067877053?check_suite_focus=true
2022-06-27 20:49:00 +08:00
Jukka Laitinen
ba1b8d0712 arch/risc-v/src/mpfs: Add mpfs_gpiosetevent and gpio irq handling functions
Add a function to easily enable event handling on fabric and mss gpios. This
is similar to what exists e.g. for stm32 arm chips.

Also fix some small bugs in mpfs_configgpio related to IRQ bits configuration

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-06-23 21:45:15 +08:00
Eero Nurkkala
92760f89eb risc-v/mpfs: emmcsd: fix two issues
This patch fixes the following issues:
  1. MPFS_EMMCSD_HRS06_EMM bitmask had to be 0x7, not 0x03
  2. putreg32() caused outright memory corruption as the
     arguments were in wrong order

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-06-22 09:50:33 +03:00
Huang Qi
9481456fde risc-v/esp32c3: Implement up_perf_xxx API
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-06-21 21:35:22 +08:00
Richard Tucker
8f36649aad arch/risc-v/src/litex/litex_emac: add liteeth peripheral driver
See the following for details on the pepheral:
https://github.com/enjoy-digital/liteeth
2022-06-21 12:06:37 +03:00
AuroraRAS
0fe219a8c9 Add I2C_M_NOSTART and I2C_M_NOSTOP support in esp32c3_i2c
Signed-off-by: AuroraRAS <chplee@gmail.com>
2022-06-20 10:34:22 -03:00
Ville Juven
6cb77a8d84 mpfs: Allow mapping of RAM/ROM regions from different memory areas
The old implementation needed a contiguous memory block for user
ROM/RAM. This is because there was only 1 L3 page table which can only
map a contiguous memory area.

Also, remove the PMP configuration which just complicates things,
rely on the MMU mappings instead.
2022-06-20 21:24:18 +08:00
Jukka Laitinen
d8cc1fd76d arch/riscv/mpfs: Add a config flag to select SD mux state
This has been previously hard-coded to SD-card. Make it build time configurable.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-06-16 09:17:30 -03:00
Eero Nurkkala
5683e020e8 risc-v/mpfs: update clock configuration parameters
Update PLL configuration parameters to match the values provided
by the vendor.

Also remove extra call to mpfs_pll_config() as it's already called
at mpfs_clockconfig().

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-06-15 21:29:45 +08:00
Masayuki Ishikawa
a0ff6f9fa6 arch: k210: Add a workaround for clock stabilization
Summary:
- I noticed that sometimes uart shows nothing on the maix-bit board.
- This commit adds a workaround to avoid such the issue

Impact:
- k210 only

Testing:
- Tested with maix-bit

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-06-13 11:42:59 +08:00
Norman Rasmussen
e6376c72d7 Fix CONFIG_ALLSYMS for arm, risc-v and xtensa after #5496 2022-06-13 11:39:06 +08:00
Gustavo Henrique Nihei
59da1bc86a risc-v/esp32c3: Disable region protection on IDFboot for Flat build
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-06-11 01:55:46 +08:00
Gustavo Henrique Nihei
5805ad3954 risc-v/esp32c3: Disable access to invalid memory regions using MPU
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-06-11 01:55:46 +08:00
Ville Juven
16286081e1 risc-v/mpfs: Move the entry point to .start section
Remove the object linkage and use an explicit .start section
2022-06-10 20:18:23 +08:00
Eero Nurkkala
39d389545e risc-v/mpfs: usb: add composite support
This provides USB composite (CDC/ACM and Mass Storage) support
for mpfs board. In addition, a number of USB fixes are included:

 - Support for Setup Out packets
 - Proper support for larger than packet size writes
 - Finishing setup packets properly

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-06-09 20:44:40 +08:00
Jukka Laitinen
b7a1b75a3b arch/risc-v/src/mpfs/mpfs_start.c: Don't boot if DDR is enabled and training fails
Output "X" with showprogress and make a system reset.

Silently ignoring failed training is dangerous and will cause random behaviour if DDR is used

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-06-09 09:36:38 -03:00
Abdelatif Guettouche
326183bbbc esp32c3/Kconfig: Remove duplicate wireless config
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-06-09 20:19:35 +08:00
Xiang Xiao
f1236da21c fs: Make the binary(no process) mode as the default
POSIX require file system shouldn't enable the \r and \n conversion by default
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-06-07 20:22:26 +03:00
Xiang Xiao
28b25e0391 arch: dump "<noname>" as the task name if CONFIG_TASK_NAME_SIZE equals 0
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-06-07 20:17:23 +03:00
Xiang Xiao
2b2830c252 arch/assert: Replace twice strlcpy with single snprintf
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-06-07 20:17:23 +03:00
Xiang Xiao
b02db04e00 arch/assert: Keep the thread dump column order same as ps
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-06-07 20:17:23 +03:00
Xiang Xiao
c52a19c8dc arch: Include nuttx/tls.h in *_assert.c
to avoid error: "invalid use of undefined type 'struct task_info_s'

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-06-07 20:17:23 +03:00
ligd
118fd3902c dump_task: also dump thread param when dump thread name
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-06-07 20:17:23 +03:00
Richard Tucker
2b8c59fcf1 arch/risc-v/litex: fix typo 2022-06-04 17:04:42 +03:00
Xiang Xiao
11e1a8b28b arch: Define WCHAR_[MIN|MAX] in arch/include/limits.h
follow up the below change:
commit 6357523892
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
Date:   Mon Nov 1 12:40:51 2021 +0800

    arch: Add _wchar_t typedef like other basic types

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-06-03 22:25:49 +03:00
Richard Tucker
85af65e72e arch/risc-v: re-add missing riscv_udelay source
This was broken with: 9d9d591b93
2022-06-03 16:39:30 +08:00
zhanghongyu
035d925864 devif: remove all devif_timer
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
2022-06-02 20:11:50 -03:00
Huang Qi
9d9d591b93 arch/risc-v: Unify common source include
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-05-31 07:59:33 +03:00
Huang Qi
eb02528a39 arch/risc-v/qemu-rv: Fix a typo in Make.defs 2022-05-30 19:58:43 +08:00
Huang Qi
571e66d03f arch/risc-v: Remove unused rv32m1_vectors.S
Since it had been merged into rv32m1_head.S

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-05-30 19:58:43 +08:00
Xiang Xiao
7ec6b4c7dd Change dpends on SCHED_[L|H]PWORK to SCHED_WORKQUEUE
since the code could map the unsupported work to the
supported one and remove select SCHED_WORKQUEUE from
Kconfig since SCHED_[L|H]PWORK already do the selection

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-28 18:41:51 +03:00
chao.an
3f65b562bb arch: inline up_interrupt_context()
inline the up_interrupt_context() to avoid unnecessary stack pushes

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-05-26 04:36:07 +08:00
Gustavo Henrique Nihei
18d74dbea0 risc-v/esp32c3: Fix leak of semaphores created by Wi-Fi kernel thread
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-05-25 09:46:30 +09:00
Gustavo Henrique Nihei
b2d77c0e9c Revert "risc-v/esp32c3: Use onexit to free thread private semaphore"
This reverts commit f5eaf82c93.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-05-25 09:46:30 +09:00
Eero Nurkkala
3ea7d4bab4 risc-v/mpfs: amend OpenSBI to utilize IHC
Linux kernel uses M-mode trap for handling Inter-Hart Communication (IHC).
This patch provides all the required functionalities for this purpose.
Previously, HSS bootloader was required. Now, NuttX is run as the
bootloader providing OpenSBI vendor extensions instead. This setup has
been tested on the following configuration:

 - Hart 0 has NuttX in bootloader mode with OpenSBI
 - Hart 1 unused
 - Hart 2 has NuttX configured at 0xa2000000
 - Hart 3 has U-boot / Linux kernel (at 0x80200000)
 - Hart 4 has U-boot / Linux kernel (at 0x80200000)

Upon startup, NuttX on hart 0 will initialize SD-card driver, loads
the hart 2 NuttX from the SD-card and loads the U-boot to 0x80200000.
Also the nuttx.sbi -binary is loaded from SD-card into address 0x80000000,
which is also marked as reserved area in the Linux kernel device tree (for
the chuck 0x80000000 - 0x80200000).

Hart 2 NuttX waits until Linux kernel (IHC master) is started. After the
initial handshake, RPMsg / virtIO bus along with the IHC may be used for
proper AMP mode.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-05-24 03:25:37 +08:00
Masayuki Ishikawa
84bcb075d7 arch: risc-v: Fix crt0.c if CONFIG_HAVE_CXX is not set
Summary:
- I noticed that rv-virt:knsh64 crashes when it executes the init.
- This commit fixes this issue.

Impact:
- None

Testing:
- Tested with rv-virt:knsh64

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-05-23 21:19:01 +08:00
Ville Juven
621062dc1d MPFS: Implement S-mode head and start function
- Remove S-mode initializations from the M-mode head file, they are not
  required
- Writing mstatus->tvm from S-mode will result in illegal instruction
2022-05-22 15:42:30 +03:00
YAMAMOTO Takashi
c60bb81387 esp32c3: Implement up_textheap_heapmember 2022-05-20 21:16:42 +08:00