Commit Graph

14700 Commits

Author SHA1 Message Date
Xiang Xiao
1cd9fa25cd arm/tlsr82xx: Don't select ARCH_HAVE_BACKTRACE
since it's already selected by ARCH_ARM

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-10-11 00:01:35 +02:00
chao an
24129e4ba7 arm/backtrace: add support for EHABI(Exception Handling ABI) stack unwinder
Reference:
https://github.com/ARM-software/abi-aa/blob/main/ehabi32/ehabi32.rst
https://github.com/ARM-software/abi-aa/releases/download/2022Q1/ehabi32.pdf

Signed-off-by: chao an <anchao@xiaomi.com>
2022-10-11 03:11:37 +08:00
Andrés Sánchez Pascual
c28b05efd3 arch: stm32h7: Add support for dual bank flash
memory

Signed-off-by: Andrés Sánchez Pascual <tito97_sp@hotmail.com>
2022-10-10 01:07:45 +08:00
Xiang Xiao
f813fea555 Fix chip/cxd56_gnss.c:2858:7: error: label 'err' used but not defined
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-10-04 20:59:30 +02:00
Xiang Xiao
e38248ee08 Return -EINVAL for the internal API
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-30 17:54:56 +02:00
Xiang Xiao
bdeaea3742 Remove the unnessary empty line after label
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-30 17:54:56 +02:00
Carlos Sanchez
6e490759d6 s32k1xx: Fix FlexIO timer register access macros 2022-09-30 23:38:59 +08:00
Carlos Sanchez
68db81ab4f s32k1xx: Allow building with debug features and no console. 2022-09-30 15:15:55 +02:00
Xiang Xiao
53dcddc9e3 arch/armv[7|8]-m: Implement up_invalidate_icache
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-30 08:07:45 +02:00
chao an
6bc4baa4ca arch/makefile: preprocess link script to make configure more flexibly
Signed-off-by: chao an <anchao@xiaomi.com>
2022-09-29 17:06:47 +08:00
yinshengkai
5c9b094d65 tools: Replace mkallsyms.sh with mkallsyms.py
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2022-09-29 08:33:04 +08:00
Fotis Panagiotopoulos
bbf3f2866d Fixed non-UTF8 characters. 2022-09-28 09:38:55 +08:00
ligd
078a0486f5 armv7-a: SMP hande all cores start at same time
In SMP mode, if all cores start at same time, all from __start(),
then only primary need do initialize, so others core should wait
primary, use 'sev' let the non-primary continue to __cpuN_start().

Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-09-28 10:33:13 +09:00
wangbowen6
589647308c arm/tlsr82: move peripherals pin config to board.h
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2022-09-28 09:30:06 +08:00
Xiang Xiao
764540267e sched/clock: Rename g_system_timer to g_system_ticks
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-27 17:45:44 -03:00
ligd
059497d1d1 armv7-a/r: NON-primary core should invalidate dacache level1
NON-primary cpu will invalidate cpu0's cache L2, that will caused cpu0's data mismatch, and then system crash

Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-09-27 14:41:39 +08:00
David Sidrane
a1ebd499ea stm32h7:SDMMC fix unaligned access for buffers not on 32 bit boundaries
The IDMA needs to have 32 bit word alignment, in fact it will
   AND off the lower 2 bits of the value stored in IDMABASE0R.
   This bug was masked by CONFIG_ARMV7M_DCACHE causing proper word alignment
   and also FAT_DMAMEMORY being aligned.

   This commit extends the unaligned logic (used for dcache) to take into account
   the need for a buffer copy when the buffer is ot 32 bit word.

    It leverages the fact that when CONFIG_ARMV7M_DCACHE is not defined the up_xxxxx_dcache are nops.
2022-09-27 09:43:29 +08:00
Rajvinder Kaur
2e1c522a79 stm32h7\stm32_fdcan_sock: reserve space for timeval struct in the intermediate storage of tx and rx CAN frames when timestamp is enabled 2022-09-26 20:05:44 -03:00
chao an
aa51629bd2 arm/armv7-r: redefine the linker symbols as armlink style
Fix build break:

Error: L6218E: Undefined symbol _sbss (referred from arm_head.o).
Error: L6218E: Undefined symbol _ebss (referred from arm_head.o).
Error: L6218E: Undefined symbol _eronly (referred from arm_head.o).
Error: L6218E: Undefined symbol _sdata (referred from arm_head.o).
Error: L6218E: Undefined symbol _edata (referred from arm_head.o).

Signed-off-by: chao an <anchao@xiaomi.com>
2022-09-26 19:04:25 +02:00
chao an
a2cd1b0db3 arm/armlink: add support of link time optimization(lto)
Optimization goal(Code size)

Smaller                           GCC(-Os) GCC(-flto -Os) CLANG(-flto -Oz) ARMCLANG(-flto -Oz/-Omin)
lm3s6965-ek/qemu-flat(Cortex-M3)   208662      193893           199525             195464
                                               -7.07%           -4.37%             -6.32%
sabre-6quad/smp(Cortex-A9)         131360      122500            N/A               123988
                                               -6.74%            N/A               -5.61%

Faster performance                GCC(-O3) GCC(-flto -O3) CLANG(-flto -Ofast) ARMCLANG(-flto -Ofast) ARMCLANG(-flto -Omax)
lm3s6965-ek/qemu-flat(Cortex-M3)   257502      296364           369465             346696                  384204
                                              +15.00%          +43.40%            +34.60%                 +49.20%
sabre-6quad/smp(Cortex-A9)         166520      196004             N/A              207908                  224140
                                              +17.70%             N/A             +24.85%                 +34.60%

Reference:
https://developer.arm.com/documentation/101754/0618/armclang-Reference/armclang-Command-line-Options/-O--armclang-

Signed-off-by: chao an <anchao@xiaomi.com>
2022-09-26 18:23:27 +08:00
Xiang Xiao
40ef5bc6db libc: Move queue.h from include to include/nuttx
to avoid the conflict with libuv's queue.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-26 08:04:58 +02:00
wangbowen6
344c8be049 poll: add poll_notify() api and call it in all drivers
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2022-09-26 12:06:32 +08:00
Xiang Xiao
70290b6e38 arch: Change the linker generated symbols from uint32_t to uint8_t *
and remove the duplicated declaration

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-24 21:26:56 +02:00
Masayuki Ishikawa
95fe8426ed arch: lc823450: Fix to boot
Summary:
- I noticed that lc823450-xgevk does not boot due to the recent
  changes on g_current_regs
- This PR fixes this issue

Impact:
- None

Testing:
- Tested with lc823450-xgevk:rndis

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-09-24 21:59:32 +08:00
chao an
b134995d92 arm/tlsr82: replace incompatible instruction sets to internal implement
1. some arm instructions are not compatible with arch tlsr:

{standard input}: Assembler messages:
{standard input}:53: Error: bad instruction `svc #0'

2. remove unsupport compile option

cc1: error: unrecognized command line option "-mlittle-endian"
Signed-off-by: chao an <anchao@xiaomi.com>
2022-09-23 23:54:25 +08:00
chao an
47b350a4c3 arch/arm: declare vector array default type to read-only
Reference:
https://developer.arm.com/documentation/dui0474/m/image-structure-and-generation/section-placement-with-the-linker/section-placement-with-the-first-and-last-attributes

CAUTION:
FIRST and LAST must not violate the basic attribute sorting order. For example, FIRST RW is placed after any read-only code or read-only data.

arm-none-eabi-readelf -aS arm_vectors.o
1. Without const:
  Section Headers:
  [Nr] Name              Type            Addr     Off    Size   ES Flg Lk Inf Al
  [ 3] .vectors          PROGBITS        00000000 000034 00011c 00  WA  0   0  4

2. const symbol:
  [ 3] .vectors          PROGBITS        00000000 000034 00011c 00   A  0   0  4

Regression by:

| commit 229b57d6cb
|
|     arch/armv[6|7|8]-m: Move _vectors to arm_internal.h to avoid the duplication
|
|     and change the type of _vectors from uint32_t to const void *
|
|     Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>

Signed-off-by: chao an <anchao@xiaomi.com>
2022-09-23 22:28:51 +08:00
chao an
c07d076bf5 arch/arm: redefine the linker symbols as armlink style
Signed-off-by: chao an <anchao@xiaomi.com>
2022-09-23 22:28:07 +08:00
chao an
bb63e1b23d arm/cortex-r: correct include path of chip.h
In file included from ./armv7-r/arm_l2cc_pl310.c:41:
./armv7-r/l2cc_pl310.h:38:10: fatal error: chip/chip.h: No such file or directory
   38 | #include "chip/chip.h"
      |          ^~~~~~~~~~~~~

Signed-off-by: chao an <anchao@xiaomi.com>
2022-09-23 13:54:03 +08:00
simbit18
4d7c15af5c arch/arm: fix conditional compilation term (#else)
Code fixing for the conditional compilation term (#else)
2022-09-23 01:36:08 +08:00
simbit18
d35307dacd stm32wl5/stm32wl5_rcc.h
fix conditional compilation term (#else)
2022-09-22 17:17:18 +02:00
chao an
59499c0bb2 arch/arm: fallback to common toolchain if armeb(endian big) is unavailable
Signed-off-by: chao an <anchao@xiaomi.com>
2022-09-22 22:19:05 +08:00
Michal Lenc
9ebd7e525c imxrt: add support for ADC triggering by an external signal
Config option IMXRT_ADCx_ETC can now be used to select an external HW
trigger to be used instead of continous trigger. Continous trigger is
used if IMXRT_ADCx_ETC = -1 (default option). Otherwise the source signal
is routed through XBAR and used as a trigger.

Hardware triggering is currently limited to maximum of 8 channels.
HW trigger is automatically disabled if there are more than 8 channels.

The external triggering was tested with PWM signal as a source.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2022-09-22 22:13:56 +08:00
simbit18
5a085176fe stm32u5/stm32_rcc.h
fix conditional compilation term (#else)
2022-09-22 21:27:09 +08:00
Xiang Xiao
3c1c29f2c4 arch: move non arm g_current_regs defintion to common place
to avoid the code duplicaiton

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-21 22:23:11 +02:00
Xiang Xiao
229b57d6cb arch/armv[6|7|8]-m: Move _vectors to arm_internal.h to avoid the duplication
and change the type of _vectors from uint32_t to const void *

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-21 22:23:11 +02:00
Amir Melzer
6274e19257 fix conditional compilation term (#else) 2022-09-21 15:57:05 -03:00
chao an
fb4c593e89 armv7-r/tms570: fix build break
1.
make[1]: *** No rule to make target 'tms570_spi.c', needed by '.depend'.  Stop.

2.
In file included from armv7-r/arm_gicv2.c:36:
armv7-r/gic.h: In function 'arm_gic_nlines':
armv7-r/mpcore.h:63:29: error: 'CHIP_MPCORE_VBASE' undeclared (first use in this function)
   63 | #define MPCORE_ICD_VBASE   (CHIP_MPCORE_VBASE+MPCORE_ICD_OFFSET)
      |                             ^~~~~~~~~~~~~~~~~

Signed-off-by: chao an <anchao@xiaomi.com>
2022-09-22 02:22:18 +08:00
Nathan Hartman
ac20a5c0d6 Remove executable permissions from source files 2022-09-22 01:59:48 +08:00
chao an
de1ad746d8 arm/armv7-r: remove incorrect include header "addrenv.h"
since armv7-r does not support kernel mode

./armv7-r/arm_syscall.c:36:10: fatal error: addrenv.h: No such file or directory
   36 | #include "addrenv.h"
      |          ^~~~~~~~~~~

Signed-off-by: chao an <anchao@xiaomi.com>
2022-09-22 01:35:03 +08:00
Masayuki Ishikawa
ae378872c2 arch: armv7-a: Remove the code for CONFIG_ARCH_PGPOOL_MAPPING=n
Summary:
- Currently, CONFIG_ARCH_PGPOOL_MAPPING=y is necessary for
  CONFIG_BUILD_KERNEL=y.
- This commit removes the code for CONFIG_ARCH_PGPOOL_MAPPING=n

Impact:
- None

Testing:
- Tested with sabre-6quad:netknsh_smp

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-09-21 19:57:27 +08:00
ligd
6903f02d41 armv7-r: add VBAR cp15 opearation
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-09-21 18:07:03 +08:00
ligd
3477c347e8 armv7a/r: add isb to cp15_invalidate_icache()
Incase invalidate_icache hasn't done

Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-09-21 18:07:03 +08:00
ligd
6d92810d5a armv7a/r: refact cp15_cache functions
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-09-21 18:07:03 +08:00
ligd
c866b6be9a armv7a/r: add common operation CP15_SET/GET()
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-09-21 18:07:03 +08:00
licheng
25d5cd11a1 mmu: mmu enable should after enable SMP
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-09-21 09:39:41 +08:00
Michal Lenc
11cf3de776 imxrt: disable PWM synchronization when XBAR connection fails
This commit supplements commit 7d877fbb. External sync mode is now
disabled if XBAR connection fails and config options are used directly
in sync_src variable and passed to XBAR macro only when needed. The first
option could caused an undefined behaviour when sync_src was equal to -1
(external sync not used)

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2022-09-21 04:53:57 +08:00
klmchp
711681a90d add SAMA5D2 support for sam_xdma driver 2022-09-21 00:14:41 +08:00
Xiang Xiao
079a6fa6cc arch/armv7[a|r]: Implement up_affinity_irq
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-20 16:20:17 +09:00
Xiang Xiao
17ac85eb0a arch/armv7[a|r]: Support non SGI in up_trigger_irq
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-20 16:20:17 +09:00
Xiang Xiao
ef43283c67 arch/arm: Unify arm_cpu_sgi to up_trigger_irq
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-20 16:20:17 +09:00