1 move fpu register to XCP_REGS
2 move save & restore fpu register to context_save/restore
Consistency with other archs.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
PR#6249 was already merged without the review fixes. Provide the
fixes here on a separate patch.
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Summary:
- This commit adds MMU support for qemu-rv
- Please note that mtimer is disabled for S-mode because
the mtimer needs to be accessed in M-mode
Impact:
- qemu-rv only
Testing:
- Tested with rv-virt:knsh64 (will be pushed later)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This provides an example of Asymmetric Multiprocessing (AMP). The
master from Linux sends pings that this NuttX echoes back. The system
uses RPMsg from OpenAMP.
The Inter-Hart Communication module is present in the vendor's software
stack with the tag "2021.11". The software is present on github at the
polarfire-soc project. The following conditions must be met:
1. FPGA programmed with 2021.11 software
2. HSS (Vendor bootloader) with 2021.11 software
3. U-boot and Linux kernel from 2011.11 software
Currently the IHC works as a slave only on the hart number 4.
On the NuttX side, this patch uses rptun that incorporates rpmsg and
virtio. If it used only rpmsg and virtio, the future maintenance would
likely be much heavier. Using rptun also simplifies many things.
Upon success, the master side from Linux may issue an example test:
root@icicle-kit-es-amp:/opt/microchip/amp/rpmsg-pingpong# ./rpmsg-pingpong
However, the rpmsg-pingpong.c (compiled on target with gcc), may need to
be modified as seen below to match the device id:
- char *rpmsg_dev="virtio0.rpmsg-amp-demo-channel.-1.0";
+ char *rpmsg_dev="virtio0.rpmsg-amp-demo-channel.-1.1024";
This work uses a separate linker script. Due to a bug yet unknown to date,
a small NuttX, when loaded by the vendor HSS bootloader, will cause the
Linux kernel to hang at boot. Thus, the binary size is increased with
a section 'filler_area' whose only purpose is to increase the image size
so that the Linux kernel will boot up.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Implement a generic access rights modification procedure instead
of the procedures that only do one thing (enable/disable write)
to one section (text).
1. using armv6-m arm_irq();
2. simplify the interrupt number get process;
3. To improve the performance, move common exception code to ram_code.
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
fix warning:
common/arm_createstack.c: In function 'up_create_stack':
common/arm_createstack.c:154:11: warning: format '%d' expects type 'int', but argument 3 has type 'size_t'
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
Summary:
- Because a context switch issue still exists with FPU,
it should be enabled only if EXPERIMENTAL=y
Impact:
- None
Testing:
- Tested with ostest
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
1. add pulse count support for pwm0;
2. add more detailed config for pwm;
3. pwm configuration and start process optimize;
4. tlsr82/Kconfig format;
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
Summary:
- TIVA_WITH_QEMU is used to run the NuttX with QEMU
- The configuration should not depend on TIVA_ETHERNET
- This commit fixes this issue
Impact:
- None
Testing:
- Tested with QEMU
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
_xtensa_sig_trampoline is returned to after a context switch and not called
by the usual Window call instructions (call4, call8 and call12),
thus does not need the entry instruction. Furthermore, the ENTRY instruction
in this case is messing up the backtrace as it creates an extra frame.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
to generate more information for profile feedback optimization
and remove -lgcov from STDLIBS since gcc/clang will automatically
add the profile help lirary(triggered by -fprofile-generate).
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Summary:
- In case of SMP and ADDRENV, allocate the page table for each cpu
- Each cpu holds separated addrenv and MMU setting
Impact:
- armv7-a
Testing:
- sabre-6quad:smp w/ qemu
- sabre-6quad:knsh w/ qemu
- sabre-6quad:knsh_smp w/ qemu (WIP)
Signed-off-by: Oki Minabe <minabe.oki@gmail.com>
Note that pinmap.h, irq.h, fdcan.h still need to be updated with proper
register definitions for the FDCAN3 peripheral present in
STM32H7[2|3][3|5] MCUs
