arch/arm/src/tiva/cc13xx: Trim code now kind of looks like NuttX code. But does not yet compile.
arch/arm/src/tiva/cc13xx: The first few, feeble steps toward getting the overall trim files compatible with the requirements of the NuttX coding standard.
arch/arm/src/tiva/cc13xx: Replace last of TI hardware access macros with NuttX hardware access macros.
arch/arm/src/tiva/cc13xx: Change TI HWREGB to NuttX getreg8 or putreg8 in trim logic.
arch/arm/src/tiva/cc13xx: Change TI HWREGBITW to NuttX getreg32/putreg32 sequence in trim logic.
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h: Completes the DDIO OSC header file.
cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h: Updated, but still not finished.
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h: Add DDI0 OSC header file. Still a work in progress. Does not yet conform to the NuttX coding standard.
Change _M and _S to _MASK and _SHIFT.
Some minor improvements.
Clean up typos in some comments.
Run all new files against tools/indent.sh
arch/arm/src/tiva/cc13xx: Bring in trim files from SDK. Convert to C-style comments, lowercase hex contants. Remove Windows-style line endings.
drivers/power/bq2425x.c: The Battery Charger expects a battery_charger_dev_s not battery_charger_operations_s
drivers/power/bq2429x.c: The Battery Charger expects a battery_charger_dev_s not battery_charger_operations_s
1. lost data when receiving buffer is full;
2. low-water mask implement issue;
3. re-flush cdc buffer when enabling
4. serial dma is conflict with cdc , modify the serial.h
1. Configurable option to use named config items instead of enumerated ID/Instance numbers.
2. Ability to iterate through the existing configdata items in the /dev/config device.
3. Ability to "unset" a configdata item.
4. Ability to perform "flash_eraseall" on the /dev/config device.
sixlowpan: Fixes logic surrounding the Universal/Local bit. This bit represents whether the IID is locally/globally administered. The U/L bit is bit 1 of the MSB of the EUI-64. It should only be inverted in cases where there is a full EUI-64. In cases whe
* sixlowpan: Fixes logic surrounding the Universal/Local bit. This bit represents whether the IID is locally/globally administered. The U/L bit is bit 1 of the MSB of the EUI-64. It should only be inverted in cases where there is a full EUI-64. In cases where the IID is derived from say, a short address, this bit should be forced to 0, indicating that it is locally administered.
See:
https://tools.ietf.org/html/rfc4291#section-2.5.1https://tools.ietf.org/html/rfc4944#section-6https://tools.ietf.org/html/rfc2464#section-4
* sixlowpan: Account for endianness with U/L bit.
Approved-by: GregoryN <gnutt@nuttx.org>
arch/arm/src/tiva/hardware/cc13x0/cc13x0_fcfg1.h: Adjust cloned CC13x9 FCFG1 header file so that it reflects reality.
arch/arm/src/tiva/hardware/cc13x0/cc13x0_fcfg1.h: Add CC13x0 FCFG1 header file. Initial commit is the same as the CC13x2/CC26x2 FCFG1 header with a few name changes.
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_fcfg1.h: Initial FCFG1 header file for the cc13xx/cc26xx family.
The user of this invalidation are mmcsd_sdio currently. The mmcsd_sdio driver makes calls for dcache invalidation through the chip specific architecture function SDIO_DMARECVSETUP(). I changed the arch/arm/stm32f7 chips to use arch_invalidate_dcache_by_addr() instead of arch_invalidate_dcache().
This commit includes additional changes to mmcsd_sdio.c. I created SDIO_DMADELYDINVLDT() (DMA delayed invalidate) to invalidate store-into mode dcaches after the DMA transfer. I have been using SDIO_DMADELYDINVLDT() for several weeks now and it has fixed the problems that I previously reported regarding non-cache aligned buffer invalidation errors (for my store-through dcache). However, it does not permit use of unaligned DMA buffers for store-into mode dcaches.
SDIO_DMADELYDINVLDT() is a NoOp unless the chip specific Kconfig file selects CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT. I have modified all the stm32f7 chips to select it.
