Commit Graph

1090 Commits

Author SHA1 Message Date
Eero Nurkkala
a1ff841ca4 risc-v/mpfs: ihc: don't use semaphores with OpenSBI vendor calls
OpenSBI vendor extension calls must not cause scheduling, as they're
part of M-mode trap handling. Thus, comment out nxsig_usleep() as
well, which is occasionally taken and crashes the system in that
case. Fix this by commenting out lines that have the potential to
cause scheduling.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-08-17 18:33:32 +08:00
Masayuki Ishikawa
548540eb13 arch: qemu-rv: Fix high CPU usage in SMP mode
Summary:
- I noticed that QEMU shows high CPU usage if the number of
  CPUs does not match the kernel configuration. (e.g. -smp 8
  and CONFIG_SMP_NCPUS=2)
- This commit fixes this issue.

Impact:
- qemu-rv only

Testing:
- Tested with the following configs
  - rv-virt:smp64 (CONFIG_NCPUS=1/2/8)
  - rv-virt:nsh64

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-08-13 22:41:42 +03:00
Xiang Xiao
2b37909c9e libc: Move crc8.h, crc16.h and crc32.h from include to include/nuttx
to avoid the conflict with the 3rd party library

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-08-13 13:28:24 +03:00
Ville Juven
b8b541fbf5 mpfs: Remove the ddrstorage section from the OpenSBI package
It is not really needed; g_hart_stacks is only used during SBI init as
a temporary stack area. We can use the scratch area buffers for this, as
the scratch areas define almost 4K of extra space, which is used for
exception stacks anyway.
2022-08-10 10:01:47 +03:00
Ville Juven
60042fea74 risc-v: Implement riscv_sbi_set_timer
This implements riscv_sbi_set_timer. This requires the OpenSBI companion
software to work (but this is needed by the kernel mode anyways).
2022-08-10 02:02:39 +08:00
Ville Juven
31bb362aab risc-v: Fix kernel MMU mapping for L3 table
The L3 table address was calculated incorrectly. For every 2MiB of
mapped memory, an offset of 4KiB is needed from the base of the L3
table. The old calculation failed if paddr was not aligned to a 2MiB
boundary.
2022-08-09 23:14:46 +08:00
Petro Karashchenko
b3cd9090d1 drivers/net: make sure that net driver d_buf is 16-bit aligned
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-08-05 22:21:37 +08:00
Xiang Xiao
c61381da56 arch/risc-v: Fix error: invalid application of 'sizeof' to incomplete type 'struct tls_info_s'
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-08-05 08:45:11 +03:00
Nathan Hartman
20bdd44e7b Remove executable permission from source and build files. 2022-08-04 12:48:18 -03:00
Eero Nurkkala
e0291b1ce8 risc-v/mpfs: usb: configure fifos properly
RX_FIFO_ADDRs and TX_FIFO_ADDR were misconfigured. These addresses
overlapped causing data corruption during high USB loads. For
example, data corruption was present during the following conditions:

  1. Composite USB driver was used (CDC/ACM + Mass storage)
  2. /dev/ttyACM0 was accessed instantly from Linux side when
     starting up.
  3. Training data was sent to /dev/ttyACM0 from NuttX from the
     very beginning periodically.

It was observed that while Mass storage was negotiating, sometimes
data sent from NuttX to Linux via CDC/ACM was corrupt, although it
was sent properly on the TX fifo.

Also, don't access TXCSRL_REG_EPN_TX_FIFO_NE_MASK for EP0 as it's
not applicable.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-08-03 23:44:12 +08:00
ligd
8c1fd1df81 rptun: update rptun to openamp 2022.04.0
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-08-03 01:22:53 +08:00
zhuyanlin
031c89db89 power: add PM_IDLE_DOMAIN to pm.h and remove definations
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-07-29 11:15:40 +08:00
Xiang Xiao
13a7ae3d06 arch: Call board_reset before up_irq_save and spin_trylock
since board_reset may call some kernel functions which try
to acquire the lock again

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-28 08:18:24 -04:00
Masayuki Ishikawa
1742b7f6a4 arch: risc-v: Fix warnings in common/crt0.c
Summary:
- This commit fixes warnings in common/crt0.c

Impact:
- None

Testing:
- Build only

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-07-27 23:22:23 +08:00
Jiuzhu Dong
9d4549d48b arch: limit output maximum size stackdump when sp is not within stack
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2022-07-27 20:48:33 +08:00
Jiuzhu Dong
136b1d6d42 arch: using remain to ignore invalid stack content when sp is not within stack
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2022-07-27 20:48:33 +08:00
Jiuzhu Dong
91d8ed319e arch/riscv: optimize stackdump
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2022-07-27 20:48:33 +08:00
Jiuzhu Dong
5c8fd46126 arch/stack: rename do_stack_check with arch prefix
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2022-07-27 20:48:33 +08:00
Jiuzhu Dong
79597d0caf arch/up_stack_check: using running_task to get correct task context
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2022-07-27 20:48:33 +08:00
ligd
8a3683fb9f rptun: add ns_match callback to resolve rptun deadlock
thread A: accept -> net_lock -> socket_rpmsg_accept
          -> rpmsg_register_callabck -> rptun_lock
thread B: ns_bind -> rpmsg_socket_ns_bind -> get_tx_payload_buffer
          -> rptun_wait_tx -> usrsock_rpmsg_ept_cb -> usrsockdev_write
          -> net_lock -> deadlock

fix:
add ns_match callback

Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-07-27 20:36:51 +08:00
Jouni Ukkonen
e268b23142 OpenSBI: Add configurable support for domain init
Initialize .domains_init function entry point in sbi_platform_operations when
CONFIG_OPENSBI_DOMAINS=y. In this case, the board specific code must provide
the "board_domains_init" function.

Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2022-07-22 19:00:33 +03:00
Abdelatif Guettouche
ae1cbc47ef esp32&c3/Kconfig: CONFIG_ESP32(C3)_WIRELESS doesn't need to be user
selectable.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-07-20 22:02:28 +03:00
Abdelatif Guettouche
20c6996e81 esp32c3/Kconfig: Don't select options already selected.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-07-20 22:02:28 +03:00
Xiang Xiao
2166c98809 Add printflike and scanflike to all printf/scanf like functions
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-18 14:14:36 +03:00
Xiang Xiao
aad5fbd2fb arch: Add up_nputs function to handle the non '\0' string correctly
and change up_puts as a simple macro

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-17 17:31:19 +03:00
Gustavo Henrique Nihei
e24621d545 arch: Convert DEBUGASSERT(false) into more intuitive DEBUGPANIC()
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-14 12:08:45 +08:00
Gustavo Henrique Nihei
8a4c9c3489 arch: Fix typo in "register" word
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-13 22:57:19 +03:00
Eero Nurkkala
14447600ac risc-v/mpfs: usb: fix illegal reads
With faster data transfer rates, it was seen that the read
requests occasionally were issued while the USB RX operation
was actually in progress.  This patch makes sure the system
doesn't accidentally read the RX fifo while it's being filled
up, but rather, checks for the RXCSRL_REG_EPN_RX_PKT_RDY_MASK
flag.  This flag indicates the packet is ready to be read.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-07-12 18:34:28 +08:00
Gustavo Henrique Nihei
5e32aa14bf risc-v/esp32c3: Fix verification of ROM function return values
cache_dbus_mmu_set and cache_ibus_mmu_set return positive values in case
of errors, so DEBUVERIFY could never detect them since this macro checks
for negative values.
Besides, the successful execution of those functions is mandatory for
the reliable operation under Protected Mode, so the verification is
always performed, even when DEBUG is not enabled.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-12 10:56:59 +08:00
Nathan Hartman
849f760b77 Fix various typos 2022-07-08 02:15:54 +08:00
Abdelatif Guettouche
0bdf713df0 risc-v/esp32c3: Add the rest of the reset causes.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-07-08 01:06:35 +08:00
Xiang Xiao
3daa18b661 arch: Remove the unnecessary #if/#endif in assert
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-07 19:25:47 +03:00
Xiang Xiao
9ff0971d3f arch: Correct the order of stack related information in assert
forget to update in this patch:
commit b02db04e00
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
Date:   Sun Jun 5 17:10:19 2022 +0800

    arch/assert: Keep the thread dump column order same as ps

    Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-07 19:25:47 +03:00
Xiang Xiao
9ab3417882 arch/risc-v: Move __XSTR, FLOAD/FSTORE and REGLOAD/REGSTORE to the right place
1.Move __XSTR from include/arch.h to include/irq.h
2.Move  FLOAD/FSTORE and REGLOAD/REGSTORE from include/arch.h to src/common/riscv_internal.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-04 13:25:56 +03:00
Xiang Xiao
c20ed58879 arch: Remove the inclusion of arch/irq.h from chip/irq.h
since arch/irq.h will include chip/irq.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-04 13:03:47 +03:00
Xiang Xiao
3d1ce144df arch: Move up_getsp from arch.h to irq.h
since all other special register operation in irq.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-01 10:44:55 -03:00
Gustavo Henrique Nihei
5ce77fad1b arch: Remove "0x" prefix preceding "%p" specifier on format string
The "p" format specifier already prepends the pointer address with "0x"
when printing.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-06-30 22:08:58 +03:00
Eero Nurkkala
ef28d915fe risc-v/mpfs: ihc: don't start rptun automatically
Starting the rptun with the autostart flag set will cause significant
delays at the boot, as it will wait for the master to be up. U-boot/linux
combination may take more than 10 seconds to boot to the point where the
rpmsg bus is initialized.

For now, the user needs to initialize the rptun separately, for example,
by issuing the following command:

  rptun start /dev/rptun/mpfs-ihc

This command will also block if started before the rpmsg bus master is up.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-06-28 11:34:38 -03:00
Ville Juven
cfebb5a5c1 risc-v: Move common memory map to its own file from riscv_internal
Move the linker defined symbols to a separate file, so they can be
accessed without pulling in everything from riscv_internal.h and
whatever it includes (e.g. syscall.h drags in a lot).
2022-06-28 14:41:56 +03:00
Nimish Telang
4afd25b567 this flag is meaningless for the linker 2022-06-27 20:03:03 -03:00
Ville Juven
77a01cfe52 mpfs: Fix IHC memory locations to native width type
Ne numeric type defaults to u32 which is not enough to represent a
native memory location

This fixes build error:
https://github.com/apache/incubator-nuttx/runs/7067877053?check_suite_focus=true
2022-06-27 20:49:00 +08:00
Jukka Laitinen
ba1b8d0712 arch/risc-v/src/mpfs: Add mpfs_gpiosetevent and gpio irq handling functions
Add a function to easily enable event handling on fabric and mss gpios. This
is similar to what exists e.g. for stm32 arm chips.

Also fix some small bugs in mpfs_configgpio related to IRQ bits configuration

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-06-23 21:45:15 +08:00
Eero Nurkkala
92760f89eb risc-v/mpfs: emmcsd: fix two issues
This patch fixes the following issues:
  1. MPFS_EMMCSD_HRS06_EMM bitmask had to be 0x7, not 0x03
  2. putreg32() caused outright memory corruption as the
     arguments were in wrong order

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-06-22 09:50:33 +03:00
Huang Qi
9481456fde risc-v/esp32c3: Implement up_perf_xxx API
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-06-21 21:35:22 +08:00
Richard Tucker
8f36649aad arch/risc-v/src/litex/litex_emac: add liteeth peripheral driver
See the following for details on the pepheral:
https://github.com/enjoy-digital/liteeth
2022-06-21 12:06:37 +03:00
AuroraRAS
0fe219a8c9 Add I2C_M_NOSTART and I2C_M_NOSTOP support in esp32c3_i2c
Signed-off-by: AuroraRAS <chplee@gmail.com>
2022-06-20 10:34:22 -03:00
Ville Juven
6cb77a8d84 mpfs: Allow mapping of RAM/ROM regions from different memory areas
The old implementation needed a contiguous memory block for user
ROM/RAM. This is because there was only 1 L3 page table which can only
map a contiguous memory area.

Also, remove the PMP configuration which just complicates things,
rely on the MMU mappings instead.
2022-06-20 21:24:18 +08:00
Jukka Laitinen
d8cc1fd76d arch/riscv/mpfs: Add a config flag to select SD mux state
This has been previously hard-coded to SD-card. Make it build time configurable.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-06-16 09:17:30 -03:00
Eero Nurkkala
5683e020e8 risc-v/mpfs: update clock configuration parameters
Update PLL configuration parameters to match the values provided
by the vendor.

Also remove extra call to mpfs_pll_config() as it's already called
at mpfs_clockconfig().

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-06-15 21:29:45 +08:00
Masayuki Ishikawa
a0ff6f9fa6 arch: k210: Add a workaround for clock stabilization
Summary:
- I noticed that sometimes uart shows nothing on the maix-bit board.
- This commit adds a workaround to avoid such the issue

Impact:
- k210 only

Testing:
- Tested with maix-bit

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-06-13 11:42:59 +08:00
Norman Rasmussen
e6376c72d7 Fix CONFIG_ALLSYMS for arm, risc-v and xtensa after #5496 2022-06-13 11:39:06 +08:00
Gustavo Henrique Nihei
59da1bc86a risc-v/esp32c3: Disable region protection on IDFboot for Flat build
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-06-11 01:55:46 +08:00
Gustavo Henrique Nihei
5805ad3954 risc-v/esp32c3: Disable access to invalid memory regions using MPU
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-06-11 01:55:46 +08:00
Ville Juven
16286081e1 risc-v/mpfs: Move the entry point to .start section
Remove the object linkage and use an explicit .start section
2022-06-10 20:18:23 +08:00
Eero Nurkkala
39d389545e risc-v/mpfs: usb: add composite support
This provides USB composite (CDC/ACM and Mass Storage) support
for mpfs board. In addition, a number of USB fixes are included:

 - Support for Setup Out packets
 - Proper support for larger than packet size writes
 - Finishing setup packets properly

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-06-09 20:44:40 +08:00
Jukka Laitinen
b7a1b75a3b arch/risc-v/src/mpfs/mpfs_start.c: Don't boot if DDR is enabled and training fails
Output "X" with showprogress and make a system reset.

Silently ignoring failed training is dangerous and will cause random behaviour if DDR is used

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-06-09 09:36:38 -03:00
Abdelatif Guettouche
326183bbbc esp32c3/Kconfig: Remove duplicate wireless config
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-06-09 20:19:35 +08:00
Xiang Xiao
f1236da21c fs: Make the binary(no process) mode as the default
POSIX require file system shouldn't enable the \r and \n conversion by default
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-06-07 20:22:26 +03:00
Xiang Xiao
28b25e0391 arch: dump "<noname>" as the task name if CONFIG_TASK_NAME_SIZE equals 0
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-06-07 20:17:23 +03:00
Xiang Xiao
2b2830c252 arch/assert: Replace twice strlcpy with single snprintf
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-06-07 20:17:23 +03:00
Xiang Xiao
b02db04e00 arch/assert: Keep the thread dump column order same as ps
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-06-07 20:17:23 +03:00
Xiang Xiao
c52a19c8dc arch: Include nuttx/tls.h in *_assert.c
to avoid error: "invalid use of undefined type 'struct task_info_s'

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-06-07 20:17:23 +03:00
ligd
118fd3902c dump_task: also dump thread param when dump thread name
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-06-07 20:17:23 +03:00
Richard Tucker
2b8c59fcf1 arch/risc-v/litex: fix typo 2022-06-04 17:04:42 +03:00
Xiang Xiao
11e1a8b28b arch: Define WCHAR_[MIN|MAX] in arch/include/limits.h
follow up the below change:
commit 6357523892
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
Date:   Mon Nov 1 12:40:51 2021 +0800

    arch: Add _wchar_t typedef like other basic types

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-06-03 22:25:49 +03:00
Richard Tucker
85af65e72e arch/risc-v: re-add missing riscv_udelay source
This was broken with: 9d9d591b93
2022-06-03 16:39:30 +08:00
zhanghongyu
035d925864 devif: remove all devif_timer
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
2022-06-02 20:11:50 -03:00
Huang Qi
9d9d591b93 arch/risc-v: Unify common source include
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-05-31 07:59:33 +03:00
Huang Qi
eb02528a39 arch/risc-v/qemu-rv: Fix a typo in Make.defs 2022-05-30 19:58:43 +08:00
Huang Qi
571e66d03f arch/risc-v: Remove unused rv32m1_vectors.S
Since it had been merged into rv32m1_head.S

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-05-30 19:58:43 +08:00
Xiang Xiao
7ec6b4c7dd Change dpends on SCHED_[L|H]PWORK to SCHED_WORKQUEUE
since the code could map the unsupported work to the
supported one and remove select SCHED_WORKQUEUE from
Kconfig since SCHED_[L|H]PWORK already do the selection

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-28 18:41:51 +03:00
chao.an
3f65b562bb arch: inline up_interrupt_context()
inline the up_interrupt_context() to avoid unnecessary stack pushes

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-05-26 04:36:07 +08:00
Gustavo Henrique Nihei
18d74dbea0 risc-v/esp32c3: Fix leak of semaphores created by Wi-Fi kernel thread
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-05-25 09:46:30 +09:00
Gustavo Henrique Nihei
b2d77c0e9c Revert "risc-v/esp32c3: Use onexit to free thread private semaphore"
This reverts commit f5eaf82c93.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-05-25 09:46:30 +09:00
Eero Nurkkala
3ea7d4bab4 risc-v/mpfs: amend OpenSBI to utilize IHC
Linux kernel uses M-mode trap for handling Inter-Hart Communication (IHC).
This patch provides all the required functionalities for this purpose.
Previously, HSS bootloader was required. Now, NuttX is run as the
bootloader providing OpenSBI vendor extensions instead. This setup has
been tested on the following configuration:

 - Hart 0 has NuttX in bootloader mode with OpenSBI
 - Hart 1 unused
 - Hart 2 has NuttX configured at 0xa2000000
 - Hart 3 has U-boot / Linux kernel (at 0x80200000)
 - Hart 4 has U-boot / Linux kernel (at 0x80200000)

Upon startup, NuttX on hart 0 will initialize SD-card driver, loads
the hart 2 NuttX from the SD-card and loads the U-boot to 0x80200000.
Also the nuttx.sbi -binary is loaded from SD-card into address 0x80000000,
which is also marked as reserved area in the Linux kernel device tree (for
the chuck 0x80000000 - 0x80200000).

Hart 2 NuttX waits until Linux kernel (IHC master) is started. After the
initial handshake, RPMsg / virtIO bus along with the IHC may be used for
proper AMP mode.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-05-24 03:25:37 +08:00
Masayuki Ishikawa
84bcb075d7 arch: risc-v: Fix crt0.c if CONFIG_HAVE_CXX is not set
Summary:
- I noticed that rv-virt:knsh64 crashes when it executes the init.
- This commit fixes this issue.

Impact:
- None

Testing:
- Tested with rv-virt:knsh64

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-05-23 21:19:01 +08:00
Ville Juven
621062dc1d MPFS: Implement S-mode head and start function
- Remove S-mode initializations from the M-mode head file, they are not
  required
- Writing mstatus->tvm from S-mode will result in illegal instruction
2022-05-22 15:42:30 +03:00
YAMAMOTO Takashi
c60bb81387 esp32c3: Implement up_textheap_heapmember 2022-05-20 21:16:42 +08:00
Ville Juven
91063e85f0 risc-v/vfork: FPU was not saved correctly
The FPU register saving upon vfork entry was missing.

Also added macro that tells the actual size of an FPU reg, instead
of just having a coefficient for qfpu/no-qfpu.
2022-05-20 15:59:24 +08:00
Ville Juven
1ec70bc704 risc-v/vfork: Save FPU registers
Save the callee saved FPU registers
2022-05-19 09:05:00 -03:00
Ville Juven
ef42b7c31e risc-v/irq: Add ABI name versions of FPU registers 2022-05-19 09:05:00 -03:00
Ville Juven
ec073d91c7 risc-v/vfork: Save correct amount of registers for vfork
The original code does not obey RISC-V calling conventions, looks like
it was copy&pasted from MIPS instead.
2022-05-19 09:05:00 -03:00
Ville Juven
12476e1f43 RISC-V: add C++ support to crt0 2022-05-19 01:35:36 +08:00
Xiang Xiao
b30e0a26ef Move "-nostartfiles -nodefaultlibs" from Make.defs to Toolchian.defs
and replace "-nostartfiles -nodefaultlibs" with "-nostdlib"

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-18 08:26:02 -04:00
Ville Juven
d7f7867f76 risc-v/opensbi: Generalize the SBI variable handling in makefile
- Remove most of the ifeq-conditions and replace them with variables.
- Move the -I flag for 3rd party headers to opensbi/Make.defs

This clean-up / generalization makes it much simpler to add a new SBI
implementation, without the need to add a bunch of ifeq / elif conditions
to the makefile.
2022-05-18 08:35:04 -03:00
Gustavo Henrique Nihei
4f31c89963 esp32c3-devkit: Rename linker script to indicate use for Flat mode
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-05-18 11:43:52 +08:00
Gustavo Henrique Nihei
c778f35f08 risc-v/esp32c3: Add support for Protected Mode
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-05-18 11:43:52 +08:00
Eero Nurkkala
817919ebb6 risc-v/mpfs: IHC: allow hart configuration
Let the user pick what runs on the harts. For example, the
default configuration now supports NuttX on hart2 and Linux
kernel on harts 3 and 4. Also fix a few issues in the code.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-05-18 01:34:33 +08:00
Xiang Xiao
5958d3ac62 risc-v: Move "LDFLAGS += -melf32lriscv" from Make.defs to Toolchain.defs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-16 11:17:08 +03:00
Xiang Xiao
1f920e55d3 Move warning option from Make.defs to Toolchain.defs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 15:40:35 +03:00
Xiang Xiao
8b7c5b039d arch: Move -fsanitize=kernel-address to ARCHOPTIMIZATION
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 15:40:35 +03:00
Xiang Xiao
1fb8c13e5e Replace nxsem_timedwait_uninterruptible with nxsem_tickwait_uninterruptible
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 13:55:58 +03:00
Xiang Xiao
816ce73ab4 Replace nxsem_timedwait with nxsem_tickwait
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 13:55:58 +03:00
Petro Karashchenko
0fee5a2b84 nuttx: fix typos in comments
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-05-14 23:45:52 +08:00
Eero Nurkkala
0178792a01 risc-v/mpfs: IHC: clarify semaphore usage
g_mpfs_ack_sig and g_mpfs_rx_sig are better used with
SEM_INITIALIZER(0) (signalling) rather than with
SEM_INITIALIZER(1) (mutual exclusion).

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-05-13 19:07:40 +03:00
Eero Nurkkala
0a75a9556d risc-v/mpfs: apply IHC review fixes
PR#6249 was already merged without the review fixes. Provide the
fixes here on a separate patch.

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-05-13 10:38:51 +03:00
Xiang Xiao
1ba316b5c7 arch: Remove board/libboard$(LIBEXT) from the rerequest of export_startup
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-12 23:34:31 +03:00
Xiang Xiao
23200471df arch/riscv: Remove & ~1 before assign signal_handler to REG_EPC
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-12 23:31:50 +03:00
Masayuki Ishikawa
3193aa3c97 arch: risc-v: Add MMU support for qemu-rv
Summary:
- This commit adds MMU support for qemu-rv
- Please note that mtimer is disabled for S-mode because
  the mtimer needs to be accessed in M-mode

Impact:
- qemu-rv only

Testing:
- Tested with rv-virt:knsh64 (will be pushed later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-05-13 04:14:01 +08:00
Eero Nurkkala
77e36d1acc risc-v/mpfs: introduce IHC driver
This provides an example of Asymmetric Multiprocessing (AMP). The
master from Linux sends pings that this NuttX echoes back. The system
uses RPMsg from OpenAMP.

The Inter-Hart Communication module is present in the vendor's software
stack with the tag "2021.11". The software is present on github at the
polarfire-soc project. The following conditions must be met:

 1. FPGA programmed with 2021.11 software
 2. HSS (Vendor bootloader) with 2021.11 software
 3. U-boot and Linux kernel from 2011.11 software

Currently the IHC works as a slave only on the hart number 4.

On the NuttX side, this patch uses rptun that incorporates rpmsg and
virtio. If it used only rpmsg and virtio, the future maintenance would
likely be much heavier. Using rptun also simplifies many things.

Upon success, the master side from Linux may issue an example test:

root@icicle-kit-es-amp:/opt/microchip/amp/rpmsg-pingpong# ./rpmsg-pingpong

However, the rpmsg-pingpong.c (compiled on target with gcc), may need to
be modified as seen below to match the device id:
 - char *rpmsg_dev="virtio0.rpmsg-amp-demo-channel.-1.0";
 + char *rpmsg_dev="virtio0.rpmsg-amp-demo-channel.-1.1024";

This work uses a separate linker script. Due to a bug yet unknown to date,
a small NuttX, when loaded by the vendor HSS bootloader, will cause the
Linux kernel to hang at boot. Thus, the binary size is increased with
a section 'filler_area' whose only purpose is to increase the image size
so that the Linux kernel will boot up.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-05-12 22:56:12 +08:00
wangbowen6
bc61e71b94 crypto: change type uint32_t to size_t in aes_cypher() arguments.
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2022-05-12 22:28:54 +08:00
Ville Juven
47e85b68fe arch/addrenv: Change text write enable/disable to generic mprot
Implement a generic access rights modification procedure instead
of the procedures that only do one thing (enable/disable write)
to one section (text).
2022-05-12 22:28:31 +08:00
Masayuki Ishikawa
45beda286b arch: risc-v: Enable FPU for qemu-rv only if EXPERIMENTAL=y
Summary:
- Because a context switch issue still exists with FPU,
  it should be enabled only if EXPERIMENTAL=y

Impact:
- None

Testing:
- Tested with ostest

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-05-11 21:57:16 +08:00
Xiang Xiao
8634e8de64 Replace all sem_xxx with nxsem_xxx
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-10 15:08:36 +03:00
dytang
96b0209366 riscv/pmp: fix bug: PMP_CFG_FLAG_MASK makes pmp cfg fail. 2022-05-08 00:26:24 +03:00
Xiang Xiao
e84e5f0e1d arch: Add gcov related config for arm/risc-v/xtensa
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-06 14:43:57 -03:00
Xiang Xiao
45fb96c508 esp32x/wlan: Fix error: increment of a boolean expression
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-05 16:23:32 -03:00
Ville Juven
9af8b740e6 Elf loader: give temporary write access to user .text memory
When the .elf file is loaded from disk, the kernel must be given write
access to the allocated .text section in the task's address environment.

The access is removed after the elf is loaded and relocations are done.

NOTE:
The reason this works for the ARM implementation, is that the ARM MMU
can be configured to give write access for the privileged mode, but
revoke write access for the user mode.

Regardless, it would be smart to revoke write access even for the
kernel, when the kernel does not need it. This framework allows doing
that, if someone wishes to take up the task.
2022-05-03 21:25:25 +09:00
Ville Juven
2fd29b6408 RISC-V: Fix bug in riscv_addrenv.c
Need 1 full page extra for heap, not 1 byte.
2022-05-03 03:05:22 +08:00
Masayuki Ishikawa
5a9b2920e8 arch: risc-v: Add support for semihosting and hostfs
Summary:
- This commit adds support for semihosting and hostfs

Impact:
- None

Testing:
- Tested with nsh and nsh64 (defconfig will be updated later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-05-02 19:46:58 +08:00
Ville Juven
0ae2e68116 RISC-V: Temporarily disable error about missing SBI 2022-05-02 16:13:15 +08:00
Ville Juven
31b916c485 MPFS: Add kernel space mappings
Mappings are done with vaddr=paddr.
- I/O space mapped with two gigapages
- Kernel space mapped to statically allocated page tables. 2MB of kernel
  memory is supported.
- Page pool is mapped to the kernel space, to allow virtual memory access
  for the kernel e.g. to initialize the page memory when it is allocated.
2022-05-02 16:13:15 +08:00
Ville Juven
3f6504076e MPFS: Add page pool allocation 2022-05-02 16:13:15 +08:00
Ville Juven
cccfe31d0c MPFS: Add sources for CONFIG_ARCH_ADDRENV 2022-05-02 16:13:15 +08:00
Ville Juven
6bf8623897 RISC-V: Fix crt0 file compilation
Definition of STACK_FRAME_SIZE was moved
2022-05-02 16:10:47 +08:00
Xiang Xiao
1fde7e17bb arch: Move -fstack-protector-all from Make.defs to Toolchain.defs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-01 23:54:15 +03:00
Xiang Xiao
aeb9c5d822 boards: Move -fno-strict-aliasing from Make.defs to Toolchain.defs
and migrate MAXOPTIMIZATION into ARCHOPTIMIZATION

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-01 11:36:41 +03:00
Xiang Xiao
1e23799455 arch/riscv: Optimize the syscall performance in kernel mode
by renaming riscv_dispatch_syscall to sys_callx, so the caller
don't need the immediate step(syscallx->riscv_dispatch_syscall)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-01 11:31:01 +03:00
Xiang Xiao
efce8bd198 Revert "arch/risc-v: use STACK_FRAME_SIZE for in S-mode syscall asm"
This reverts commit 9b7f9867aa.
2022-05-01 11:31:01 +03:00
Xiang Xiao
a021177de8 arch: Fix the style found in review
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-01 11:29:44 +03:00
Xiang Xiao
94cb0c6072 arch: Move -nostdinc++ to Tooolchain.defs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-29 21:08:14 -03:00
Ville Juven
b3baf95835 UMM: Implement getter for address environment heap start vaddr
Using the Kconfig macro does not work for RISC-V target, as there the
user heap follows .data/.bss and does not obey any Kconfig provided
boundary.

Added stubs for ARM and Z80 also.
2022-04-29 23:13:16 +08:00
Ville Juven
e674d5cb86 RISC-V: Add crt0 file
Contains the code for the user process signal trampoline.
2022-04-29 02:02:15 +08:00
Ville Juven
0ccda05a82 RISC-V: Move wipe_page to pgalloc.h and rename it riscv_pgwipe 2022-04-29 02:02:15 +08:00
Ville Juven
3d8ba496a2 RISC-V: Add pgpool to vaddr utility function
The only mapping that is supported now is vaddr=paddr, but the function
DOES check that the address is within the page pool, so it is not
useless.
2022-04-29 02:02:15 +08:00
Ville Juven
1322f82802 RISC-V: Copy kernel memory mappings to userspace addrenv
Copy the kernel mappings to the new (user) address environment. The
copyuing is done exactly once. This relies on the fact that the kernel
L1/L2 mappings will never change, as all of the kernel memory is mapped
upon boot.
2022-04-29 02:02:15 +08:00
Ville Juven
57127b9429 RISC-V: Initial support for CONFIG_BUILD_KERNEL
This implements initial support for kernel build (address environments,
page allocator) for RISC-V.

This is done a bit differently compared to the ARMV7 implementation:

- Support implemented for Sv39 MMU, however the implementation should be
  extensible for other MMU types also.
- Instead of preserving and moving the L1 references around, a canonical
  approach is used instead, where the page table base address register
  is switched upon context switch.
- To preserve a bit of memory, only a single L1/L2 table is supported,
  this gives access to 1GiB of virtual memory for each process, which
  should be more than enough.

Some things worth noting:
- Assumes page pool is mapped with vaddr=paddr mappings
- The CONFIG_ARCH_XXXX_VBASE and CONFIG_ARCH_XXXX_NPAGES values are
  ignored, with the exception of CONFIG_ARCH_DATA_VBASE which is used
  for ARCH_DATA_RESERVE
- ARCH_DATA_RESERVE is placed at the beginning of the userspace task's
  address environment
2022-04-29 02:02:15 +08:00
Gustavo Henrique Nihei
ffab2dc628 risc-v: Restrict Fence instruction for chips that support S-mode
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-04-28 01:18:46 +08:00
Gustavo Henrique Nihei
1967805b91 risc-v: Fix format specifier in debug log
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-04-28 01:18:46 +08:00
chao.an
cbef8681fe arch/risc-v: add support for GCC LTO
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-27 23:42:37 +08:00
Ville Juven
216574bba8 OpenSBI: Add riscv_hardfp.S to compilation
It will just become an empty object if FPU support is not included.
2022-04-27 23:20:51 +08:00
dytang
d7cc3f9275 RISC-V: workaround for the RV64 SoC which does not has mem mapped MTIMER currten value regs. 2022-04-27 22:48:54 +08:00
Abdelatif Guettouche
587145a881 riscv/Makefile: Delete old target used for debugging.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-27 12:58:57 +08:00
Xiang Xiao
fc16cfaefe Correct the code alignment found in review
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-26 11:34:28 +03:00
Ville Juven
6546789b7e RISC-V: Add syscall support for vfork
If vfork is called via syscall (PROTECTED/KERNEL build) need to set up
return parameters for syscall. Otherwise the SW will get lost.
2022-04-25 16:23:17 +03:00
Xiang Xiao
8f8ee25a9c boards: Move -g from Make.defs to Toolchain.defs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-25 16:23:03 +03:00
Ville Juven
a014daf44f RISC-V: Add implementation for vfork 2022-04-25 15:44:32 +08:00
Ville Juven
2580520828 RISC-V: Fix system crash when FPU is in use
FPU registers need to be written prior to updating CSR_STATUS
2022-04-25 15:44:06 +08:00
Xiang Xiao
75326e563d boards: Move -fno-common from Make.defs to Toolchain.defs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-25 07:57:29 +03:00
Xiang Xiao
5a565e753c pm: Move pm_initialize call from driver_initialize to xxx_pminitialize
since it's too late with the below commit:
ommit a594a5d7a8
Author: chao.an <anchao@xiaomi.com>
Date:   Mon Apr 11 19:44:26 2022 +0800

    sched/init: drivers_initialize() should be late than up_initialize()

    up_initialize
    |
     ->up_serialinit
       |
        ->uart_register  /* ("/dev/console", &CONSOLE_DEV); */

    drivers_initialize
    |
     ->syslog_console_init
       |
        ->register_driver /* ("/dev/console", &g_consoleops, 0666, NULL); */

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-22 14:36:27 +03:00
Masayuki Ishikawa
04f81ecddb arch: risc-v: Do not enable FPU for K210 with QEMU
Summary:
- I noticed that maix-bit:smp does not work with QEMU.
- Actually, QEMU supports sifive_u (not K210) but it works
  if FPU is disabled.
- This commit fixes this issue.

Impact:
- K210 with QEMU only

Testing:
- Tested with qemu-5.2

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-04-22 14:52:04 +08:00
Huang Qi
06c7a3ca59 arch/risc-v/riscv_misaligned: Implement float load/store support
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-22 12:23:10 +08:00
Huang Qi
be95e76910 arch/risc-v: Enable FPU for K210
K210 support rv64gc ISA, now we enable F/D extension for it.

Note: QEMU for K210 don't support FPU now.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-21 21:47:29 +03:00
chao.an
1c8e12406e compile/opt: add config DEBUG_LINK_MAP
Selecting this option will pass "-Map=$(TOPDIR)$(DELIM)nuttx.map" to ld
when linking NuttX ELF. That file can be useful for verifying
and debugging magic section games, and for seeing which
pieces of code get eliminated with DEBUG_OPT_UNUSED_SECTIONS.

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-22 01:37:23 +08:00
chao.an
64d7326ed5 compile/opt: add config DEBUG_OPT_UNUSED_SECTIONS
Enable this option to optimization the unused input sections with the
linker by compiling with " -ffunction-sections -fdata-sections ", and
linking with " --gc-sections ".

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-22 01:37:23 +08:00
Huang Qi
0332b78f99 arch/risc-v: Don't clear reserved bits in fcsr in riscv_fpuconfig
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-21 15:26:05 +08:00
Huang Qi
48b81bda09 arch/risc-v: Change riscv_savefpu/riscv_loadfpu to macro
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-20 16:08:17 +03:00
chao.an
e066d5d1e0 arch/risc-v: Unify the toolchain definition of RVG for linux and windows
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-19 23:17:27 +08:00
Ville Juven
5b6dd876b8 risc-v/riscv_assert.c Fix dumping of status from ISR
The status dump did not work if the first fault triggers before
the first context switch (during nx_start()).
2022-04-19 15:28:09 +03:00
Xiang Xiao
7a0fd8d10f arch/risc-v: Remove FAR from chip and board folder
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-19 00:22:45 +03:00