zhuyanlin
c833048484
xtensa:kconfig: move ARCH_HAVE_TESTSET config to chip
...
Some xtensa arch have not implentment testset instructions
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-10 14:22:58 +08:00
Abdelatif Guettouche
f826e053ae
arch/xtensa/esp32: Remove the QEMU special case when initializing the
...
heap.
QEMU had a different ROM image that used the regions of PRO CPU for both
CPUs. This was causing crashes when running SMP mode as the heap was
being corrupted when the APP CPU starts.
QEMU is now loading the same image as the hardware chip and thus this
special case doesn't exist anymore.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-02-03 16:18:09 -03:00
chao.an
3ab557e748
arch/xtensa: correct the netlock handling
...
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-03 11:09:18 -03:00
Xiang Xiao
4c167b0729
Correct the code alignment
...
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-01 21:22:21 -03:00
Xiang Xiao
2c3020ddaf
arch/Toolchain.defs: Replace --print-file-name=libgcc.a with --print-libgcc-file-name
...
to more compatable with clang: https://reviews.llvm.org/D25338
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-31 09:46:04 +01:00
Xiang Xiao
e0b62bf677
arch/Toolchain.defs: Don't expand EXTRA_LIBS immediately
...
since board's Make.defs may overwrite ARCHCPUFLAGS
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-30 11:04:35 +09:00
Xiang Xiao
1c2c0e4707
arch/Toolchain.defs: Simplify the builtin library addition for EXTRA_LIBS
...
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-28 12:02:38 +01:00
Gustavo Henrique Nihei
b0d24f53c4
xtensa: Add initial support for ESP32-S3
...
Co-authored-by: Alan Carvalho de Assis <alan.carvalho@espressif.com>
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-27 13:46:50 -03:00
zhuyanlin
1b08f607be
arm/xtensa:cache: flush/clean dcache all if size large than cache size
...
For performance, if size large than cache size, use xxx_all instead
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-27 15:15:28 +08:00
Petro Karashchenko
6c27f3c19d
toolchain: add libm to EXTRA_LIBS only if it is provided by the compiler
...
Some toolchains may be built without libm support, but using
such toochain should not generate any errors in case if math
functions are not used in the program
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-22 15:36:29 +08:00
Xiang Xiao
2935751bfd
Fix error: implicit declaration of function 'up_cpu_index'
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 23:21:21 +08:00
Xiang Xiao
aa2cdcd848
xtensa/esp32: Change "cpu <= CONFIG_SMP_NCPUS" to "cpu < CONFIG_SMP_NCPUS"
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 23:21:21 +08:00
Xiang Xiao
77792a1598
sched: Define CONFIG_SMP_NCPUS to 1 in no SMP case
...
to simplify the SMP related code logic
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 23:21:21 +08:00
Petro Karashchenko
08043fb5bc
net: unify FAR keyword usage for all net buffer memory mapped buffers
...
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-20 01:42:56 +08:00
zhuyanlin
793ec6c909
arch:xtensa:vectors:fix bugs in a0 save
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Use right EXCSAVE_X
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-19 16:28:03 +01:00
zhuyanlin
a1a9ce3d1e
arch:xtensa_panic: use right interrupt pointer in xtensa_panic
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When enable interrupt stack, use a12 instead of sp
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-19 16:28:03 +01:00
zhuyanlin
88f5a209ce
xtensa: move a3 save in handler instead of _xtensa_context_save
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As in _xtensa_syscall_handler, a3 was save and reused before
_xtensa_context_save, a3 save in _xtensa_context_save will generate
error.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-19 16:28:03 +01:00
zhuyanlin
561fa88ed1
xtensa: add svcall handler
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svcall.c for xtensa
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-19 16:28:03 +01:00
zhuyanlin
662f071d9a
xtensa: fix svccall enter error
...
1. error in A3 push stack
2. when interrupt stack enable, push a12 is xtensa_irq_dispatch
parameter 1, instead of sp. As sp is interrupt stack address set by
`setintstack`, not the interruptee stack address
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-19 16:28:03 +01:00
Petro Karashchenko
9551de7115
net: use HTONS, NTOHS, HTONL, NTOHL macro in kernel code
...
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-18 10:59:47 +01:00
Gustavo Henrique Nihei
04723a89f2
xtensa: Fix core voltage level when SPI Flash runs at 80Mhz
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-18 02:21:46 +08:00
Petro Karashchenko
8d3bf05fd2
include: fix double include pre-processor guards
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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-16 11:11:14 -03:00
chao.an
c27839f98e
arm/xtensa: save the running registers to xcp context
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Signed-off-by: chao.an <anchao@xiaomi.com>
2022-01-15 02:20:01 +08:00
Gustavo Henrique Nihei
c372e1e295
xtensa: Fix typo in xchal_cpX_store macros' invocation
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-13 21:07:04 +01:00
Alan C. Assis
7b32849b84
esp32s2: Fix data cache option in menuconfig
2022-01-12 21:45:04 +01:00
Gustavo Henrique Nihei
80436dd7be
xtensa/esp32s2: Fix some wrong definitions related to IRQ management
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-12 21:28:40 +01:00
Gustavo Henrique Nihei
efca63e9e3
xtensa/esp32s2: Fix missing parenthesis on macro expression
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-11 23:21:13 +08:00
ligd
3cfc6761ff
xtensa: fix lack of float register save & resotre
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Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-01-11 12:17:09 +01:00
Alan C. Assis
2079cc0f6e
esp32: Add support to RS485
2022-01-10 10:49:16 +08:00
Alan C. Assis
4ca38c6c50
esp32: Add PWM support using the LEDC peripheral
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Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-08 14:46:51 +01:00
Gustavo Henrique Nihei
73ea0c1627
xtensa: Improve Kconfig description of ESP32-S2 arch family
...
Also fix the wrong "dual-core" statement, since all ESP32-S2 chips are
composed of a single Xtensa LX7 core.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-07 22:25:05 +01:00
Zeng Zhaoxiu
fb43fd73ed
signal: signal handler may cause task's state error
...
For example, task is blocked by nxsem_wait(sem1), use nxsem_wait(sem2)
in signal handler, and take sem2 successfully, after exit from signal
handler to task, nxsem_wait(sem1) returns OK, but the correct result
should be -EINTR.
Signed-off-by: Zeng Zhaoxiu <zhaoxiu.zeng@gmail.com>
2022-01-05 21:36:44 +09:00
Abdelatif Guettouche
4edc5fb701
xtensa: Rename up_stack_color to xtensa_stack_color since it's an
...
internal function.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-01-04 02:45:45 +08:00
Gustavo Henrique Nihei
78362b0949
xtensa/esp32: Use ROM implementations of libc functions
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-03 10:37:04 -03:00
Petro Karashchenko
d23ad9b9b0
userspace: fix typos in comments
...
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-02 20:50:30 +01:00
Gustavo Henrique Nihei
c1fac720ec
xtensa/esp32: Add missing param documentation for SPI Flash function
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-01 20:37:44 +08:00
Gustavo Henrique Nihei
9e5e60ba48
esp32s2/esp32c3: Build MCUboot bootloader with Flash Encryption support
2022-01-01 20:37:44 +08:00
Gustavo Henrique Nihei
f130d8b91e
xtensa/esp32s2: Remove unavailable support for ROM Basic Console
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This feature is only available for ESP32 chips.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-31 00:56:08 +08:00
chao.an
736add0fe8
arch/backtrace: correct the skip counter
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-30 16:57:40 +08:00
Gustavo Henrique Nihei
80da9abd6a
xtensa/esp32: Move assertions after logging to improve debugging
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-30 12:35:41 +08:00
Gustavo Henrique Nihei
b6addaa4c7
xtensa/esp32: Enable the creation of encrypted Flash partitions
...
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-30 12:35:41 +08:00
Gustavo Henrique Nihei
340e0c8a8f
xtensa/esp32: Build MCUboot bootloader with Flash Encryption support
...
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-30 12:35:41 +08:00
ChenWen
6ce335fa84
xtensa/esp32: Fix some Wi-Fi issues
...
1. Fix the issue that Wi-Fi can't connect to some special routers occasionally.
2. Update Wi-Fi driver code to fix issue of failure to send pkt.
3. Replace software random with hardware random
2021-12-28 23:48:25 -06:00
chao.an
7ed0b97414
make/allsyms: skip the unnecessary link operation
...
For incremental compilation, skip the stage 1 dummy link
operation if nuttx elf has been generated
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-28 23:47:10 -06:00
Xiang Xiao
dd942f0b04
sched/backtrace: Dump the complete stack regardless the depth
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-29 12:09:54 +08:00
chao.an
a42aa8415d
compile/flags: add FRAME_POINTER into Toolchain.defs
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-27 22:31:27 -06:00
Petro Karashchenko
3ccb657dc2
nuttx: remove space befone newline in logs
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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-27 21:01:19 -06:00
Alan C. Assis
01e4e249cc
Add WiFi/BLE Coexistence support
...
Co-authored-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-12-23 20:42:23 -06:00
chao.an
fe2830ec94
xtensa: enhance the task dump
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add irq stack information
add cpu loading
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-22 11:46:02 -03:00
Gustavo Henrique Nihei
f542ab4564
xtensa/esp32s2: Add Secure Boot support on top of MCUboot
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-21 07:02:40 -06:00
Gustavo Henrique Nihei
d22a2aa7a0
xtensa/esp32: Refactor makefiles for compliance to Function Call Syntax
...
According to Make documentation:
- "Commas and unmatched parentheses or braces cannot appear in the text
of an argument as written";
- "Leading spaces cannot appear in the text of the first argument as
written".
Although in the current state it was not resulting in parsing issues, it
is better to fix it.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-21 07:02:40 -06:00
Gustavo Henrique Nihei
6c3223289f
xtensa/esp32: Add Secure Boot support on top of MCUboot
...
This adds the capabitlity of building signed images on NuttX.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-21 07:02:40 -06:00
Petro Karashchenko
3e76c3266e
assert: unify stack and register dump across platforms
...
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-20 00:02:12 -03:00
Petro Karashchenko
67d8a82393
Kconfig: fix non-string default values uniformity
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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-20 00:10:57 +01:00
chao.an
b11833cbba
arch/assert: flush the syslog before stack dump
...
flush the syslog before stack dump to avoid buffer overwrite
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-15 12:00:35 -06:00
chao.an
56ef1419dd
arch/xtensa: set the current reg before print syslog
...
ensure the semantics of the up_interrupt_context() works as expected
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-14 21:40:03 -06:00
chao.an
2fe06ac083
arch: xtensa: save current SP before overwrting
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-14 21:40:03 -06:00
chao.an
93b133fe66
arch/xtensa: correct the interrupt stack on irq handler
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-14 21:40:03 -06:00
Petro Karashchenko
51a2db6ffc
Kconfig: improve uniformity
...
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-14 07:32:48 -06:00
chao.an
c2fd66bfab
arch/arm/risc-v/xtensa: add support of all symbols for debugging
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-13 08:31:13 -06:00
Abdelatif Guettouche
d31a0d8aca
arch/xtensa/esp32: Show CPU activity on IDLE task and on interrupts.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-12-13 08:30:58 -06:00
Abdelatif Guettouche
6262f7e99a
esp32_idle.c: Change private function's name to start with esp32_
...
instead of up_.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-12-13 08:30:58 -06:00
Xiang Xiao
6357523892
arch: Add _wchar_t typedef like other basic types
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-09 16:57:23 +09:00
Xiang Xiao
a0990ee416
arch: Remove the duplicated up_tls_info implementation
...
Define up_tls_info in arch/arch.h directly if the general one isn't suitable
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-05 20:59:53 -06:00
Xiang Xiao
19e5ee6ce0
arch: Remove FILE dump code from _up_dumponexit
...
since the kernel build can't access the userspace memory
inside other process directly
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-06 11:23:58 +09:00
Abdelatif Guettouche
50d217a9e8
esp32_cpustart.c: Improve comments around the usage of the inter-cpu
...
startup handshake.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-12-02 11:21:49 -06:00
Abdelatif Guettouche
b34951e3a0
esp32_cpustart.c: Remove the CONFIG_SMP condition on some part of code
...
because the whole file is only built if CONFIG_SMP is enabled.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-12-02 11:21:49 -06:00
Xiang Xiao
b65c7c26cf
arch: Dump task name through tcb_s::name instead of argv[0]
...
since argv is defined in task_tcb_s not tcb_s
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-01 16:04:15 +01:00
Abdelatif Guettouche
251b8a3445
esp32xx_rtc: Include "clock/clock.h" to have a declaration of
...
g_basetime.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-26 15:23:47 -03:00
Abdelatif Guettouche
af11cf6cd1
esp32xx_rtc.c: Fix a duplicated assignment.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-26 15:23:47 -03:00
Xiang Xiao
e30a5f3790
arch/sim: Add new option to enable arch specific hostfs
...
we have many different hostfs implementation now, so it's better
to select the implementation explicitly, just like what we have
done for arm(FS_HOSTFS vs. ARM_SEMIHOSTING_HOSTFS).
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-11-25 14:42:23 +01:00
zhuyanlin
1b3005accf
arch:cache_invalidate: fix unalign cacheline invalidate
...
Only invalidate may corrupt data in unalign start and end.
Use writeback and invalidate instead.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-24 22:48:13 -06:00
zhuyanlin
4db5016d83
arch:hostfs: add cache coherence config for semihosting option
...
N/A
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-24 22:48:13 -06:00
Abdelatif Guettouche
65db787eff
esp32_irq.c: Fix retrieving IRQ number and peripheral ID when it comes
...
to GPIOs in SMP mode.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-22 11:41:10 -06:00
zhuyanlin
ffb543d061
xtensa: add setjmp.h include file
...
N/A
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-17 02:23:45 -06:00
zhuyanlin
0e002af323
xtensa_backtrace: fix typ error
...
N/A
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-17 01:47:26 -06:00
Xiang Xiao
2262ddfa6d
arch: Remove fflush(stdout) from driver code
...
it's wrong to call stdio function inside driver
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-11-15 00:04:12 +01:00
Abdelatif Guettouche
6cbcbd5481
arch/risc-v&xtensa/Kconfig: Don't select LIBC_ARCH_MEMCCMP. The Kconfig
...
option doens't exist and we are not providing any external
implementation.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-13 11:54:42 -03:00
zhuyanlin
c6c534f27b
xtensa:mpu:use WRITEBACK attribute for intsram & extsram
...
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-13 05:59:10 -06:00
Dong Heng
fed7808d80
esp32 & esp32c3: Partition supports BIO cmd
2021-11-13 05:58:30 -06:00
Dong Heng
a59aae6927
esp32/esp32c3: Fix MMU pages number calculation error
2021-11-07 21:59:54 -06:00
zhuyanlin
580d17cc02
arch:xtensa: make xtensa_abi.h global include and usage
...
N/A
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-06 07:39:27 -05:00
Abdelatif Guettouche
73f15ed544
esp32/Kconfig: Make ESP32_BT_RESERVE_DRAM default to 0 again if
...
Bluetooth is not enabled. When Bluetooth is enbaled then it defaults to
64KB. This will not wast those 64KB of memory when Bluetooth is not enabled.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-01 10:01:38 -05:00
Gustavo Henrique Nihei
de0e4d4aac
xtensa/esp32s2: Rename MTD-related configs to become more intuitive
...
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-25 21:45:20 -05:00
Gustavo Henrique Nihei
fb00ab3242
xtensa/esp32: Rename MTD-related configs to become more intuitive
...
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-25 21:45:20 -05:00
Gustavo Henrique Nihei
eb889b0884
xtensa/esp32s2: Enable Partition Table allocation at custom offset
...
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-25 16:34:58 -03:00
Gustavo Henrique Nihei
9d7b9821b3
xtensa/esp32: Enable Partition Table allocation at custom offset
...
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-25 16:34:58 -03:00
Gustavo Henrique Nihei
b555b3f89e
xtensa/esp32: Refactor and reorganize Partition Table related configs
...
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-25 16:34:58 -03:00
Gustavo Henrique Nihei
793266d39e
espressif: Fix spacing style in Kconfig files
...
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-25 08:01:44 -05:00
Gustavo Henrique Nihei
4ff754827c
espressif: Fix prompt string of Wi-Fi FS mount point configs
...
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-25 08:01:44 -05:00
Gustavo Henrique Nihei
a1af605973
espressif: Fix references to Wi-Fi according to Wi-Fi Alliance
...
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-25 08:01:44 -05:00
Alan C. Assis
7e8003cba1
Move chip specific file compilation to CHIP_CSRCS
2021-10-23 04:03:12 -05:00
Alan C. Assis
03738622a1
esp32s2: Add RNG driver support and board profile example
2021-10-23 04:03:12 -05:00
zhuyanlin
cf1a04d0a2
xtensa:cache: add lock & unlock feature
...
Since some xtensa cores cache support lock & unlock feature.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-10-22 13:31:32 -03:00
Abdelatif Guettouche
8288a04a0b
arch/xtensa/esp32: Remove the AES test from the driver.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-19 18:41:57 -03:00
zhuyanlin
b5134565fa
arch:xtens:mpu: modify acc and memtype to uint32_t
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The uint8_t and uint16_t will overflow in MPU_ENTRY_AR marco.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-10-19 00:24:31 -05:00
Xiang Xiao
91398e73eb
arch/xtensa/Kconfig: add quotes in source to clean warnings from setconfig
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-10-19 00:33:51 +02:00
Abdelatif Guettouche
7b43d11435
esp32_spiflash.c: Allocate only one variable to hold the cache state in
...
single CPU mode.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-16 22:56:21 -07:00
Abdelatif Guettouche
f54a929001
esp32_spiflash.c: Keep the index of the other CPU between SPI Flash
...
operations.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-16 22:56:21 -07:00
Abdelatif Guettouche
eeb68bda3d
xtensa_testset.c: Simplify the test-set function and remove some old
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comments.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-16 22:56:21 -07:00
Abdelatif Guettouche
dfe1637864
esp32_spiflash.c: Pause the other CPU during flash operation.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-16 22:56:21 -07:00
Abdelatif Guettouche
f2c2323642
esp32_intercpu_interrupt.c: Force the functions to internal SRAM.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-16 22:56:21 -07:00
Abdelatif Guettouche
d2bc011719
arch/xtensa/xtensa_cpupause.c: Allow a spin before taking the g_cpu_wait
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spinlock.
If we repeatedly call up_cpu_pause and up_cpu_resume, there would be
cases where the next call to up_cpu_pause happens while the other CPU is
still responding to the previous resume request. In this case the
DEBUGASSERT will trigger. We should allow the first CPU to wait until the
other CPU has finished responding to the resume request.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-16 09:46:23 -07:00
Abdelatif Guettouche
591c1563b8
esp32_oneshot_lowerhalf.c: Use the same alignment as the rest of the
...
code base.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
9e1d2ca95e
esp32_rt_timer.c: Group static variables into a struct and fix naming
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standard
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
0dff3f2762
esp32_wifi_adapter.c: Use the specified spin lock when
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enabling/disabling interrupts.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
a50d673df7
esp32_wifi_adapter.c: Don't hold another spinlock when calling
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enter_critical_section, we already hold the global IRQ spinlock.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
11216257cf
esp32_rt_timer.c: Don't nest calls to spin_lock_irqsave with a device
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specific spinlock, this will lead to deadlocks.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
e847c61801
esp32_wifi_adapter.c: Use device specific locks.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
32f7471f9e
esp32_wlan.c: Use device specific locks.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
4ae1285124
esp32_emac.c: Use device specific locks.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
e64390d5e9
esp32_rt_timer.c: Use device specific locks.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
c61009c2cf
esp32/esp32_spi_slave.c: Use device specific locks.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
2273684cb1
esp32/esp32_spi.c: Use device specific locks.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
0123243f9a
esp32/esp32_i2c.c: Use device specific locks.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
0af9a49d9c
esp32/esp32_oneshot_lowerhalf.c: Use device specific locks.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
698af43d78
esp32/esp32_freerun.c: Use device specific locks.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
04bd27400a
xtensa/esp32_wdt_lowerhalf.c: Use device specific locks.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
19a096cdfe
arch/xtensa/esp32_tim_lowerhalf.c: Use device specific locks.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-16 00:01:23 -07:00
Gustavo Henrique Nihei
ff705586bb
xtensa/esp32s2: Provide SPI Flash parameters to MCUboot build
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Also unify bootloader config creation to reduce duplication.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-15 23:55:10 -07:00
Gustavo Henrique Nihei
4d5e0f8fe1
xtensa/esp32: Provide SPI Flash parameters to MCUboot build
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Also unify bootloader config creation to reduce duplication.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-15 23:55:10 -07:00
Abdelatif Guettouche
a7d8d9dd98
esp32s2/tie.h: Run the file though detab.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-14 07:39:54 -03:00
Abdelatif Guettouche
6d246eb18f
esp32s2/tie.h: The old tie.h file was from ESP32 which doesn't apply to
...
ESP32-S2. This commit gets the correct S2 tie.h file
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-14 07:39:54 -03:00
Abdelatif Guettouche
217fd97fd3
xtensa_coproc.S: Correctly save/restore coprocessor0 state.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-14 07:39:54 -03:00
Abdelatif Guettouche
7420f245bc
xtensa_context.S: Save and restore SCOMPARE1 when necessary.
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SCOMPARE1 is used by some atomic instructions and need to be preserved
during a context switch.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-14 06:32:17 -03:00
Alan C. Assis
867c6d0636
esp32: Add initial support to Bluetooth Low Energy
...
Co-authored-by: saramonteiro <saramonteirosouza44@gmail.com>
Co-authored-by: Gustavo Henrique Nihei <gustavonihei@gmail.com>
2021-10-04 15:10:37 -03:00
Abdelatif Guettouche
d22b4ec539
espxx_rng.c: Add "/" at the beginning of paths for consistency.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-09-30 13:50:25 -03:00
Abdelatif Guettouche
5c6a30c00b
esp32_rng.c: Remove the initialization guard. The init function is
...
called only once during startup.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-09-30 13:50:25 -03:00
Abdelatif Guettouche
6a262c5203
esp32_rng.c: Remove unused functions.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-09-30 13:50:25 -03:00
Sara Souza
8a142f474e
xtensa/esp32-s2/rttimer: Disable alarm before setting a new value and enabling it
2021-09-28 21:02:57 -03:00
Alin Jerpelea
15a37c5a5a
arch: Omni Hoverboards: update licenses to Apache
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Gregory Nutt has submitted the SGA
Omni Hoverboards has submitted the SGA
David Sidrane has submitted the ICLA
Mateusz Szafoni has submitted the ICLA
Sebastien Lorquet has submitted the ICLA
Paul Alexander Patience has submitted the ICLA
as a result we can migrate the licenses to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-09-28 04:37:38 -07:00
Gustavo Henrique Nihei
a5f9e29d78
xtensa/esp32s2: Enable support for "make bootloader" target
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This enables the provisioning of the bootloader binaries through the
build system.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-09-27 18:21:53 -07:00
Gustavo Henrique Nihei
800678ca78
xtensa/esp32s2: Enable booting from MCUboot bootloader
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-09-27 18:21:53 -07:00
Abdelatif Guettouche
5336704c77
esp32_start.c: Initialize the SPI RAM before enabling its cache.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-09-27 05:13:51 -07:00
Gustavo Henrique Nihei
c23986ec63
xtensa/esp32: Select ARCH_HAVE_BOOTLOADER for ESP32 chips
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-09-24 10:48:19 -07:00
Gustavo Henrique Nihei
4ac3044cc3
xtensa/esp32: Enable build system to download or build bins from source
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-09-23 20:52:25 -07:00
Abdelatif Guettouche
f2f2040c44
esp32_spiram/psram/himem: Add and fix the files' sections.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-09-23 02:49:11 -07:00
Abdelatif Guettouche
3d8a6fb676
esp32_spiram.c: Remove esp_himem_reserved_area_size from esp32_spiram.c
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file. This function is already defined in esp_himem and is used only
when that file is built. We don't need another weak function.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-09-23 02:49:11 -07:00
Abdelatif Guettouche
2834d2a46f
esp32_spiflash.c/esp32_spiram.c: Remove some unused macros/functions/variables.
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Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-09-23 02:49:11 -07:00
Sara Souza
962059f843
xtensa/esp32-s2: Adds oneshot device driver support
2021-09-22 22:53:54 -03:00
Sara Souza
fba6fa2dc1
xtensa/esp32-s2: Adds support to rt_timer and systimer to ESP32-S2.
2021-09-22 17:18:24 -03:00
Sara Souza
2cd4f4af79
xtensa/esp32-s2: Adds freerun timer wrapper
2021-09-22 09:38:10 -03:00
Gustavo Henrique Nihei
eca1f86294
arch/xtensa: Remove CODE qualifier for Xtensa-specific files
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei
e13dd7dab9
arch/xtensa: Remove FAR qualifier for Xtensa-specific files
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei
58f87ef443
xtensa/esp32: Fix wrong position for ++ operator on I2C driver
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-09-22 08:16:01 -03:00
Abdelatif Guettouche
9f4d7e4767
xtensa_dumpstate.c: Fix the name of the TCB variable when dumping the
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backtrace.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-09-21 09:22:28 -03:00
Abdelatif Guettouche
15b68b9abb
esp32_spiflash.c: Correctly disable APP's CPU cache.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-09-17 17:43:45 -03:00
Gustavo Henrique Nihei
b33ccd01cf
xtensa/esp32: Make the semaphore timeout on I2C configurable
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-09-16 14:07:26 -03:00
zhuyanlin
7947e50f06
xtensa:backtrace: flush to stack when in interrupt
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The registers may be in window during interrupt.
Flush window stack to stack first.
And fix warning in build.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-09-16 10:53:35 -05:00
zhuyanlin
cdb441cc3f
arch:xtensa:dumpstate: use sched_dumpstack
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Use sched_dumpstack instead. The backtrace infomation like
xtensa_user_panic: User Exception: EXCCAUSE=0009 task: hello
xtensa_registerdump: PC: 202b32b8 PS: 00060030
xtensa_registerdump: A0: a02acb87 A1: 20998d10 A2: ffffaaaa A3: 12345678
xtensa_registerdump: A4: a02ba26c A5: 209949c0 A6: 20990994 A7: 00000258
xtensa_registerdump: A8: a02b32af A9: 20998cb0 A10: 0000000f A11: 209949a0
xtensa_registerdump: A12: a02be95c A13: 20994980 A14: 00000003 A15: 209949d0
xtensa_registerdump: SAR: 00000000 CAUSE: 00000009 VADDR: ffffaaaa
xtensa_registerdump: LBEG: 00000000 LEND: 00000000 LCNT: 00000000
xtensa_registerdump: TMP0: 202b1512 TMP1: 20998af0
sched_dumpstack: [BackTrace| 3|0]: 0x202acbae 0x202b232e 0x202b1912 0x202b19f5 0x202b24f1 0x202b152f 0x40023 0x202b32b0
sched_dumpstack: [BackTrace| 3|1]: 0x202acb87 0x202a86a4
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-09-16 10:32:38 +08:00
zhuyanlin
6e0f84dc88
arch:xtensa: add up_backtrace support
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Up_backtrace can be backtrace from task or interrupt.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-09-16 10:32:38 +08:00
zhuyanlin
3acdbef60d
xtensa:arch: force up_getsp to inline
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Up_getsp may be not inline in gcc, thus get the sp
is up_getsp function's sp, not the caller function.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-09-16 10:32:38 +08:00
zhuyanlin
583dce0b98
arch:xtensa: remove WSBITS/WBBITS to core.h
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Remove WSBITS/WBBITS macro to core.h as may be used by
arch common code.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-09-16 10:32:38 +08:00
Sara Souza
83a9c2b24b
xtensa/irq.h: Fixes the routine that clears the processor interrupt
2021-09-13 17:01:49 -03:00
zhuyanlin
8e6fbe700e
xtensa:dcache_clean: use DCACHE_LINZESIZE instead of DCACHE_SIZE
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Clean_dcache use DCACHE_LINZESIZE instead of DCACHE_SIZE in addr loop
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-09-13 14:38:57 +08:00
Abdelatif Guettouche
4ef859924b
esp32_serial.c: Release the spinlock before calling uart_xmitchars, this
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functions will call esp32_txint again which leads to deadlock since
esp32_txint has already locked the spinlock.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-09-09 19:35:17 +09:00
Abdelatif Guettouche
b5bb1fb8a3
esp32_serial.c: Replace critical section by a device specific spin lock.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-09-09 19:35:17 +09:00
Abdelatif Guettouche
f47d28c108
esp32_serial.c: Don't fake an interrupt when interrupts are not
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suppressed.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-09-08 09:27:08 -03:00
zhuyanlin
26b4bb3075
xtensa:cache: fix typo error
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use addr instead of add
2021-09-08 11:19:02 +02:00
zhuyanlin
7b5c39a9d3
arch:xtensa: add xtensa_cache code support
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Add xtensa_cache code support
2021-09-07 13:33:31 +08:00
zhuyanlin
d6fe0f18f5
arch:xtensa: add XTENSA_CACHE config support
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Add support for XTENSA_HAVE_ICACHE & XTENSA_HAVE_DACHE
2021-09-07 13:33:31 +08:00
Sara Souza
26397c6695
xtensa/esp32: Wi-Fi board logic refactoring.
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This commit removes the initialization of the Wi-Fi partition
from the Wi-Fi board logic and moves it to the SPI Flash board code.
It creates 2 different partition (one for Wi-Fi and one for general
use).
It also allows these partitions to be mounted over several FSs.
2021-09-04 14:30:02 +08:00
zhuyanlin
fd9ce0137e
arch:xtensa: add xtensa mpu support
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Add support for Xtensa Memory Protect Unit.
Change-Id: I27e2f05daae24429ef7513d843b4f217daeefa0d
2021-09-02 09:17:26 -03:00
Sara Souza
8081228556
xtensa/esp32-s2: Adds support to the timer driver
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Only one more support for ESP32-S2 chip.
2021-09-01 14:10:01 -03:00
Xiang Xiao
b0c782255c
libxx: Change CXX_LIBSUPCXX to LIBSUPCXX
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align with other Kconfig(e.g. LIBCXXABI, LIBCXX, UCLIBCXX)
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-28 17:14:48 -03:00
zhuyanlin
9ea7676731
arch:xtensa: rename XCHAL_INT_NLEVELS to XCHAL_NUM_INTLEVELS
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The name used in Tensilica support file core-isa.h for all vendors is
`XCHAL_NUM_INTLEVELS`.
Use a new name may be confused by newer porting xtensa arch.
Change-Id: Ie108d3fdfcc02c81f0eacfca852a1cfc9eea17de
2021-08-28 21:51:45 +02:00
Abdelatif Guettouche
1385ea7673
arch/esp32: Properly handle GPIO interrupt in SMP.
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The PRO CPU and APP CPU have different peripherals for GPIO interrupts.
Each CPU needs to allocate an interrupt and attach it to its GPIO
peripheral.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-27 13:24:00 +09:00
Kapil Gupta
ec99e11f5e
esp32/softap: Enable the WPA2 by default to ask user password
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Signed-off-by: Kapil Gupta <kapil.gupta@espressif.com>
Co-author: Alan Carvalho de Assis <alan.carvalho@espressif.com>
2021-08-26 13:26:57 +08:00
Abdelatif Guettouche
fc594c5d25
esp32_irq.c: Extend the CPU interrupt/peripheral map to include the
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status of the interrupt (enabled/disabled).
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
810ed19b8f
arch/xtensa/esp32_irq.c: Enable/disable interrupts using the Interrupt
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Matrix.
This allows manipulating interrupts from both CPUs. Internal interrupts
however, still need to be disabled/enabled by each CPU.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
a7abd56448
arch/xtensa: Move the Xtensa specific part of interrupts to
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xtensa/include/irq.h
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
470799b0b3
arch/xtensa/esp32_irq: Remove the map/unmap IRQ functions they are used
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only inside this file.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
04cd520293
arch/xtensa/esp32: Merge esp32_intdecode with esp32_irq.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
79cc12c034
arch/xtesna/esp32: Merge the contents of esp32_cpuint and esp32_irq.
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They do the same thing (manipulate interrupts) keeping them separated
was making things harder.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
237aebb7e1
arch/xtensa/esp32_cpuint.c: Refactor retrieving the intmap and register
...
address of a peripheral.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
02c17c3169
arch/esp32: Simplify the interrupt allocation process.
...
Allocating and attaching interrupts were both exported outside, however
these two move hand in hand and we don't have to expose these details.
Also, the parameters passed are saved and will be used to retrieve
information about the interrupt and the attached peripheral.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
eefe7ebe5f
xtensa/esp32_cpuint: export only one function to allocate a CPU
...
interrupt.
That function will have a parameter to decide whether to allocate a
level sensitive interrupt or an edge sensitive interrupt.
All the drivers are also updated with this API change.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
dbdec45049
arch/xtensa/src/common: Use irq_spin APIs in modifyregXX
...
Replace enter_critical_section with spin_lock_irqsave.
Replace leave_critical_section with spin_unlock_irqrestore.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-25 23:32:40 +08:00
Abdelatif Guettouche
5ff703d5d0
arch/*_testset: Fix few typos.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-25 00:20:20 +08:00
Abdelatif Guettouche
2925d4956b
xtensa/esp32: Use up_cpu_index instead of this_cpu.
...
this_cpu requires sched.h to be included.
2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
5d626f7267
xtensa/esp32_irq.c: Hard code special IRQs in the IRQ map. These IRQs
...
are do not go through the regular process where we attache the CPU
interrupt to a peripheral and update our map, also, they are fixed and a
have reserved CPU interrupt, thus hard code their values at startup.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
56a7f3b651
arch/xtensa/esp32: Update the drivers regarding the API change in IRQ
...
handling.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
5be9f24fe5
arch/xtensa/esp32: Disable the CPU interrupt right when it's alloacted.
...
At this point we are in a critical section and have all the necessary
information to disable the interrupt properly (CPU, and CPU interrupt).
Leaving it to the drivers will complicate things as converting from IRQs
to CPU interrupts could be tricky in SMP mode.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
97dca8fe10
arch/xtensa/esp32: Use the same g_intenable shadows in cpuint.c and
...
irq.c
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
633cdf8e27
arch/xtensa/esp32: Map NuttX's IRQs to ESP32 CPU interrupts.
...
This map also keeps track of the CPU that attached the IRQ. This will
be used to properly disable the interrupt in the correct CPU in SMP
mode.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-20 13:17:25 -03:00
Sara Souza
e092c457e6
xtensa/lx7: Fix the CROSSDEV variable
2021-08-20 16:48:20 +02:00
Xiang Xiao
af72376773
fs: Remove magic field from partition_info_s
...
since it is wrong and impossible to return file
system magic number from the block or mtd layer.
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-20 09:19:52 -03:00
Abdelatif Guettouche
cd0f64d779
xtensa/irq.h: Add a macro to convert to an IRQ from a peripheral ID.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-18 10:49:58 -03:00
Abdelatif Guettouche
a220766d57
xtensa.h: Remove unused function prototype.
...
ESP32 uses a different function to start the app CPU and no other xtensa
CPU uses this __cpu1_start function.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-18 04:41:40 -07:00
Xiang Xiao
71269811ca
mtd: Implement BIOC_PARTINFO for all drivers
...
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-16 10:08:26 -03:00
Abdelatif Guettouche
5b350f3a0f
arch/*_reprioritizertr.c: Fix typos in comments.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-14 11:19:34 -07:00
Gustavo Henrique Nihei
1dfcc6ab49
xtensa/esp32: Enable boot from Espressif's port of MCUboot
...
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-08-13 08:44:20 -03:00
zhuyanlin
1a1b1cc2b4
arch:xtensa: replace include file from src/chip_xxx to chip.h
...
Use chip.h as a standard include file, replace chip_xxx in src dir
2021-08-12 16:18:35 +02:00
zhuyanlin
30a2338e92
arch:esp: create chip.h header for chip src code.
...
Create chip.h header for esp src code.
2021-08-12 16:18:35 +02:00
zhuyanlin
6d592256fb
arch:xtensa: add __ASSEMBLY__ for espxxx_soc.h
...
Those header contain syntax not be recognize by gnu assembler.
2021-08-12 16:18:35 +02:00
zhuyanlin
e333733053
xtensa:coproc: fix XTENSA_CP_ALLSET error in some case
...
Consider follow coprocessor configuration case:
\#define XCHAL_CP_NUM 1 /* number of coprocessors */
\#define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */
\#define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */
\#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
\
\#define XCHAL_CP1_NAME "AudioEngineLX"
\#define XCHAL_CP1_IDENT AudioEngineLX
\#define XCHAL_CP1_SA_SIZE 208 /* size of state save area */
\#define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
\#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
In this case, XTENSA_CP_ALLSET is 0x1, but valid coprocessors
bitmap is 0x2, use marco XCHAL_CP_MASK instead, it is bitmap of all
vaild coprocs.
Change-Id: I63ec01e4bd0cbafc62d56636cc11bdc4a2f7857f
2021-08-10 19:44:55 -07:00
Abdelatif Guettouche
054e284785
*_cpustart.c: Fix typos in function description.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-11 11:06:27 +09:00
Sara Souza
61ab4f9f14
xtensa/esp32: Fix the type of enum passed between functions in esp32_rtc_clk
2021-08-10 11:15:51 -03:00
Sara Souza
67d29e7537
xtensa/esp32: initialize RTC in case PM or RTC configs are not set, but RWDT is.
2021-08-10 11:15:51 -03:00
zhuyanlin
5820972727
arch:xtensa: add arch stdarg.h include file for xtensa
...
Add arch/include/stdarg.h for xtensa.
Change-Id: Ia914ca0f4c95e86b130983ce690479a994a08b56
2021-08-09 17:58:25 -03:00
Xiang Xiao
776458143c
fs/hostfs: Support fchstat and chstat callback
...
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-09 17:55:44 -03:00
zhuyanlin
ec17cad69d
arch:xtensa:include chip/irq.h instead of depend on chip config.
...
Many duplicate code when more chips add-in,
follow arch/arm/include/irq.h method, use chip/irq.h instead.
Change-Id: I42f516c1dda68e973939c669f627c457cd0bc65e
2021-08-05 10:08:48 +02:00
zhuyanlin
cec6aeb059
arch:xtensa:vector: fix typo error in level4_ventor
...
Change-Id: I66cd3ff30e50e18ed718499aef609dd7aeb82dd3
2021-08-04 20:16:41 -07:00
zhuyanlin
51d13df317
arch: xtensa: save current SP before overwrting in dispatch_c_isr.
...
In levelx(2,3,4,5)_handler, first need to save sp in a12,
then after dispatch_c_isr we can restore sp from a12.
Change-Id: Idb6b64a782da866670a4db80b33435a9b63f02c3
2021-08-04 20:16:41 -07:00
zhuyanlin
4fc5b62ec3
arch:xtensa: use letter 'i' in inline assemble constraint instead of I
...
Some toolchain such as xtensa-xcc is unrecognize with constraint letter 'I',
letter 'i' is more common in GNU assembler.
Change-Id: I00f6a33fd7a5f2b95508c683e9954d402b68755f
2021-08-04 18:23:40 +02:00
zhuyanlin
9a34705b80
arch:xtensa_testset: remove include arch/spinlock.h
...
In config with no "CONFIG_SPINLOCK", include arch/spinlock.h will lead to
build error as multi definition with spinlock_t. Nuttx/spinlock.h will
include arch/spinlock.h when needed.
Change-Id: I33b48503f679ec79af3a0ef1f0fb1536aaf1ce7c
2021-08-04 18:18:11 +02:00
zhuyanlin
355133f218
arch:xtensa: add new GNU toolchain for xtensa.
...
Add support xcc,xclang GUN toolchin in xtensa,
ESP toolchain is default.
Change-Id: Id00bcf4a16c1e16862a106db32b1da3f3713a14c
2021-08-04 18:16:14 +02:00
Abdelatif Guettouche
238a96e7de
arch/esp32_cpuint.c: Simplify up_disable/enable_irq.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-03 19:52:12 -07:00
Abdelatif Guettouche
4f2f2ef9fb
arch/xtensa: Get the cpu member out of the read only structure.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-03 19:52:12 -07:00
Abdelatif Guettouche
239f0e257b
arch/xtensa/esp32: Keep track to which CPU the interrupt was attached.
...
This is used when dettaching.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-03 19:52:12 -07:00
Abdelatif Guettouche
0ca5fb4edc
arch/xtensa/esp32: When calling up_cpu_index no need to check if in SMP
...
mode. up_cpu_index already does that.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-03 19:52:12 -07:00
Abdelatif Guettouche
3e44c347fd
arch/xtensa/esp32_spi&i2c: Get the CPU index when attaching an
...
interrupt.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-03 19:52:12 -07:00
Xiang Xiao
21b69cfd5d
Replace all __attribute__((weak)) with weak_data/weak_function
...
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-07-29 21:55:21 -03:00
Xiang Xiao
007adc7736
Replace all __attribute__((section(x)) with locate_data(x)
...
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-07-29 21:55:21 -03:00
Xiang Xiao
b3f9ffbe72
Replace all __attribute__((aligned(x)) with aligned_data(x)
...
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-07-29 21:55:21 -03:00
Gustavo Henrique Nihei
a7a922611b
xtensa/esp32: Enable the allocation of multiple SPI Flash partitions
...
Currently the "esp32_spiflash_alloc_mtdpart" allocates a
statically-defined partition from "offset" and "size" set via
Kconfig.
This commit changes the function interface to receive those information
as arguments, enabling the creation of multiple MTD partitions with
different offsets and sizes.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-07-29 20:17:13 +02:00
Sara Souza
857414e95d
xtensa/esp32: expose SPI2 as a char driver
2021-07-27 09:55:49 -07:00
Sara Souza
400d927011
xtensa/esp32s2: Disable wdt and wrap it.
2021-07-26 19:44:30 -07:00
Sara Souza
5baeb7430b
xtensa/esp32: Wrap wdt deinitialization in a function
2021-07-26 19:44:30 -07:00
Gustavo Henrique Nihei
2d676f5e46
xtensa/esp32: Enable configuration of GPIO pad's drive strength
...
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-07-26 19:37:06 -07:00
jordi
f3af6edf93
Kconfig: add quotes in source to clean warnings from setconfig
...
To avoid the setconfig warning "style: quotes recommended around xxx in
source xxx"
2021-07-23 02:32:19 -07:00
Abdelatif Guettouche
e85b119363
arch/: Clean what was made during context
in distclean.
...
Cleaning during `clean_context` had the issue of remaking everything
when `menuconfig` was issued. That's because `menuconfig` has a
`clean_context` on its way.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-07-21 16:52:36 -03:00
Abdelatif Guettouche
315ba8c77f
esp32_allocateheap.c: Remove the amount reserved to himem from the heap.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-07-21 08:58:18 -07:00
Alan C. Assis
011c938116
Remove xtensa_backtrace.S reference from esp32s2 as well
2021-07-20 19:30:09 -07:00
Alan C. Assis
d2eeeee262
Fix xtensa_btdump() to look at the exception frame
...
Remove xtensa_backtrace_start() since it is not used anymore
2021-07-20 19:30:09 -07:00
Gustavo Henrique Nihei
df2e890cfc
xtensa/esp32: Implement MTDIOC_ERASESTATE for SPI Flash driver
...
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-07-17 09:00:41 -07:00
Xiang Xiao
98b5724b59
arch: Fix rtcb can't found error
...
use the same condition check in declaration and reference
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I7b05316e914708fceeddac394d784ee3720a3c1b
2021-07-16 12:48:09 -03:00
Sara Souza
c7bf5c7a1d
xtensa/esp32: Make UART TX DMA depends on EXPERIMENTAL and adds caveats regarding its use
2021-07-12 21:03:06 -07:00
Sara Souza
2abeba041d
xtensa/esp32: Fixes termios issue.
2021-07-12 21:02:26 -07:00
Xiang Xiao
76cdd5c329
mm: Remove mm_heap_impl_s struct
...
it's more simple to make mm_heap_s opaque outside of mm
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I5c8e435f6baba6d22b10c5f7e8d9191104fb5af2
2021-07-07 04:25:15 -07:00
Sara Souza
a5bf47b93e
xtensa/esp32: Fixes issue with UART 2
2021-07-05 23:20:26 -05:00
Sara Souza
d67852da4b
xtensa/esp32: Change default pins of UART2
2021-07-05 23:20:26 -05:00
Xiang Xiao
97216c220b
mm: Support malloc_size function
...
and rename malloc_usable_size to malloc_size
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-07-04 18:53:44 -03:00
Xiang Xiao
b1f711f790
mm: Move procfs_register_meminfo into common place
...
to avoid the code duplication and ensure the consistent behaviour
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-07-03 09:39:32 -07:00
Sara Souza
b45ccad6a0
xtensa/esp32: Adds support for SERIAL_TXDMA.
2021-07-01 01:50:13 -05:00
Sara Souza
87fabb2bc7
xtensa/esp32: Support to select different clock source for RTC controller and close TODOs.
2021-06-30 21:27:27 -05:00
Abdelatif Guettouche
553f070357
arch/xtensa/esp32: Remove up_textheap_init function since it's not
...
needed anymore.
Decouple the IRAM heap from the text allocator since that heap can
still be used as a generic pool of memory.
Implement the up_extraheaps_init function to initialize all of the
additional heaps.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-26 09:52:43 -05:00
Gustavo Henrique Nihei
db18a12844
xtensa/esp32: Move RTC WDT deinit after initial setup
...
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-06-25 10:58:39 -03:00
Gustavo Henrique Nihei
8c70e4f1c1
xtensa/esp32: Fix RTC watchdog timer deinit at startup
...
Write protection must be disabled before performing changes to the WDT
registers. Furthermore, the routine was resetting the wrong field from
the RTC WDT register.
The RTC_CNTL_WDT_FLASHBOOT_MOD_EN field relates to Flash Boot Protection
and it is enabled by the 1st stage bootloader. The 2nd stage bootloader
takes care of disabling it.
Then the 2nd stage bootloader enables the RTC WDT for checking the
startup sequence of the application image.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-06-25 10:58:39 -03:00
Abdelatif Guettouche
55a210d305
arch/xtensa/esp32_textheap.c: When allocating text prioritize alloacting
...
from the RTC heap. If that's not available fall back to the IRAM heap.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-23 08:37:01 +09:00
Abdelatif Guettouche
1e49f2929f
arch/xtensa/src/esp32: Extract the IRAM region as a separate heap.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-23 08:37:01 +09:00
Abdelatif Guettouche
1719e9df94
arch/xtensa/esp32: Add the RTC Slow memory as a separate heap.
...
This memory region can be accessed by both I & D buses, so the heap can
be used for data storage and code execution.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-23 08:37:01 +09:00
Abdelatif Guettouche
6582c19904
arch/xtensa/src/esp32/hardware/esp32_soc.h: Add a function to check if a
...
buffer comes from the RTC Slow memory.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-23 08:37:01 +09:00
Abdelatif Guettouche
a4289c4f84
xtensa/esp32_aes.c: Use the same output when testing the AES driver.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-21 06:23:55 -05:00
Masayuki Ishikawa
841fb02ac0
arch: esp32: Replace getcoreid with the latest esp-idf's
...
Summary:
- I noticed that the getcoreid macro in the latest esp-idf
is much simpler than the current NuttX's.
- This commit replaces the macro with the latest esp-idf's
Impact:
- SMP only
Testing:
- Tested with esp32-devkitc:wapi_smp
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-06-21 06:21:39 -05:00
chenwen
8648970994
esp32&esp32c3/wifi: Fix the issues of Wi-Fi configuration being overwritten
2021-06-19 08:00:35 -03:00
chenwen
c3792f0aae
xtensa/esp32: Support ESP32 RTC driver
2021-06-18 22:01:34 -05:00
Xiang Xiao
ab974edc84
sched: Identify the stack need to free by TCB_FLAG_FREE_STACK
...
instead calling kmm_heapmember or umm_heapmember because:
1.The stack supplied by caller may allocate from heap too
2.It's hard to implement these two function in ASan case
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I196377822b7c4643ab4f29b7c1dc41dcd7c4dab1
2021-06-18 05:44:41 -07:00
Abdelatif Guettouche
af5e0c620f
Rename MODULE_TEXT to TEXT_HEAP as the latter is more generic.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-18 07:14:17 -05:00
Sara Souza
00edeee1ff
xtensa/esp32: Adds I2C Bit banging reset
2021-06-18 00:48:27 -05:00
Masayuki Ishikawa
83ac6cd399
arch: xtensa: Remove ISYNC from xtensa_compareset()
...
Summary:
- According to the Xtensa ISA document, this ISYNC instruction
between WSR SCOMPARE1 and S32C1I is unnecessary
Impact:
- SMP only
Testing:
- Tested with esp32-devkitc:wapi_smp
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-06-17 09:58:29 -05:00
Masayuki Ishikawa
2d016f8d21
arch: xtensa: Fix the PS register handling
...
Summary:
- I noticed that DEBUGASSERT sometimes happens in nxsem_wait()
when testing Wi-Fi with esp32-devkitc:wsifi_smp
- The call stack was not from an interrupt handler and actually
g_current_regs[] were correct, even though asserted with
(up_interrupt_handler() == false)
- Finally, I found that we need to call rsync after we set
a new value to the PS register which is described in the
Xtensa document.
- This commit fixes this issue
Impact:
- All xtensa architectures
Testing:
- Tested with esp32-devkitc:wifi_smp and esp32-devkitc:wifi
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-06-17 09:58:29 -05:00
Sara Souza
7300bc8f1c
xtensa/esp32: Adds I2C polled support.
2021-06-13 05:04:51 -05:00
Xiang Xiao
c0fdddc5d7
arch: Remove all go_nx_start from chip specifc source
...
since the idle stack color is done in the common code now
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-06-10 06:50:41 -07:00
Xiang Xiao
fa0d123f87
arch: Colorize the idle thread stack in an unified way
...
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Idae8da53e5a4799a8edc0e882f17fd515b70cb14
2021-06-10 06:50:41 -07:00
Xiang Xiao
6576306bca
arch: Rename xxx_getsp to up_getsp
...
All modern desgin support stack pointer and it's also an
important information, so let's standardize this interface.
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-06-09 10:20:02 -07:00
Xiang Xiao
5b2a17b892
Include assert.h in necessary place
...
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-06-08 13:06:08 -07:00
Gustavo Henrique Nihei
0b3c2c7603
spi: Refactor SPI Slave interface prefix to sync with I2C Slave
2021-06-05 04:50:34 -07:00
Xiang Xiao
2e54df0f35
Don't include assert.h from public header file
...
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-06-03 08:36:03 -07:00
Sara Souza
7dd131b4c1
xtensa/esp32: Fixes support for HW flow control
2021-06-02 09:55:50 -05:00
Sara Souza
a54fe4ee1e
xtensa/esp32-s2: Add support for serial HW flow control.
2021-06-01 21:37:37 -05:00
Alan C. Assis
929a4a7278
Fix dangling whitespace at the end of line
2021-06-01 07:49:54 +02:00
Sara Souza
f1d653c08c
xtensa/esp32-s2: Adds support for serial driver, lowputc and termios.
2021-06-01 07:49:54 +02:00
Alan C. Assis
06795a221a
Clean ESP32S2 Xtensa files
2021-06-01 07:49:54 +02:00
Abdelatif Guettouche
fccd5fbdd2
esp32s2_allocateheap.c: Use the address of the ROM data from the ROM linker script.
2021-06-01 07:49:54 +02:00
Alan C. Assis
7767acd24a
Add initial ESP32S2 Xtensa support
2021-06-01 07:49:54 +02:00
Xiang Xiao
d7f96003cf
Don't include debug.h from public header file
...
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-06-01 06:42:02 +09:00
chenwen
1d1dd8512f
esp32&esp32c3/wifi: Support specific channel and bssid scan
2021-05-31 11:09:19 +01:00
Abdelatif Guettouche
45d01ae2a8
arch/xtensa/esp32_emac.c: Call phy_enable_interrupt correctly.
2021-05-28 20:46:27 -03:00
Abdelatif Guettouche
08aa9ce540
arch/xtensa/src/esp32/esp32_rt_timer: Fix typos and re-word some
...
comments.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-05-27 05:01:54 -07:00
Abdelatif Guettouche
0f3d94e8e8
arch/risc-v/src/esp32c3/esp32c3_rt_timer.h: Add section headers.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-05-27 05:01:54 -07:00
Abdelatif Guettouche
f24a687f8e
arch/xtensa/src/esp32/esp32_rt_timer.h: Add section headers.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-05-27 05:01:54 -07:00
Sara Souza
3144a5a272
xtensa: Fixes names of serial functions
2021-05-24 10:04:50 -05:00
Xiang Xiao
001e7c3e76
sched: Don't include nuttx/sched.h inside sched.h
...
But let nuttx/sched.h include sched.h instead to
avoid expose nuttx kernel API to userspace.
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-05-24 12:11:53 +09:00
Alan C. Assis
1a84314f5d
xtensa: #ifdef SYMBOL is always true if SYMBOL defined as 0
2021-05-22 08:35:12 -05:00
jordi
ccc8c078f9
xtensa/esp32: Fix warning "is not defined"
...
Detected with "-Werror" flag
2021-05-19 20:03:03 +01:00
Chen Wen
e44ec9e48e
xtensa/esp32: Fix code nxstyle issue
2021-05-19 06:45:42 -03:00
chenwen
f7db743152
xtensa/esp32: Support auto-sleep
2021-05-19 06:45:42 -03:00
chenwen
f50160f0e1
xtensa/esp32: Support tick-less OS
2021-05-19 06:45:42 -03:00
Abdelatif Guettouche
65e9ff5a48
xtensa/esp32/esp32_start.c: Remove an old and unnecessary piece of code.
...
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-05-19 03:05:52 -05:00
Sara Souza
873293cc3f
xtensa/esp32: Applies REG_MASK to extract a field value
2021-05-05 01:30:03 -07:00
Sara Souza
50daf24242
esp32/esp32-c3: Adds two helpers to extract and include a field value
2021-05-05 01:30:03 -07:00
Sara Souza
cce42d5f74
xtensa/esp32: Reorganize the pins initialization and adds showprogress in __start
2021-05-05 01:30:03 -07:00
Sara Souza
afd6b26232
xtensa/esp32: Replace serialout/in and fixes the fifo counter issue
2021-05-05 01:30:03 -07:00
Abdelatif Guettouche
e24af207f8
esp32/hardware: Include files of the same level by their names only and
...
remove unnecessary includes.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-05-05 01:28:22 -07:00
Gustavo Henrique Nihei
f8a36f10c3
arch: Uniformize optimization flag setting across architectures
2021-04-29 19:17:16 -07:00
Alan C. Assis
0a0a034a3f
esp32: replace EPS32 typo with ESP32
2021-04-29 18:03:05 -03:00
Gustavo Henrique Nihei
91955be0e1
xtensa/esp32: Change ESP32_RT_TIMER_TASK_PRIORITY comment into help text
2021-04-27 20:45:28 -06:00
Gustavo Henrique Nihei
2b179c5ab3
xtensa/esp32: Add missing default value for CONFIG_ESP32_GPIO_IRQ
2021-04-27 20:45:28 -06:00
Gustavo Henrique Nihei
95a76adc90
xtensa/esp32: Uniformize Kconfig alignment and styling
2021-04-27 20:45:28 -06:00
Gustavo Henrique Nihei
03c8e2d5c7
xtensa/esp32: Remove inconsistent usage of comment command
2021-04-27 20:45:28 -06:00
Gustavo Henrique Nihei
4d3fa83d7a
xtensa/esp32: Remove redundant dependency
2021-04-27 20:45:28 -06:00
chenwen
666d718302
xtensa/esp32: Fix crash issue caused by null pointer operation
2021-04-27 11:00:16 +01:00
Sara Souza
0c440cfdfe
xtensa/esp32: Reorganize the timer logic for wireless use
2021-04-22 21:38:16 -05:00
Dong Heng
fecdd27df3
esp32 & esp32c3: Update Wi-Fi BT and Wi-Fi libraries to fix some issues
2021-04-22 07:34:06 -03:00
Sara Souza
f696364b6a
xtensa/esp32: Adds freerun wrapper
2021-04-21 16:37:39 -03:00
Masayuki Ishikawa
1b00e5d518
spinlock: Remove SP_SECTION
...
Summary:
- SP_SECTION was introduced to allocate spinlock in non-cachable
region mainly for Cortex-A to stabilize the NuttX SMP kernel
- However, all spinlocks are now allocated in cachable area and
works without any problems
- So SP_SECTION should be removed to simplify the kernel code
Impact:
- None
Testing:
- Build test only
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-04-20 22:41:44 -05:00
Masayuki Ishikawa
1a9e7efde5
smp: Remove CONFIG_SMP_IDLETHREAD_STACKSIZE
...
Summary:
- The CONFIG_SMP_IDLETHREAD_STACKSIZE was introduced to optimize
the idle stack size for other than CPU0
- However, there are no big differences between the idle stacks.
- This commit removes the config to simplify the kernel code
Impact:
- All SMP configurations
Testing:
- Tested with ostest with the following configs
- spresense:smp, spresense:rndis_smp
- esp32-devkitc:smp (QEMU), maix-bit:smp (QEMU)
- sabre-6quad:smp (QEMU), sabre-6quad:netnsh_smp (QEMU)
- raspberrypi-pico:smp, sim:smp (x86_64)
Signed-off-by: Masayuki Ishikawa <asayuki.Ishikawa@jp.sony.com>
2021-04-19 21:46:39 -05:00
Abdelatif Guettouche
c1b0ee436c
arch/xtensa/src/esp32/Kconfig: Make bank switching default to disabled.
...
This config is only useful when there is a > 4MB PSRAM and thus needs to
be selected by the user explicitly.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-04-19 07:48:35 -05:00
Xiang Xiao
2335b69120
arch: Allocate the space from the beginning in up_stack_frame
...
arch: Allocate the space from the beginning in up_stack_frame
and modify the affected portion:
1.Correct the stack dump and check
2.Allocate tls_info_s by up_stack_frame too
3.Move the stack fork allocation from arch to sched
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-04-16 12:41:41 +09:00
Xiang Xiao
8640d82ce0
arch: Rename g_intstackbase to g_intstacktop
...
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-04-16 12:41:41 +09:00
YAMAMOTO Takashi
3806803a7a
arch/xtensa/src/esp32/esp32_user.c: Implement L16SI emulation
...
I don't know why this was not necessary before.
Probably I was just lucky about the combination of configs.
Or maybe some of recent changes happened to make the compiler
to use the instruction.
```
400d38f0 <mm_givesemaphore>:
400d38f0: 004136 entry a1, 32
400d38f3: 228c beqz.n a2, 400d38f9 <mm_givesemaphore+0x9>
400d38f5: 0228 l32i.n a2, a2, 0
400d38f7: 52cc bnez.n a2, 400d3900 <mm_givesemaphore+0x10>
400d38f9: fea0b2 movi a11, 254
400d38fc: 000306 j 400d390c <mm_givesemaphore+0x1c>
400d38ff: 00 .byte 00
400d3900: 019232 l16si a3, a2, 2
400d3903: feebe5 call8 400d27c0 <getpid>
400d3906: 0813a7 beq a3, a10, 400d3912 <mm_givesemaphore+0x22>
400d3909: 05a1b2 movi a11, 0x105
400d390c: f241a1 l32r a10, 400d0210 <_stext+0x1f0>
400d390f: ff23e5 call8 400d2b4c <_assert>
400d3912: 1288 l32i.n a8, a2, 4
400d3914: 0828a6 blti a8, 2, 400d3920 <mm_givesemaphore+0x30>
400d3917: 880b addi.n a8, a8, -1
400d3919: 1289 s32i.n a8, a2, 4
400d391b: 000606 j 400d3937 <mm_givesemaphore+0x47>
400d391e: 00 .byte 00
400d391f: 00 .byte 00
400d3920: ffaf82 movi a8, -1
400d3923: 015282 s16i a8, a2, 2
400d3926: 00a082 movi a8, 0
400d3929: 016282 s32i a8, a2, 4
400d392c: 02ad mov.n a10, a2
400d392e: feb125 call8 400d2440 <sem_post>
400d3931: 19a1b2 movi a11, 0x119
400d3934: fd4a96 bltz a10, 400d390c <mm_givesemaphore+0x1c>
400d3937: f01d retw.n
400d3939: 000000 ill
```
2021-04-15 12:18:52 +01:00
YAMAMOTO Takashi
a28de1d681
arch/xtensa/src/esp32/esp32_user.c: Fix S16I/L16LU emulation
...
I misunderstood how imm8 is used to calculate the address.
2021-04-15 12:18:52 +01:00
YAMAMOTO Takashi
51490bad55
modlib: Implement sh_addralign handling
...
I've seen a module with 16 bytes .rodata alignment for xmm operations.
It was getting SEGV on sim/Linux because of the alignment issue.
The same module binary seems working fine after applying this patch.
Also, tested on sim/macOS and esp32 on qemu,
using a module with an artificially large alignment. (64 bytes)
2021-04-14 21:17:07 -05:00
Alan Carvalho
ac5fb7d701
esp32: Fix GPIO Pull-Up/Pull-Down using RTC GPIO
...
Some ESP32 GPIO pins (2, 4, 12, 13, 25, 27, 32) weren't accepting
pull-up/pull-down resistors. These pins are RTC GPIO pins and need
to have pull-up/pull-down configured in the RTC registers.
Co-authored-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-04-11 14:36:02 +01:00
Xiang Xiao
3f67c67aaf
arch: Fix the stack boundary calculation and check
...
All supported arch uses a push-down stack:
The stack grows toward lower addresses in memory. The stack pointer
register points to the lowest, valid working address (the "top" of
the stack). Items on the stack are referenced as positive(include zero)
word offsets from sp.
Which means that for stack in the [begin, begin + size):
1.The initial SP point to begin + size
2.push equals sub and then store
3.pop equals load and then add
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-04-10 08:39:54 -07:00
Xiang Xiao
0fdde5be26
arch/esp32: Fix error: Mixed case identifier found
...
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-04-10 12:00:06 +01:00
Gustavo Henrique Nihei
4d4250fcca
xtensa/esp32: Improve SPI polling to use the entire HW buffer
2021-04-08 23:36:28 -05:00
Matias N
ab206687bb
Replace wrong inclusion of sys/errno.h (toolchain provided) with errno.h
2021-04-07 21:27:06 -05:00
Alin Jerpelea
cb2ecefbf1
arch: xtensa: fix nxstyle errors
...
Fix for errors reported by nxstyle tool
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-04-07 21:21:51 -05:00
Matias N
d88b5aac97
esp32: move common XTAL and RUN_IRAM configs to ESP32 KConfig
2021-04-07 21:45:48 +01:00
Alan Carvalho de Assis
bac84de45f
esp32c3: Add support to RNG driver
...
Co-authored-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-04-03 07:20:03 -05:00
Alan C. Assis
18f88c35fc
esp32: Fix small typo that will trigger an error when IPv6 is enabled
2021-04-03 00:53:02 -05:00
Alin Jerpelea
778f050102
arch: xtensa: Author Gregory Nutt: update licenses to Apache
...
Gregory Nutt has submitted the SGA and we can migrate the licenses
to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-04-02 03:14:31 -05:00
Gustavo Henrique Nihei
2d0e690803
xtensa/esp32: Refactor register access functions on SPI driver
2021-04-01 17:13:55 -03:00
Alin Jerpelea
3d96d5f2ce
arch: esp32: Mixed Case identifier fix
...
Fix Mixed Case Identifier reported by nxstyle
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-04-01 12:13:12 -05:00
Alin Jerpelea
4e26e39ffe
arch: xtensa: Espressif Systems: update licenses to Apache
...
Espressif Systems has submitted the SGA and we can migrate the licenses
to Apache.
Gregory Nutt has submitted the SGA and we can migrate the licenses
to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-04-01 12:13:12 -05:00
Matias N
8ed2bb8eb5
esp32: remove unneeded "INFO" and "ERROR" prefixes to syslog calls
2021-03-31 07:37:18 -03:00
Matias N
a5a435e98f
esp32: remove extra initial newline on syslog call
2021-03-31 10:04:42 +01:00
Gustavo Henrique Nihei
77c5995f93
xtensa/esp32: Use essential boolean expressions on condition statements
2021-03-30 01:23:02 -05:00
Gustavo Henrique Nihei
5e8eb420b7
xtensa/esp32: Fix MISO/MOSI data length field configuration
...
Both fields were being configured with the total number of remaining
bytes instead of the number of bytes actually bound to DMA descriptors.
2021-03-30 01:23:02 -05:00
Gustavo Henrique Nihei
b4dbae1b10
xtensa/esp32: Commit setbits configuration before SPI transaction
...
The motivation is to avoid consistency issues when using Mixed Mode
(i.e. Polling and Interrupt/DMA transfers being used interchangeably)
2021-03-30 01:23:02 -05:00
Gustavo Henrique Nihei
4d877abf3f
xtensa/esp32: Avoid incrementing a NULL pointer for RX buffer
2021-03-30 01:23:02 -05:00
Gustavo Henrique Nihei
a27d5b1063
xtensa/esp32: Remove useless pointer check in SPI DMA exchange
2021-03-30 01:23:02 -05:00
Brennan Ashton
0a3b20e546
syslog: Drop extra carriage return from syslog calls
2021-03-28 21:24:00 -05:00
Gustavo Henrique Nihei
96037f01d5
xtensa/esp32: Clean up unused include headers from DMA driver
2021-03-26 23:40:44 -05:00
Gustavo Henrique Nihei
d3342795a8
xtensa/esp32: Fix wrong math round operation on DMA init
2021-03-26 23:40:44 -05:00
Gustavo Henrique Nihei
eb505ed866
xtensa/esp32: Fix DMA burst mode being unintendedly disabled
2021-03-26 23:39:53 -05:00
Sara Souza
59313c86d1
xtensa/esp32: Adds oneshot timer driver.
2021-03-24 16:01:26 -03:00
chenwen
f54aef9977
xtensa/esp32: Support esp32 wireless ioctl cmd
2021-03-23 16:29:52 -03:00
Abdelatif Guettouche
fcafacb9a3
esp32_allocateheap.c: Adjust the region of the heap coming from the
...
external memory when a BSS section is allowed to reside there.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-03-23 16:39:01 +09:00
Abdelatif Guettouche
cc23bdeca4
boards/xtensa/esp32: Add a section in external memory to hold some BSS
...
data.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-03-23 16:39:01 +09:00
YAMAMOTO Takashi
37300a43a5
esp32_part_ioctl: Return -ENOTTY for unknown commands
...
It's traditional to use ENOTTY for this purpose.
Littlefs seems to rely on this behavior for BIOC_FLUSH.
Also, drop the log level.
2021-03-22 19:49:27 -07:00
Gustavo Henrique Nihei
e4efa9dfa7
xtensa/esp32: Fix interrupt flag configuration for DMA transfers
...
Previously SPI interrupts were enabled on DMA initialization. But since
the addition of SPI Mixed mode it created a side-effect, breaking
polling transfers. So now interrupts are enabled before the DMA
transactions and disabled once they are finished.
Furthermore, the transaction done flag is also cleared before a new
transaction starts.
2021-03-21 00:16:59 -07:00
Gustavo Henrique Nihei
20d24fe148
xtensa/esp32: Fix esp32_spi_setbits for Polling when DMA is also enabled
...
Commit 6382b2ba introduced the possibility of using SPI in Mixed mode,
i.e. performing SPI transfers via both polling and interrupts. However,
setbits was only applying the configuration if DMA was not enabled.
2021-03-21 00:16:59 -07:00
Gustavo Henrique Nihei
27e2da33b4
xtensa/esp32: Fix buffer size word-alignment for DMA transfers
2021-03-20 19:23:44 -07:00
Gustavo Henrique Nihei
bfc551484a
xtensa/esp32: Clean up esp32_dma_init code
...
Removed "isrx" parameter whose only purpose is to trigger an assertion
on DEBUG builds. Also performed a minor refactor.
2021-03-20 19:23:44 -07:00
Gustavo Henrique Nihei
dc7a0b0a5c
xtensa/esp32: Use Polling instead of DMA for transfers below threshold
...
Also refactored code to remove a confusing duplicate "dma_chan" field
which had the same purpose of the "use_dma" boolean.
2021-03-19 23:13:32 -07:00
Abdelatif Guettouche
27d5c9340a
esp32_allocateheap.c: Don't allocate the ROM CPU regions the same way in
...
QEMU, the image is different.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-03-18 11:28:36 +09:00
Jiuzhu Dong
e96c8b9283
fs: allocate file/socket dynamically
...
Change-Id: I8aea63eaf0275f47f21fc8d5482b51ffecd5c906
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2021-03-17 06:46:42 -07:00
Dong Heng
b2f5031e96
xtensa/esp32: Refactor ESP32 WiFi driver to support station and softAP coexistence
2021-03-16 10:20:59 -03:00
Abdelatif Guettouche
28160823b6
arch/xtensa/esp32: ~6KB of memory at address 0x3ffae6f0 is not used by
...
the ROM bootloader, add that to the heap as well.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-03-16 16:22:08 +09:00
Abdelatif Guettouche
8389e83742
esp32/memory_layout.h: Update the layout taking under consideration the
...
changes to the heap regions and to the internal heap.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-03-16 16:22:08 +09:00
Abdelatif Guettouche
9cfc30fa85
memory_layout.h: Fix the start of region2 when a QEMU image generation
...
is enabled.
That region is technically part of the PRO CPU and we should be able to
allocate it early. However, QEMU uses a slightly different bootloader
image that uses the same part for both CPU. So, when APP CPU starts
during the SMP bring up it will corrupt some data.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-03-16 16:22:08 +09:00
Abdelatif Guettouche
7fbc350589
xtensa/esp32: Warn about unused memory regions.
...
In case CONFIG_MM_REGIONS doesn't include all the available memory
regions the user will have a warning to increase it.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-03-16 16:22:08 +09:00
Abdelatif Guettouche
5c7d041b91
arch/xtensa/esp32: In SMP case move the internal memory to region 3.
...
Region 2 is only 15KB in SMP, so we don't have enough memory to play
with.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-03-16 16:22:08 +09:00
Abdelatif Guettouche
cba44928d2
arch/xtensa/esp32: Part of the ROM regions in middle of DRAM are not
...
used, retrieve them as heap.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-03-16 16:22:08 +09:00
Abdelatif Guettouche
a68a39c785
xtensa/esp32: Move internal heap to the beginning of region 2.
...
Internal heap was occupying the region straight after .data up to
HEAP_REGION1. The issue with this is if static allocation is large,
we'll end up with too little memory left for the internal heap.
Moving it to the beginning of region 2 gives us more room to play with.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-03-16 16:22:08 +09:00
Sara Souza
4ca0c6e3c8
xtensa/esp32: timer driver refactor
2021-03-14 20:22:36 -03:00
Alin Jerpelea
bd94263a33
arch: Makefile: Author Gregory Nutt: update licenses to Apache
...
Gregory Nutt has submitted the SGA and we can migrate the licenses
to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-03-13 05:56:43 -08:00