Make a separate config flag for enabling L2 cache. This is on by
default when compiling a standalone/bootloader configuration, but
can also be disabled for special cases, such as memory testing
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Summary:
- This commit refactors the entry point name for BUILD_KERNEL
to avoid misunderstanding the name
Impact:
- None
Testing:
- Tested with rv-virt:ksmp64
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I noticed that the OS timer sometimes proceeds fast when
a task is scheduled to run on CPUO via IPI.
- Actually, qemu-rv implementation shares supervisor software
interrupt for both timer and IPI on CPU0.
- This commit fixes this issue.
Impact:
- qemu-rv only
Testing:
- Tested with qemu-6.2
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit adds SMP support for BUILD_KERNEL
Impact:
- RISC-V: BUILD_KERNEL + SMP only
Testing:
- Tested with rv-virt:ksmp64 (will be added later)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Run-time check for L3 page table size, to ensure it is large enough
to map all of the kernel memory.
NOTE: The check has to be run-time, as KFLASH_SIZE/KSRAM_SIZE are really
linker relocation symbols, and thus cannot be utilized compile-time.
L3 table maps 2MB of memory, this brings an implicit requirement for
any L3 region to be aligned to 2MB. This commit adds build time sanity
checks to ensure this requirement is met.
For other SvXX architectures the boundary requirement (might be) is
different.
Summary:
- This commit introduces g_percpu_spin to avoid deadlock
in riscv_percpu.c instead of using the global spinlock.
Impact:
- None
Testing:
- Tested with rv-virt:knsh64 and rv-virt:ksmp64 (will be added later)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This allows properly using 10/100Mbps also with 1G phy. Some gigabit PHYs
come out of reset with 1G advertisement enabled, causing other devices to
set up link with 1G. If, after this, the link is set to 10/100 on the mpfs,
the link won't work.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Summary:
- In RISC-V, BUILD_KERNEL uses S-mode and to use M-mode timer
we need to handle it by using OpenSBI or self-implementation.
- This commit adds M-timer self-implementation for BUILD_KERNEL.
Impact:
- qemu-rv only
Testing:
- Tested with rv-virt:knsh64 on qemu-6.2
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I found inappropriate SET_CSR() usage in the function.
- This PR fixes this issue.
Impact:
- None
Testing:
- tested with rv-virt:knsh64
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I noticed that the OpenSBI library depends on the BSD license
- This commit fixes this issue
Impact:
- CONFIG_OPENSBI=y only
Testing:
- Build with icicle:opensbi (will be updated later)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Because a context switch issue still exists with FPU
the configs should be removed until it works.
Impact:
- None
Testing:
- Tested with ostest
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
undeclare TCGETS on esp32c3 when enable usbserial and termios
error:
chip/esp32c3_usbserial.c: In function 'esp32c3_ioctl':
chip/esp32c3_usbserial.c:411:10: error: 'TCGETS' undeclared (first use in this function)
Situation:
Assume we have 2 cpus, and busy run task0.
CPU0 CPU1
task0 -> task1 task2 -> task0
1. remove task0 form runninglist
2. take task1 as new tcb
3. add task0 to blocklist
4. clear spinlock
4.1 remove task2 form runninglist
4.2 take task0 as new tcb
4.3 add task2 to blocklist
4.4 use svc ISR swith to task0
4.5 crash
5. use svc ISR swith to task1
Fix:
Move clear spinlock to the end of svc ISR
Signed-off-by: ligd <liguiding1@xiaomi.com>
Simplify the clock mode from the board.h -files. Also make the
SD clock definable as well.
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Some related products, such as Aries m100pfs, don't support eMMC
speeds up to 200MHz. Thus, provide option to select slower clock.
This has only to do with the clocking, no CMD6 is sent to select
high speed modes.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
The L3 mapping function was just way too simplistic. Depending on memory
configuration it either works or not.
Noticed that with icicle:pnsh the software crashes due to instruction
page fault, reason is the map_region() implementation that does not
work for regions that are not aligned to 2MB (the L2 page size).
Implemented an extremely simplistic page table allocator for the L3
references, that should once and for all get rid of the L3 mapping issue.
NOTE: gran_alloc() cannot be used at this point, it is too early for it.
If the system starts up using the SD-card, and later wants
to switch to use the eMMC, it's not going to happen. SD-card
will be kept selected within the FPGA making the transition
fail.
It's been possible to switch from eMMC to SD, but now the
transition is possible for both directions.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Issuing the following commands doesn't succeed:
- conn
- disconn
- conn
This USB driver doesn't even disconnect without this patch.
If the USB driver has been started from another hart, closing it
will not disable the PLIC interrupt. This means it's possible many
harts get the USB interrupt and thus make the USB look very unstable.
Fix these problems by disconnecting the USB via the USB_POWER
register at shutdown and disabling the interrupt at shutdown. Also
clear the software internals via the mpfs_sw_setup() for the conn /
disconect loop to succeed.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
The underlying hardware supports 9 endpoints:
- EP0
- 4x IN EPs
- 4x OUT EPs
Currently the driver assumes every EP number is unique. This limits
the amount of EPs to 1 + 4 = 5. Utilize the EPs in such a manner
that all may be used.
Also fix a few error handling related bugs. Update the composite
driver to match the current situation as well.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
==2117790==ERROR: AddressSanitizer: global-buffer-overflow on address 0x64d9e3c0 at pc 0x59ac4e16 bp 0xcefe8058 sp 0xcefe8048
READ of size 1 at 0x64d9e3c0 thread T0
#0 0x59ac4e15 in up_nputs sim/up_nputs.c:54
#1 0x59a67e4c in syslog_default_write syslog/syslog_channel.c:220
#2 0x59a67823 in syslog_default_write syslog/syslog_write.c:101
#3 0x59a67f10 in syslog_write syslog/syslog_write.c:153
#4 0x59a651c3 in syslogstream_flush syslog/syslog_stream.c:60
#5 0x59a6564e in syslogstream_addchar syslog/syslog_stream.c:104
#6 0x59a6576f in syslogstream_putc syslog/syslog_stream.c:140
#7 0x5989fc4d in vsprintf_internal stdio/lib_libvsprintf.c:952
#8 0x598a1298 in lib_vsprintf stdio/lib_libvsprintf.c:1379
#9 0x59a64ea4 in nx_vsyslog syslog/vsyslog.c:223
#10 0x598a601a in vsyslog syslog/lib_syslog.c:68
#11 0x59b0e3dc in AIOTJS::logPrintf(int, char const*, ...) src/ajs_log.cpp:45
#12 0x59b03d56 in jse_dump_obj src/jse/quickjs/jse_quickjs.cpp:569
#13 0x59b03ea1 in jse_dump_error1(JSContext*, unsigned long long) src/jse/quickjs/jse_quickjs.cpp:602
#14 0x59b03dd9 in jse_dump_error(JSContext*) src/jse/quickjs/jse_quickjs.cpp:591
#15 0x59bed615 in ferry::DomComponent::callHook(char const*) src/framework/dom/component.cpp:65
#16 0x59bfe0ff in ferry::DomComponent::initialize() src/framework/dom/component.cpp:645
#17 0x59bb141d in dom_create_component(JSContext*, unsigned long long, unsigned long long, unsigned long long) (/home/wangbowen/project/central/vela_miot_bes_m0/bin/audio+0x365c41d)
#18 0x59b4c0d3 in AIOTJS::__createComponent(JSContext*, unsigned long long, int, unsigned long long*) (/home/wangbowen/project/central/vela_miot_bes_m0/bin/audio+0x35f70d3)
#19 0x5a56ec17 in js_call_c_function quickjs/quickjs.c:16108
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
Summary:
- I noticed that ps shows incorrect stack usage when running
getprime in the background.
- With CONFIG_ARCH_ADDRENV=y, a user task including pthread
allocates its stack in the user space that needs to be
accessed with a correct address environment.
- This commit fixes this issue.
Impact:
- CONFIG_ARCH_ADDRENV=y only
Testing:
- Tested with rv-virt:knsh64 on qemu-6.2
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Current RISC-V/NuttX implementation assumes that text/data/heap
areas are continuous. In fact, CONFIG_ARCH_TEXT_VBASE and
CONFIG_ARCH_HEAP_VBASE are not used for memory allocation.
- This commit assigns dedicated virtual addresses for text and heap
which are the same approach to ARM-v7A/NuttX implementation.
Impact:
- None
Testing:
- Tested with rv-virt:knsh64 (will be updated later)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
mpfs_write_tx_fifo() gets stuck in the following case:
- CDCACM is used
- ttyACM0 is opened and then closed from the remote end,
such as Linux or Windows
- data is written into ttyACM0 from NuttX
- tx fifo will never get empty and the system is stuck
Fix this by issuing an error code if the transmit fifo doesn't
proceed as expected. The error code is then propagated into
higher level keeping the system functional.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
nxsig_usleep() will wait for the next timer tick which is way
too much here. It's not sleeping 100 us, but rather, near 1/60 s.
This causes severe performance problems. Fix this by polling the
register for a while if the remote end is busy.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
- Clarify the macros MSSIO_EC_DEFAULT and MSSIO_EC_USB_DEFAULT
- Remove PULLDOWN bit from MSSIO_EC_DEFAULT, it was on by accident
- Fix some EC configuration macros; DRVSTR was wrong, clean up the others
- Define GPIO_PULLUP and GPIO_PULLDOWN like on many other platforms
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Since the commit cf22dd8 (related to OpenAMP update), the notifyid
is no longer NOTIFY_ALL, but the vq id.
Utilize the vq id now properly as it's being provided. However,
vq id 0 generates action.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
so the user could disable the full image instrumentation,
but enable the instrumentation by files or directories.
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
so the user could disable the full image instrumentation,
but enable the instrumentation by files or directories.
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
without UBSan
```
text data bss dec hex filename
85612 208 142258 228078 37aee nuttx
```
with UBSan:
```
text data bss dec hex filename
194290 98164 208634 501088 7a560 nuttx
```
```c
int main(int argc, FAR char *argv[])
{
uint32_t ptr[32];
printf("Hello, World!! %lu\n", ptr[64]);
return 0;
}
```
Try to run this sample:
```
nsh> hello
ubsan_prologue: ================================================================================
ubsan_prologue: UBSAN: array-index-out-of-bounds in hello_main.c:39:37
__ubsan_handle_out_of_bounds: index 64 is out of range for type 'uint32_t [32]'
ubsan_epilogue: ================================================================================
Hello, World!! 1070182368
nsh>
```
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
OpenSBI vendor extension calls must not cause scheduling, as they're
part of M-mode trap handling. Thus, comment out nxsig_usleep() as
well, which is occasionally taken and crashes the system in that
case. Fix this by commenting out lines that have the potential to
cause scheduling.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Summary:
- I noticed that QEMU shows high CPU usage if the number of
CPUs does not match the kernel configuration. (e.g. -smp 8
and CONFIG_SMP_NCPUS=2)
- This commit fixes this issue.
Impact:
- qemu-rv only
Testing:
- Tested with the following configs
- rv-virt:smp64 (CONFIG_NCPUS=1/2/8)
- rv-virt:nsh64
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
It is not really needed; g_hart_stacks is only used during SBI init as
a temporary stack area. We can use the scratch area buffers for this, as
the scratch areas define almost 4K of extra space, which is used for
exception stacks anyway.
The L3 table address was calculated incorrectly. For every 2MiB of
mapped memory, an offset of 4KiB is needed from the base of the L3
table. The old calculation failed if paddr was not aligned to a 2MiB
boundary.
RX_FIFO_ADDRs and TX_FIFO_ADDR were misconfigured. These addresses
overlapped causing data corruption during high USB loads. For
example, data corruption was present during the following conditions:
1. Composite USB driver was used (CDC/ACM + Mass storage)
2. /dev/ttyACM0 was accessed instantly from Linux side when
starting up.
3. Training data was sent to /dev/ttyACM0 from NuttX from the
very beginning periodically.
It was observed that while Mass storage was negotiating, sometimes
data sent from NuttX to Linux via CDC/ACM was corrupt, although it
was sent properly on the TX fifo.
Also, don't access TXCSRL_REG_EPN_TX_FIFO_NE_MASK for EP0 as it's
not applicable.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Initialize .domains_init function entry point in sbi_platform_operations when
CONFIG_OPENSBI_DOMAINS=y. In this case, the board specific code must provide
the "board_domains_init" function.
Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
With faster data transfer rates, it was seen that the read
requests occasionally were issued while the USB RX operation
was actually in progress. This patch makes sure the system
doesn't accidentally read the RX fifo while it's being filled
up, but rather, checks for the RXCSRL_REG_EPN_RX_PKT_RDY_MASK
flag. This flag indicates the packet is ready to be read.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
cache_dbus_mmu_set and cache_ibus_mmu_set return positive values in case
of errors, so DEBUVERIFY could never detect them since this macro checks
for negative values.
Besides, the successful execution of those functions is mandatory for
the reliable operation under Protected Mode, so the verification is
always performed, even when DEBUG is not enabled.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
forget to update in this patch:
commit b02db04e00
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
Date: Sun Jun 5 17:10:19 2022 +0800
arch/assert: Keep the thread dump column order same as ps
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
1.Move __XSTR from include/arch.h to include/irq.h
2.Move FLOAD/FSTORE and REGLOAD/REGSTORE from include/arch.h to src/common/riscv_internal.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
The "p" format specifier already prepends the pointer address with "0x"
when printing.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Starting the rptun with the autostart flag set will cause significant
delays at the boot, as it will wait for the master to be up. U-boot/linux
combination may take more than 10 seconds to boot to the point where the
rpmsg bus is initialized.
For now, the user needs to initialize the rptun separately, for example,
by issuing the following command:
rptun start /dev/rptun/mpfs-ihc
This command will also block if started before the rpmsg bus master is up.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Move the linker defined symbols to a separate file, so they can be
accessed without pulling in everything from riscv_internal.h and
whatever it includes (e.g. syscall.h drags in a lot).
Add a function to easily enable event handling on fabric and mss gpios. This
is similar to what exists e.g. for stm32 arm chips.
Also fix some small bugs in mpfs_configgpio related to IRQ bits configuration
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This patch fixes the following issues:
1. MPFS_EMMCSD_HRS06_EMM bitmask had to be 0x7, not 0x03
2. putreg32() caused outright memory corruption as the
arguments were in wrong order
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
The old implementation needed a contiguous memory block for user
ROM/RAM. This is because there was only 1 L3 page table which can only
map a contiguous memory area.
Also, remove the PMP configuration which just complicates things,
rely on the MMU mappings instead.
Update PLL configuration parameters to match the values provided
by the vendor.
Also remove extra call to mpfs_pll_config() as it's already called
at mpfs_clockconfig().
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Summary:
- I noticed that sometimes uart shows nothing on the maix-bit board.
- This commit adds a workaround to avoid such the issue
Impact:
- k210 only
Testing:
- Tested with maix-bit
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This provides USB composite (CDC/ACM and Mass Storage) support
for mpfs board. In addition, a number of USB fixes are included:
- Support for Setup Out packets
- Proper support for larger than packet size writes
- Finishing setup packets properly
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Output "X" with showprogress and make a system reset.
Silently ignoring failed training is dangerous and will cause random behaviour if DDR is used
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
since the code could map the unsupported work to the
supported one and remove select SCHED_WORKQUEUE from
Kconfig since SCHED_[L|H]PWORK already do the selection
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Linux kernel uses M-mode trap for handling Inter-Hart Communication (IHC).
This patch provides all the required functionalities for this purpose.
Previously, HSS bootloader was required. Now, NuttX is run as the
bootloader providing OpenSBI vendor extensions instead. This setup has
been tested on the following configuration:
- Hart 0 has NuttX in bootloader mode with OpenSBI
- Hart 1 unused
- Hart 2 has NuttX configured at 0xa2000000
- Hart 3 has U-boot / Linux kernel (at 0x80200000)
- Hart 4 has U-boot / Linux kernel (at 0x80200000)
Upon startup, NuttX on hart 0 will initialize SD-card driver, loads
the hart 2 NuttX from the SD-card and loads the U-boot to 0x80200000.
Also the nuttx.sbi -binary is loaded from SD-card into address 0x80000000,
which is also marked as reserved area in the Linux kernel device tree (for
the chuck 0x80000000 - 0x80200000).
Hart 2 NuttX waits until Linux kernel (IHC master) is started. After the
initial handshake, RPMsg / virtIO bus along with the IHC may be used for
proper AMP mode.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Summary:
- I noticed that rv-virt:knsh64 crashes when it executes the init.
- This commit fixes this issue.
Impact:
- None
Testing:
- Tested with rv-virt:knsh64
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
The FPU register saving upon vfork entry was missing.
Also added macro that tells the actual size of an FPU reg, instead
of just having a coefficient for qfpu/no-qfpu.
- Remove most of the ifeq-conditions and replace them with variables.
- Move the -I flag for 3rd party headers to opensbi/Make.defs
This clean-up / generalization makes it much simpler to add a new SBI
implementation, without the need to add a bunch of ifeq / elif conditions
to the makefile.
Let the user pick what runs on the harts. For example, the
default configuration now supports NuttX on hart2 and Linux
kernel on harts 3 and 4. Also fix a few issues in the code.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
g_mpfs_ack_sig and g_mpfs_rx_sig are better used with
SEM_INITIALIZER(0) (signalling) rather than with
SEM_INITIALIZER(1) (mutual exclusion).
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
PR#6249 was already merged without the review fixes. Provide the
fixes here on a separate patch.
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Summary:
- This commit adds MMU support for qemu-rv
- Please note that mtimer is disabled for S-mode because
the mtimer needs to be accessed in M-mode
Impact:
- qemu-rv only
Testing:
- Tested with rv-virt:knsh64 (will be pushed later)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This provides an example of Asymmetric Multiprocessing (AMP). The
master from Linux sends pings that this NuttX echoes back. The system
uses RPMsg from OpenAMP.
The Inter-Hart Communication module is present in the vendor's software
stack with the tag "2021.11". The software is present on github at the
polarfire-soc project. The following conditions must be met:
1. FPGA programmed with 2021.11 software
2. HSS (Vendor bootloader) with 2021.11 software
3. U-boot and Linux kernel from 2011.11 software
Currently the IHC works as a slave only on the hart number 4.
On the NuttX side, this patch uses rptun that incorporates rpmsg and
virtio. If it used only rpmsg and virtio, the future maintenance would
likely be much heavier. Using rptun also simplifies many things.
Upon success, the master side from Linux may issue an example test:
root@icicle-kit-es-amp:/opt/microchip/amp/rpmsg-pingpong# ./rpmsg-pingpong
However, the rpmsg-pingpong.c (compiled on target with gcc), may need to
be modified as seen below to match the device id:
- char *rpmsg_dev="virtio0.rpmsg-amp-demo-channel.-1.0";
+ char *rpmsg_dev="virtio0.rpmsg-amp-demo-channel.-1.1024";
This work uses a separate linker script. Due to a bug yet unknown to date,
a small NuttX, when loaded by the vendor HSS bootloader, will cause the
Linux kernel to hang at boot. Thus, the binary size is increased with
a section 'filler_area' whose only purpose is to increase the image size
so that the Linux kernel will boot up.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Implement a generic access rights modification procedure instead
of the procedures that only do one thing (enable/disable write)
to one section (text).
Summary:
- Because a context switch issue still exists with FPU,
it should be enabled only if EXPERIMENTAL=y
Impact:
- None
Testing:
- Tested with ostest
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
When the .elf file is loaded from disk, the kernel must be given write
access to the allocated .text section in the task's address environment.
The access is removed after the elf is loaded and relocations are done.
NOTE:
The reason this works for the ARM implementation, is that the ARM MMU
can be configured to give write access for the privileged mode, but
revoke write access for the user mode.
Regardless, it would be smart to revoke write access even for the
kernel, when the kernel does not need it. This framework allows doing
that, if someone wishes to take up the task.
Summary:
- This commit adds support for semihosting and hostfs
Impact:
- None
Testing:
- Tested with nsh and nsh64 (defconfig will be updated later)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Mappings are done with vaddr=paddr.
- I/O space mapped with two gigapages
- Kernel space mapped to statically allocated page tables. 2MB of kernel
memory is supported.
- Page pool is mapped to the kernel space, to allow virtual memory access
for the kernel e.g. to initialize the page memory when it is allocated.
by renaming riscv_dispatch_syscall to sys_callx, so the caller
don't need the immediate step(syscallx->riscv_dispatch_syscall)
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Using the Kconfig macro does not work for RISC-V target, as there the
user heap follows .data/.bss and does not obey any Kconfig provided
boundary.
Added stubs for ARM and Z80 also.
Copy the kernel mappings to the new (user) address environment. The
copyuing is done exactly once. This relies on the fact that the kernel
L1/L2 mappings will never change, as all of the kernel memory is mapped
upon boot.
This implements initial support for kernel build (address environments,
page allocator) for RISC-V.
This is done a bit differently compared to the ARMV7 implementation:
- Support implemented for Sv39 MMU, however the implementation should be
extensible for other MMU types also.
- Instead of preserving and moving the L1 references around, a canonical
approach is used instead, where the page table base address register
is switched upon context switch.
- To preserve a bit of memory, only a single L1/L2 table is supported,
this gives access to 1GiB of virtual memory for each process, which
should be more than enough.
Some things worth noting:
- Assumes page pool is mapped with vaddr=paddr mappings
- The CONFIG_ARCH_XXXX_VBASE and CONFIG_ARCH_XXXX_NPAGES values are
ignored, with the exception of CONFIG_ARCH_DATA_VBASE which is used
for ARCH_DATA_RESERVE
- ARCH_DATA_RESERVE is placed at the beginning of the userspace task's
address environment
Summary:
- I noticed that maix-bit:smp does not work with QEMU.
- Actually, QEMU supports sifive_u (not K210) but it works
if FPU is disabled.
- This commit fixes this issue.
Impact:
- K210 with QEMU only
Testing:
- Tested with qemu-5.2
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
