This change decouples that upper activity-based logic from the lower random walk logic and allows use of other upper state detection logic (such as a custom, application-specific state machine).
(1) unifies the iomux definitions - previously some pins had them, and some didn't. This effectively made it impossible to use the pinmuxes without editing the header file in the standard distribution tree.
(2) unifies the pin definitions so that every pin now has a suffix. This makes it *much* easier to see when a pin is in use in your code, because it will always have a definition in your board.h file.
For anyone who is already using this CPU, a couple of small changes are needed to existing code;
In respect of (1) add IOMUX decorators to your pin definitions. You will find defaults in haardware/imxrt_iomux.h. Every pin should have a IOMUX decorator and in general the defaults should be OK. So while previously in your board.h file you might have had;
You will now have;
In respect of (2) you will need to add selectors for any function that previously only had one pinning option. There aren't many of those but LPUART1 is a good example. That just means adding into your board.h something like;
net/netlink/netlink_route.c: Add Netlink socket NETLINK_ROUTE support for getting a snopshot of the Neighbor table.
net/neighbor/neighbor_snapshot.c: Add neighbor_snapshot() that will eventually be used by the Netlink sockets. Also fixed naming violation 'struct neighbor_entry' -> 'struct neighbor_entry_s'.
include/nuttx/net/neighbor.h: Expose format of the IPv6 neighbor table for use with Netlink sockets.
STM32H7:Set the BBSRAM memory range to non-cacheable.
* armv7-m:mpu add user peripheral helper
* stm32h7:BBSRAM Exclude BBSRAM from cacheable when CONFIG_ARMV7M_DCACHE
ST placed the STM32H7 BBSRAM in the SRAM default memory region
which is cacheable. This commit sets the BBSRAM memory range
to non-cacheable.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/tiva/common/tiva_flash.c: Fix several mistakes in
tiva_write() but note that this function needs more work. (1) Fix wrong
use of && when & was intended. (2) Add compile- time warning directive
because according to this function's interface, it is supposed to
support unaligned writes and/or writes of arbitrary numbers of bytes to
FLASH. However, this function does NOT support that at this time. This
needs to be fixed. (3) Fix wrong preprocessor conditional. Was written
to use the 32-word write buffer only for TM4C1294NCPDT. This buffer is
available on all TM4C123 and TM4C129 parts. Now conditioned upon
CONFIG_ARCH_CHIP_TM4C123 or CONFIG_ARCH_CHIP_TM4C129. (4) Add comments
to document the intent of the above preprocessor logic.
drivers: modem: altair: auto select SPI
The Altair hardware is connected to SPI and will not work without SPI support
The SPI_EXCHANGE is automaticaly enabled (default y) when SPI is selected.
Since SPI is mandatory it should be auto selected
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
