Commit Graph

1701 Commits

Author SHA1 Message Date
Tiago Medicci Serrano
72acec7275 esp32s3: Fix faulty esp32s3-devkit:stack example
This defconfig is an example of the recorded stack and it became
faulty recently after the implementation of the `up_current_regs`
functions. The `noinstrument_function` directive must be used for
preventing it from being looped when instrumentation is enabled.
Also, this commit places `sched/instrument/stack_record.c` in IRAM.
2024-09-21 10:42:06 +08:00
simbit18
6a0c0722e2 CI: Improvement to speed up compilation and reduce download errors.
The simple improvement is designed to speed up compilation and reduce download errors on github and local.

Added a folder nxtmpdir for storing third-party packages

nuttxworkspace
|
|- nuttx
|- apps
|- nxtmpdir

tools/Unix.mk:
added export NXTMPDIR := $(WSDIR)/nxtmpdir

tools/configure.sh:
added option -S creates the nxtmpdir folder for third-party packages.

tools/Config.mk:
added macro
CLONE - Git clone repository.
CHECK_COMMITSHA - Check if the branch contains the commit SHA-1.

tools/testbuild.sh:
added option -S

For now I added in the folder this package

ESP_HAL_3RDPARTY_URL = https://github.com/espressif/esp-hal-3rdparty.git

ARCH
arch/xtensa/src/esp32/Make.defs
arch/xtensa/src/esp32s2/Make.defs
arch/xtensa/src/esp32s3/Make.defs
arch/risc-v/src/common/espressif/Make.defs
arch/risc-v/src/esp32c3-legacy/Make.defs

but you can also add other packages (maybe also of apps)
2024-09-20 11:26:01 +08:00
Masayuki Ishikawa
df298c186f Revert "build depend:Revert Make.dep intermediate ddc file"
This reverts commit ddc3119c4e.
2024-09-15 19:29:47 +08:00
Kevin Zhou
d6ae4a0342 xtensa/esp32s3: Adjust I2C clock timing 2024-09-15 10:23:19 +08:00
xuxin19
ddc3119c4e build depend:Revert Make.dep intermediate ddc file
Revert "Parallelize depend file generation"
This reverts commit d5b6ec450f.

parallel depend ddc does not significantly speed up compilation,
intermediately generated .ddc files can cause problems if compilation is interrupted unexpectedly

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-09-15 10:01:58 +08:00
hujun5
908df725ad arch: use up_current_regs/up_set_current_regs replace CURRENT_REGS
reason:
1 On different architectures, we can utilize more optimized strategies
  to implement up_current_regs/up_set_current_regs.
eg. use interrupt registersor percpu registers.

code size
before
    text    data     bss     dec     hex filename
 262848   49985   63893  376726   5bf96 nuttx

after
       text    data     bss     dec     hex filename
 262844   49985   63893  376722   5bf92 nuttx

size change -4

Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
   -machine virt,virtualization=on,gic-version=3 \
   -net none -chardev stdio,id=con,mux=on -serial chardev:con \
   -mon chardev=con,mode=readline -kernel ./nuttx

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-13 23:18:58 +08:00
YAMAMOTO Takashi
419da0209f esp32: retire 0001-esp32-Connect-Xtensa-Instruction-RAM1-to-Cache.patch
This file is no longer used.
2024-09-12 21:17:04 +08:00
YAMAMOTO Takashi
64804be879 arch/xtensa/src/esp32/Bootloader.mk: stop applying a local patch
From @tmedicci
https://github.com/apache/nuttx/pull/13311#issuecomment-2343486553
2024-09-12 21:17:04 +08:00
YAMAMOTO Takashi
e02325a0a6 esp32: Port the bootloader patch
currently esp32 protected mode requires a patched bootloader.
it's a bit cumbersome to build the bootloader for that purpose.

this commit attempts to remove the need of the patched bootloader
by applying the changes by ourselves using esp hal.
2024-09-12 21:17:04 +08:00
Tiago Medicci Serrano
f063e47c28 espressif: Update external libraries to fix GPIO interrupt bug
This commit updates the HAL version used by NuttX to fix the bug
reported in https://github.com/apache/nuttx/issues/13303
2024-09-11 09:05:45 +08:00
hujun5
1aab457b4c sched:add parameters to restore_critical_section
reason:
In SMP, when a context switch occurs, restore_critical_section is executed.
To reduce the time taken for context switching, we directly pass the required
parameters to restore_critical_section instead of acquiring them repeatedly.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-10 23:14:09 +08:00
YAMAMOTO Takashi
8b81689f2c Appease a GCC warning
```
common/xtensa_swint.c:442:24: error: passing argument 1 of 'up_dump_register' discards 'volatile' qualifier from pointer target type [-Werror=discarded-qualifiers]
  442 |       up_dump_register(CURRENT_REGS);
      |                        ^~~~~~~~~~~~
```
2024-09-06 21:17:57 +02:00
Filipe Cavalcanti
2af7037fa1 xtensa/esp32s2: add WiFi support on ESP32S2 2024-09-06 09:46:59 +08:00
Filipe Cavalcanti
4915338857 xtensa/esp32s2: fix for timers and watchdog init on startup 2024-09-06 09:46:59 +08:00
Filipe Cavalcanti
2e884cbd11 xtensa/esp32s2: add support for shutdown handlers 2024-09-06 09:46:59 +08:00
hujun5
608b59e401 smp: enable smp_call in all smp arch
reason:
In subsequent implementations, we will replace up_cpu_pause with smp_call.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-06 07:11:38 +09:00
hujun5
198630a809 sched: use this_task replace nxsched_self
reason:
We can reduce a function call to improve performance.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-05 09:33:50 -03:00
fangxinyong
7b05a550dc sched: replace up_cpu_index with this_cpu
Make this_cpu is arch independent and up_cpu_index do that.
In AMP mode, up_cpu_index() may return the index of the physical core.

Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
2024-09-05 12:09:24 +08:00
YAMAMOTO Takashi
fb58ac99fa esp32_psram.c: Remove a seemingly stale comment 2024-09-05 11:49:31 +08:00
Kevin Zhou
fc6bcd6600 xtensa/esp32s3: Add timing delay set interface for QSPI 2024-09-05 11:36:18 +08:00
YAMAMOTO Takashi
3d275bd4a2 psram_cache_init: remove cosmetic differences between PRO/APP
No functional changes are intended.
2024-09-05 09:44:18 +08:00
hujun5
433f159c06 arch: remove unused up_cpu_pausereq waiting
reason:
After the up_cpu_pause call completes, it guarantees that other CPUs have fully stopped.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-05 07:15:54 +09:00
YAMAMOTO Takashi
58d3c53d2e esp32: fix seemingly wrong calculations
DPORT_APP_CACHE_MASK_DRAM1 is already a mask.
2024-09-04 09:15:16 +02:00
YAMAMOTO Takashi
471d411503 esp32: psram_set_cs_timing: sync with esp-idf
I have no idea what this setting is.
I'm just blindly trying to follow whatever esp-idf does.

the esp-idf counterpart:
6e5414b6c4/components/esp_psram/esp32/esp_psram_impl_quad.c (L702-L712)
6e5414b6c4/components/esp_psram/esp32/esp_psram_impl_quad.c (L136-L147)
2024-09-03 19:16:28 -03:00
Filipe Cavalcanti
29ae9d1110 esp32s2: fix SPI flash and file system mounting
Copied spi flash files from risc-v
Removed old spiflash from make.defs
KConfig modifications for common spiflash
Added new spiflash entry to make.defs
S2 Board config update
Modifications working on S2. Need fix on ROM function
Board fixes
Deleted old spiflash files
Fixes for smartfs operation
Set new HAL version
Fixed wrong change on S3
2024-09-03 19:13:46 -03:00
Tiago Medicci Serrano
6df9de8788 esp32: fix initialization with PSRAM + SMP
Cache flush must be done prior to the APP cpu initalization. This,
however, must be true for the case where PSRAM is not available or
not selected. To do that, this commit flushs the cache during the
device initialization.
2024-09-02 10:24:26 -03:00
YAMAMOTO Takashi
c06a742a63 esp32: fix a crash with PSRAM + SMP
this function is called via esp_spiram_init_cache early in the boot.
2024-09-02 10:24:26 -03:00
Tiago Medicci Serrano
c72c66fff8 espressif: Fix deadlock in RT timer caused by critical section
This commit fixes a deadlock in `esp32s3-devkit:sta_softap`
defconfig: `spin_lock_irqsave` was being used to enter a critical
section that calls `nxsem_post`. In this case, it's recommended
to use `[enter|leave]_critical_section` to avoid deadlocks when a
context switch may happen, for instance.
2024-08-30 17:00:51 -03:00
YAMAMOTO Takashi
e8b1876f99 esp32: enable APP_CPU cache earlier
NuttX uses PSRAM, possibly using the APP_CPU cache MMU,
way before starting the APP_CPU in up_cpu_start().
Flushing the cache when launching the APP_CPU can cause
data corruptions on PSRAM.
Eg. mm_heap structures if the PSRAM is added to a heap.
2024-08-31 00:13:42 +08:00
YAMAMOTO Takashi
a722b74de7 esp32: cache_sram_mmu_set: update the correct register bits 2024-08-30 21:46:31 +08:00
Tiago Medicci Serrano
a916de0e14 espressif: Update HAL library reference to include debug assert
During the board bringup, the new HAL reference includes an assert
to check if the critical section flags is being stored as expected.
2024-08-30 21:41:47 +08:00
yangsong8
5a39e83c05 usbdev: extend the usb req len to size_t
Some USB controllers can receive or send multiple data packets then
generate one interrupt. This mechanism can reduce the number of data
copies. Extend req buf to accommodate this.

Signed-off-by: yangsong8 <yangsong8@xiaomi.com>
2024-08-30 01:32:02 +08:00
Windrow14
cc8d453b5a arch/xtensa/src/esp32s3/esp32s3_sdmmc.c: wait for command done event also on error response
Wait for CMDDONE in esp32s3_waitresponse even an error response is received.
Otherwise, the CMDDONE event of this command will disrupt later command.

Signed-off-by: Yinzhe Wu <Yinzhe.Wu@sony.com>
Reviewed-by: Yuezhang Mo <Yuezhang.Mo@sony.com>
Reviewed-by: Jacky Cao <Jacky.Cao@sony.com>
Tested-by: Yinzhe Wu <Yinzhe.Wu@sony.com>
2024-08-26 13:44:57 +08:00
hujun5
1d6a099180 irq: remove restore_critical_section in irq
Only in the non-critical region, nuttx can the respond to the irq and not hold the lock
When returning from the irq, there is no need to check whether the lock needs to be released
we also need keep restore_critical_section in svc call

test:
Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
   -machine virt,virtualization=on,gic-version=3 \
   -net none -chardev stdio,id=con,mux=on -serial chardev:con \
   -mon chardev=con,mode=readline -kernel ./nuttx

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-08-25 21:14:19 +08:00
Petro Karashchenko
d499ac9d58 nuttx: fix multiple 'FAR', 'CODE' and style issues
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-08-25 19:22:15 +08:00
Petro Karashchenko
f40b09cbc9 style: remove redundant spaces
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-08-25 19:22:15 +08:00
Kevin Zhou
bf57047429 xtensa/esp32s3: Separate address and command flag for QSPI DMA transfer 2024-08-24 11:31:35 +08:00
chenrun1
3a6a23d157 xtensa_mpu:Modify the specified Region attributes
Due to the xtensa mpu feature, the size of the Region depends on the Base of the next Region. e.g.
Region[1] = 0x20000000
Region[0] = 0x30000000
Then Region[1] length = Region[0] - Region[1]
So this approach is not suitable to implement the behavior of cleaning
up the Region and such a configuration will result in affecting the very beginning (the higher) Region
Therefore, to address this feature, in this change we return the Region
value and implement the ability to modify the target Region's attributes

Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
2024-08-22 01:58:46 +08:00
chenrun1
8e1a042eef nuttx/atomic.h:Fix missing type declarations at compile time
Summary:
  1.Modify the conditions for entering different include header files
  2.Added pre-definition for _Atomic _Bool when it is missing
  3.Added nuttx for stdatomic implementation. When toolchain does not support atomic, use lib/stdatomic to implement it

Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
2024-08-22 01:44:29 +08:00
Tiago Medicci Serrano
568917bfd2 espressif: Fix MCUboot build on RISC-V and unify linker script
This commit fixes building MCUboot on Espressif's RISC-V SoCs and
unify the associated linker scripts to make improve readability.
2024-08-21 23:28:45 +08:00
Tiago Medicci Serrano
5680e9d5a4 espressif: Update internal libraries reference
Update internal reference to get the most updated Espressif's
libraries. Those libraries are based on branch `release/v5.1` of
the ESP-IDF and include `v5.1.4` version of it.
2024-08-21 23:28:45 +08:00
chenrun1
bb4d710d62 xtensa_cache:Disable clean/flush optimization in case of SMP restriction
In a multicore task scenario, there may be a situation where the task runs on different cores at different time slices (when the task is not bound to a particular core).
When the task calls cache clean/flush(range > cache size), depending on the optimization, clean_all, flush_all are called. however, at this point, there may be dirty data or incomplete data profiles in the cache on the kernel that is running the task, which may result in dirty data being flushed into memory or make the application think that the flushed data should be successfully flushed into memory, leading to unknown consequences.

Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
2024-08-21 03:04:41 +08:00
hujun5
4cb419866f arch: inline up_testset in arm arm64 riscv xtensa
test:
Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
   -machine virt,virtualization=on,gic-version=3 \
   -net none -chardev stdio,id=con,mux=on -serial chardev:con \
   -mon chardev=con,mode=readline -kernel ./nuttx

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-08-21 01:45:10 +08:00
Windrow14
190c8787ff arch/xtensa/src/esp32s3/Kconfig|Make.defs|esp32s3_sdmmc.c,
arch/xtensa/src/esp32s3/hardware/esp32s3_sdmmc.h|esp32s3_soc.h,
boards/xtensa/esp32s3/common/include/esp32s3_board_sdmmc.h,
boards/xtensa/esp32s3/common/src/Make.defs|esp32s3_board_sdmmc.c,
boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c: add SD/mmc driver

Support 1-bit bus width and 4-bit bus width. Support eMMC high speed SDR mode.
Support transfer data with DMA. Support SD clock frequency up to 40MHZ.

Signed-off-by: Yinzhe Wu <Yinzhe.Wu@sony.com>
Reviewed-by: Yuezhang Mo <Yuezhang.Mo@sony.com>
Reviewed-by: Jacky Cao <Jacky.Cao@sony.com>
Tested-by: Yinzhe Wu <Yinzhe.Wu@sony.com>
2024-08-19 19:52:39 +08:00
chenrun1
12318bd947 xtensa_cache:add up_get_cachesize api
Summary:
  Added up_get_dcache_size and up_get_icache_size common APIs

Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
2024-08-19 13:54:53 +08:00
Gao Feng
87ff0ddf6d xtensa/esp32s3: reserve memory for a mutex struct depending on the OS
Enabling CONFIG_PRIORITY_INHERITANCE config causes a build error

Based on Nuttx OS reserve memory for mutex struct.

Pass build based on
 - CONFIG_PRIORITY_INHERITANCE y
 - CONFIG_SEM_PREALLOCHOLDERS 0/8
2024-08-16 15:25:20 +08:00
Gao Feng
ddbbdd7fd3 xtensa/esp32s3: partition name duplicate and free 2024-08-16 15:11:14 +08:00
chenxiaoyi
7ce5241f0e types.h: fix windows build error
Windows Kits\10\Include\10.0.22621.0\ucrt\corecrt.h(605,39): error C2371: 'wint_t': redefinition; different basic types
Windows Kits\10\Include\10.0.22621.0\ucrt\corecrt.h(606,39): error C2371: 'wctype_t': redefinition; different basic types

Co-authored-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
Co-authored-by: xuxin19 <xuxin19@xiaomi.com>
2024-08-14 22:36:57 +08:00
chenwen@espressif.com
cde0de00fe xtensa/esp32s3: Update the rtc code to fix system blocking issue
1. For some reasons, the bootloader will set CPU source to BBPLL and enable it,
      but there are calibration issues, so we need turn off the BBPLL and do calibration again to fix the issue.
   2. Corresponding issue link: 89cc9084ab

Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-08-09 12:49:34 -03:00
nuttxs
2af8a886ab arch/xtensa/esp32: Replace nxsig_usleep() with up_udelay() to
avoid context switching, and the actual time difference caused
by the setting of TICK in nxsig_usleep() is quite large.
2024-08-08 20:01:46 +08:00