Commit Graph

19268 Commits

Author SHA1 Message Date
Huang Qi
eb02528a39 arch/risc-v/qemu-rv: Fix a typo in Make.defs 2022-05-30 19:58:43 +08:00
Huang Qi
571e66d03f arch/risc-v: Remove unused rv32m1_vectors.S
Since it had been merged into rv32m1_head.S

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-05-30 19:58:43 +08:00
wangbowen6
360e319959 arm/tlsr82: ble performance optimize and problems solve.
RF and system timer interrupt are used for ble.

tlsr82_flash.c:
1. BLE will loss packets during flash operation beacause the interrupt
   is disabled and the operation take too long (especially erasing,
   about 100ms), so allow RF and system timer interrupt during flash
   operation;
2. Add sched_lock()/sched_unlock() to avoid the task switch in ble and
   system timer interrupt;

flash_boot_ble.ld:
3. Because of 1, the code executes in RF and system timer interrupt
   must be in ram to avoid bus error. The sem_post() will be called and
   const variable g_tasklisttable will be accessed in RF and system
   timer interrupt handler;
4. To improve the performance, copy some frequently called function to
   ram as well, such as: sem_take(), sched_lock(), sched_unlock(),
   some lib functions, some zephyr ble functions and some tinycrypt
   functions;
5. The RF and system timer interrupt handler will call some libgcc
   functions, so copy all the libgcc functions to ram exclude _divdi3.o,
   _udivdi3.o and _umoddi3.o;

tlsr82_serial.c
6. Make up_putc() be thread safe, add enter/leave_critical_section() in
   function uart_send_byte();

tc32_doirq.c
7. Increase the RF and system timer interrupt response priority;

Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2022-05-30 19:52:38 +08:00
Xiang Xiao
7ec6b4c7dd Change dpends on SCHED_[L|H]PWORK to SCHED_WORKQUEUE
since the code could map the unsupported work to the
supported one and remove select SCHED_WORKQUEUE from
Kconfig since SCHED_[L|H]PWORK already do the selection

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-28 18:41:51 +03:00
klmchp
6bd2d172b0 Fix sama5d2 Kconfig errors and add missing pin definitions
1.Fix sama5d2 Kconfig. 2. Add missing pin definitions of sama5d2-xult board for sam_emacb and sam_lcd drivers.
2022-05-28 14:41:15 +08:00
Xiang Xiao
d05b031d8d arch/sparc: Remove FILE dump code from _up_dumponexit
since the kernel build can't access the userspace memory
inside other process directly

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-26 16:34:56 -03:00
Oki Minabe
f0fb530eaa arch: imx6: add support kernel build and smp
Summary:
- add support BUILD_KERNEL and SMP for imx6
- prepare page tables of cpu1,2,3
- add sabre-6quad:knsh_smp config

Impact:
- imx6

Testing:
- getprime, smp on sabre-6quad:knsh_smp w/ qemu

Signed-off-by: Oki Minabe <minabe.oki@gmail.com>
2022-05-27 01:31:58 +08:00
chao.an
3f65b562bb arch: inline up_interrupt_context()
inline the up_interrupt_context() to avoid unnecessary stack pushes

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-05-26 04:36:07 +08:00
Alan Carvalho de Assis
d4b0fc9eb4 xtensa/esp32s3: Add basic support to SPI
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Co-authored-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-05-25 16:10:29 -03:00
Alexey Matveev
684f2cbbac Fix stm32 pwm HAVE_ADVTIM 2022-05-25 12:16:16 +03:00
Gustavo Henrique Nihei
b4392f7323 xtensa/esp32: Fix leak of semaphores created by Wi-Fi kernel thread
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-05-25 09:46:30 +09:00
Gustavo Henrique Nihei
18d74dbea0 risc-v/esp32c3: Fix leak of semaphores created by Wi-Fi kernel thread
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-05-25 09:46:30 +09:00
Gustavo Henrique Nihei
b2d77c0e9c Revert "risc-v/esp32c3: Use onexit to free thread private semaphore"
This reverts commit f5eaf82c93.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-05-25 09:46:30 +09:00
zhuyanlin
0e478e559f xtensa: coproc: modify coproc_save/restore to macro
As coproc_save/restore only used in context_restore/save.
Use macro instead of function.
Some register use optimize.
Unify with arm/riscv.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-05-24 14:11:58 +09:00
Abdelatif Guettouche
2a8b2cad17 esp32_cpuidlestack.c: Remove unnecessary code.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-05-24 08:59:10 +09:00
zhuyanlin
23d35336ad xtensa:esp32: enable cp processor of app core
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-05-23 22:02:24 +02:00
Petro Karashchenko
7a6253cb89 arch/arm/samv7: Fix PWM operation for single channel mode
The current SAMv7 PWM driver assumes that all PWM channels should
work in sync mode, but that is a partial case of a generic PWM
driver operation.

Start SAMv7 PWM channels in async mode. The sync mode should be
implemeted either using ioctl command or via a separate Kconfig
option.

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-05-24 03:26:13 +08:00
Eero Nurkkala
3ea7d4bab4 risc-v/mpfs: amend OpenSBI to utilize IHC
Linux kernel uses M-mode trap for handling Inter-Hart Communication (IHC).
This patch provides all the required functionalities for this purpose.
Previously, HSS bootloader was required. Now, NuttX is run as the
bootloader providing OpenSBI vendor extensions instead. This setup has
been tested on the following configuration:

 - Hart 0 has NuttX in bootloader mode with OpenSBI
 - Hart 1 unused
 - Hart 2 has NuttX configured at 0xa2000000
 - Hart 3 has U-boot / Linux kernel (at 0x80200000)
 - Hart 4 has U-boot / Linux kernel (at 0x80200000)

Upon startup, NuttX on hart 0 will initialize SD-card driver, loads
the hart 2 NuttX from the SD-card and loads the U-boot to 0x80200000.
Also the nuttx.sbi -binary is loaded from SD-card into address 0x80000000,
which is also marked as reserved area in the Linux kernel device tree (for
the chuck 0x80000000 - 0x80200000).

Hart 2 NuttX waits until Linux kernel (IHC master) is started. After the
initial handshake, RPMsg / virtIO bus along with the IHC may be used for
proper AMP mode.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-05-24 03:25:37 +08:00
Masayuki Ishikawa
84bcb075d7 arch: risc-v: Fix crt0.c if CONFIG_HAVE_CXX is not set
Summary:
- I noticed that rv-virt:knsh64 crashes when it executes the init.
- This commit fixes this issue.

Impact:
- None

Testing:
- Tested with rv-virt:knsh64

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-05-23 21:19:01 +08:00
wangbowen6
200109fd28 arm/tlsr82: optimize the adc driver.
1. Add vbat mode for chip internal voltage sample;
2. Add adc channel config;
3. Using DFIFO2 to get the sample value, follow telink sdk.
4. Add calibration function and config;

Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2022-05-22 23:10:06 +08:00
Ville Juven
621062dc1d MPFS: Implement S-mode head and start function
- Remove S-mode initializations from the M-mode head file, they are not
  required
- Writing mstatus->tvm from S-mode will result in illegal instruction
2022-05-22 15:42:30 +03:00
Karel Kočí
a74c707da6 arch: arm: armv6-m: fix LTO build
This imports changes from armv7-m.
2022-05-21 00:03:03 +08:00
YAMAMOTO Takashi
0b547e2384 esp32: Implement up_textheap_heapmember 2022-05-20 21:16:42 +08:00
YAMAMOTO Takashi
c60bb81387 esp32c3: Implement up_textheap_heapmember 2022-05-20 21:16:42 +08:00
YAMAMOTO Takashi
a9317b1895 cxd56xx: Implement up_textheap_heapmember 2022-05-20 21:16:42 +08:00
Ville Juven
91063e85f0 risc-v/vfork: FPU was not saved correctly
The FPU register saving upon vfork entry was missing.

Also added macro that tells the actual size of an FPU reg, instead
of just having a coefficient for qfpu/no-qfpu.
2022-05-20 15:59:24 +08:00
Ville Juven
1ec70bc704 risc-v/vfork: Save FPU registers
Save the callee saved FPU registers
2022-05-19 09:05:00 -03:00
Ville Juven
ef42b7c31e risc-v/irq: Add ABI name versions of FPU registers 2022-05-19 09:05:00 -03:00
Ville Juven
ec073d91c7 risc-v/vfork: Save correct amount of registers for vfork
The original code does not obey RISC-V calling conventions, looks like
it was copy&pasted from MIPS instead.
2022-05-19 09:05:00 -03:00
Sebastien Lorquet
517f179f8d stm32h7: Adds the ability to choose the HSI divider, which must be indicated in board.h if used. 2022-05-18 11:59:07 -07:00
Ville Juven
12476e1f43 RISC-V: add C++ support to crt0 2022-05-19 01:35:36 +08:00
zhuyanlin
b71a1f77c3 xtensa: add perf counter
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-05-18 19:11:32 +03:00
Gustavo Henrique Nihei
aefe78a884 xtensa: Add missing input operand on sys_call6 inline ASM
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-05-18 15:46:57 +02:00
Xiang Xiao
b30e0a26ef Move "-nostartfiles -nodefaultlibs" from Make.defs to Toolchian.defs
and replace "-nostartfiles -nodefaultlibs" with "-nostdlib"

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-18 08:26:02 -04:00
Ville Juven
d7f7867f76 risc-v/opensbi: Generalize the SBI variable handling in makefile
- Remove most of the ifeq-conditions and replace them with variables.
- Move the -I flag for 3rd party headers to opensbi/Make.defs

This clean-up / generalization makes it much simpler to add a new SBI
implementation, without the need to add a bunch of ifeq / elif conditions
to the makefile.
2022-05-18 08:35:04 -03:00
Gustavo Henrique Nihei
4f31c89963 esp32c3-devkit: Rename linker script to indicate use for Flat mode
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-05-18 11:43:52 +08:00
Gustavo Henrique Nihei
c778f35f08 risc-v/esp32c3: Add support for Protected Mode
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-05-18 11:43:52 +08:00
Eero Nurkkala
817919ebb6 risc-v/mpfs: IHC: allow hart configuration
Let the user pick what runs on the harts. For example, the
default configuration now supports NuttX on hart2 and Linux
kernel on harts 3 and 4. Also fix a few issues in the code.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-05-18 01:34:33 +08:00
Abdelatif Guettouche
06f2c67fc2 xtensa.h: Remove old prototype.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-05-16 23:38:09 +08:00
zhuyanlin
883337c3a0 xtensa:fpu: add up_fpucmp and enable CONFIG_ARCH_FPU macro
For arch with CP_NUM > 0, enable ARCH_FPU

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-05-16 12:30:39 +03:00
Xiang Xiao
5958d3ac62 risc-v: Move "LDFLAGS += -melf32lriscv" from Make.defs to Toolchain.defs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-16 11:17:08 +03:00
Xiang Xiao
d3524d4f8b arch/i2c: Change xxx_i2c_tousecs to xxx_i2c_toticks
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 23:22:01 +03:00
Xiang Xiao
f311228f80 arm/efm32: Fix typo error: CONFIG_EFM32_I2C_DYNTIMEOUT to CONFIG_EFM32_I2C_DYNTIMEO
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 19:18:09 +03:00
Xiang Xiao
1f920e55d3 Move warning option from Make.defs to Toolchain.defs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 15:40:35 +03:00
Xiang Xiao
8b7c5b039d arch: Move -fsanitize=kernel-address to ARCHOPTIMIZATION
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 15:40:35 +03:00
Xiang Xiao
4f090eb7fd arch/sparc: Move toolchain macro from board's Make.defs to Toolchain.defs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 15:40:35 +03:00
Xiang Xiao
51cf7ba05a Remove FAR from arm/risc-v/xtensa/sim/x86
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 13:55:58 +03:00
Xiang Xiao
2976accd9f arch: Remove the extra space before the function prototype
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 13:55:58 +03:00
Xiang Xiao
1fb8c13e5e Replace nxsem_timedwait_uninterruptible with nxsem_tickwait_uninterruptible
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 13:55:58 +03:00
Xiang Xiao
816ce73ab4 Replace nxsem_timedwait with nxsem_tickwait
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 13:55:58 +03:00