14958 Commits

Author	SHA1	Message	Date
raiden00pl	c563d8a993	arch/stm32/stm32_pwm.c: cosmetics	2022-08-27 20:40:06 +08:00
raiden00pl	9a85a0959a	stm32/Kconfig: remove the unnecessary option	2022-08-27 20:40:06 +08:00
yangxuan8282	2d32ebe952	arch/arm/src/stm32f7/stm32_otghost.c: fix syslog formats	2022-08-26 20:46:50 +08:00
Gustavo Henrique Nihei	5ed2ee85c9	arch: Improve documentation for up_fpucmp function ... Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2022-08-26 11:57:06 +08:00
Masayuki Ishikawa	50177dbae1	arch: common: Fix arm_allocateheap.c for BUILD_KERNEL ... Summary: - I noticed that the kernel heap area overlaps the PGPOOL - This commit fixes this issue Impact: - None Testing: - Tested with sabre-6quad:netknsh Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>	2022-08-25 13:38:47 +08:00
Huang Qi	e4e3208180	Replace all strncpy with strlcpy for safety ... Signed-off-by: Huang Qi <huangqi3@xiaomi.com>	2022-08-25 13:38:36 +08:00
Nathan Hartman	1d622b6f79	arch/tiva: Fix typo and minor code formatting	2022-08-24 21:29:18 +02:00
Xiang Xiao	d22e1e1998	compiler.h: Add nosanitize_address macro ... and replace all __attribute__((no_sanitize_address)) with it Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-08-23 17:50:52 +02:00
Xiang Xiao	c44a7cbf88	arch: Add ARCH_COVERAGE_ALL option ... so the user could disable the full image instrumentation, but enable the instrumentation by files or directories. Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-08-23 17:50:52 +02:00
Xiang Xiao	f1355680ca	mm/kasan: Add MM_KASAN_ALL option ... so the user could disable the full image instrumentation, but enable the instrumentation by files or directories. Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-08-23 17:50:52 +02:00
yangxuan8282	8a8c268e6b	arch/arm/src/stm32f7/Kconfig: add STM32F7_SYSCFG	2022-08-22 17:31:49 +08:00
yangxuan8282	78f44e7769	arch/arm/src/stm32f7/stm32_otg.h: fix stm32_otghost_initialize definition	2022-08-22 17:31:38 +08:00
Huang Qi	a06ec54cd0	debug: Introduce portion of UBSan ... without UBSan ``` text data bss dec hex filename 85612 208 142258 228078 37aee nuttx ``` with UBSan: ``` text data bss dec hex filename 194290 98164 208634 501088 7a560 nuttx ``` ```c int main(int argc, FAR char *argv[]) { uint32_t ptr[32]; printf("Hello, World!! %lu\n", ptr[64]); return 0; } ``` Try to run this sample: ``` nsh> hello ubsan_prologue: ================================================================================ ubsan_prologue: UBSAN: array-index-out-of-bounds in hello_main.c:39:37 __ubsan_handle_out_of_bounds: index 64 is out of range for type 'uint32_t [32]' ubsan_epilogue: ================================================================================ Hello, World!! 1070182368 nsh> ``` Signed-off-by: Huang Qi <huangqi3@xiaomi.com>	2022-08-22 13:57:29 +08:00
Masanari Iida	bd584332a4	rp2040: Add missing comma in rp2040_i2c_slave.c ... This patch fixes missing comma, found by cppcheck. rp2040_i2c_slave.c:259:0: error: failed to expand 'modbits_reg32', Wrong number of parameters for macro 'modbits_reg32'. Signed-off-by: Masanari Iida <standby24x7@gmail.com>	2022-08-20 16:37:32 +08:00
yangxuan8282	df6e3d1349	arch/arm/src/stm32f7/stm32_otghost.c: fix undeclared ret	2022-08-19 21:02:02 +08:00
Cis van Mierlo	2c42b93962	S32K1xx: Fixed PM bug for clockconfig	2022-08-19 06:01:30 -07:00
Daniel P. Carvalho	7518beee2e	STM32L4 ADC: Change the way that hardware trigger configuration word for regular and injected channels are done.	2022-08-18 11:26:25 -03:00
Michał Łyszczek	4e967c67b4	stm32wl5: fix unbuffered mode and other possible bugs ... This patch fixes unbuffered mode so it actually works. Also, patch contains fixes for possible bugs that could result in deadlock or system hang in certain situations. Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>	2022-08-18 11:46:38 +08:00
Michał Łyszczek	cc08ae67cb	stm32wl5_pwr: add support to boot second CPU (cortex-m0) ... Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>	2022-08-18 11:46:38 +08:00
curuvar	74f1bfbfd7	Added support for Raspberry Pi Pico W	2022-08-17 19:03:19 -03:00
raiden00pl	6d1646625a	arch/arm/src/stm32f7: port FOC driver from arch/stm32	2022-08-15 13:39:08 +02:00
Xiang Xiao	2b37909c9e	libc: Move crc8.h, crc16.h and crc32.h from include to include/nuttx ... to avoid the conflict with the 3rd party library Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-08-13 13:28:24 +03:00
Masayuki Ishikawa	690c178e4b	arch: imx6: Apply the imxrt_enet.c changes to imx_enet.c (4/4) ... Summary: - This commit applies the following imxrt_enet.c changes to imx_enet.c commit 0628019c2c Author: David Sidrane <David.Sidrane@NscDg.com> Date: Wed Jul 13 11:01:49 2022 -0700 imxrt:Enet ensure proper dcache for Writeback mode Impact: - imx_enet.c Testing: - Tested with qemu-6.2 Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>	2022-08-12 10:30:48 -04:00
Masayuki Ishikawa	fb8562763a	arch: imx6: Apply the imxrt_enet.c changes to imx_enet.c (3/4) ... Summary: - This commit applies the following imxrt_enet.c changes to imx_enet.c commit 522a949ed5 Author: David Sidrane <David.Sidrane@NscDg.com> Date: Wed Jul 13 11:00:11 2022 -0700 imxrt:enet Better interrupt state handeling - NOTE: I also fixed typo and compile error in the above commit Impact: - imx_enet.c Testing: - Tested with qemu-6.2 Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>	2022-08-12 10:30:48 -04:00
Masayuki Ishikawa	6dfd01885d	arch: imx6: Apply the imxrt_enet.c changes to imx_enet.c (2/4) ... Summary: - This commit applies the following imxrt_enet.c changes to imx_enet.c commit 81f03a9151 Author: David Sidrane <David.Sidrane@NscDg.com> Date: Tue Mar 15 14:27:51 2022 -0700 imxrt:ETH Add Support for ETH2 Impact: - imx_enet.c Testing: - Tested with qemu-6.2 Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>	2022-08-12 10:30:48 -04:00
Masayuki Ishikawa	4e4ebba306	arch: imx6: Apply the imxrt_enet.c changes to imx_enet.c (1/4) ... Summary: - This commit applies the following imxrt_enet.c changes to imx_enet.c commit 12a515ebb6 Author: Masayuki Ishikawa <masayuki.ishikawa@gmail.com> Date: Thu Feb 4 11:27:09 2021 +0900 arch: imxrt: Introduce CONFIG_NET_GUARDSIZE to imxrt_enet.c Impact: - imx_enet.c Testing: - Tested with qemu-6.2 (defconfig will be updated later) Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>	2022-08-12 10:30:48 -04:00
Petro Karashchenko	27fe5a50c6	arch/arm/stm32f7: fix cache invalidation issue in Ethernet RX ... Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-08-11 03:40:25 -04:00
Petro Karashchenko	4cd7e33b8d	arch/arm/samv7: fix compilation warnings ... Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-08-11 10:00:39 +08:00
Petro Karashchenko	49d26e1b50	arch/arm/samv7: get TX DMA running for HSMCI interface ... Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-08-11 10:00:39 +08:00
David Sidrane	32c4bdb7a6	s32k1xx:LPI2C Add DMA support	2022-08-10 11:22:38 +08:00
raiden00pl	08b8234e9e	arch/arm/src/stm32f7: port ADC driver from arch/stm32 ... This change adds support for the following features: - injected channels (default: 0) - ADC resolution (default: 12bit) - ADC low-level operations - ADC external triggers - custom ADC interrupts - ADC sample time configuration - configurable ADC SCAN mode (default on if DMA) - configurable ADC DMA mode (default: one shot mode) - reset the ADC block only if all ADC instances are closed	2022-08-10 02:03:51 +08:00
David Sidrane	4ee917c14c	stm32f7:Serial Fix breakage from #6779	2022-08-09 20:18:23 +03:00
Jiuzhu Dong	fe17f747a7	fs/directory: move private directory information to filesystem ... Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>	2022-08-09 23:30:01 +08:00
Jiuzhu Dong	90db4daca9	fs/directory: update readdir interface for all filesystem ... Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>	2022-08-09 23:30:01 +08:00
David Sidrane	2e7b594bf4	s32k1xx:Add s32k146 DMAMUX	2022-08-09 16:29:21 +03:00
David Sidrane	3813320c31	s32k1xx_edma:Add Looping and cleanup ... s32k1xx:EDMA Use aligned_data macros s32k1xx:EDMA CONFIG_ARCH_CHIP_S32K14x->CONFIG_ARCH_CHIP_S32K14X s32k1xx:EDMA remove FAR keyword s32k1xx:EDMA Fix C&P error from Kinetis s32k1xx:EDMA TCD Alignment of 32 Bytes to support Scatter/Gather s32k1xx:EDMA Fix access violation s32k1xx:dmamux fixed missing closing paren	2022-08-09 16:29:21 +03:00
raiden00pl	a05db5299e	arch/arm/src/stm32f7: port PWM driver from arch/stm32 ... This change adds support for the following features: 1. PWM complementary outputs 2. interface for low-level PWM operations 3. support for all PWM channel modes 4. support for internal PWM channels (TIM1/TIM8) 5. support for PWM channel polarity and IDLE state 6. support for TRGO and BREAK	2022-08-09 12:37:49 +08:00
raiden00pl	fd02855c63	arch/stm32f7: rename PWM complementary output pins from CHxN to CHxNOUT (always output)	2022-08-09 12:37:49 +08:00
David Sidrane	050ce3e0d3	kinetis:spi remove ttype & do cache ops	2022-08-09 10:46:31 +08:00
David Sidrane	22580584d2	kinetis:[lp]serial remove ttype & do cache ops	2022-08-09 10:46:31 +08:00
David Sidrane	7a7a01153b	Kinetis:edma Cleanup ... Kientis:edma Cleanup Kinetis:EDMA Interrupt on last TCD Kintis:edma remove dcache operations on passed data Data can be chained in TCD and both read and write can be in the chain. So the dmach ttype is not relevent for all; the TCDs. Therefor we only perform dcache operations on internal strutures, The caller must perform dcache operations on their data. kinetis:EDMA TCD Alignment of 32 Bytes to support Scatter/Gather	2022-08-09 10:46:31 +08:00
Nathan Hartman	dd718e78f7	Fix typos	2022-08-07 23:33:19 +08:00
p-eaglelaw	631ae0032e	fix warning	2022-08-07 13:03:39 +08:00
p-eaglelaw	702e2f3680	remove unused lib,fix according review comments	2022-08-07 01:57:02 +08:00
David Sidrane	55aaba53fc	imxrt:SPI add DMA support	2022-08-06 15:32:07 +08:00
David Sidrane	fa58381e58	imxrt:serial add TX & RX DMA support ... imxrt:serial ioctl should call to proper setup	2022-08-06 15:32:07 +08:00
David Sidrane	85ec2e1446	imxrt:Add LPI2C DMA	2022-08-06 15:32:07 +08:00
David Sidrane	f34acdb936	imxrt:lpi2c add parens for macros expansions	2022-08-06 15:32:07 +08:00
Peter van der Perk	22d41f6b9c	LPC17xx_40xx PWM multichannel support ... USB no softconnect SocketCAN kconfig fixes	2022-08-06 15:31:38 +08:00
David Sidrane	6ab76bfc7c	imrt105x:ENET Match Data sheet Naming	2022-08-06 15:31:23 +08:00
David Sidrane	b9a6b01e6c	imrt102x:ENET Match Data sheet Naming	2022-08-06 15:31:23 +08:00
David Sidrane	0628019c2c	imxrt:Enet ensure proper dcache for Writeback mode ... Use aligned_data added proper handeling for Writeback	2022-08-06 15:31:23 +08:00
David Sidrane	522a949ed5	imxrt:enet Better interrupt state handeling	2022-08-06 15:31:23 +08:00
David Sidrane	1d88f8df37	imxrt:pinmux ENET2 correct ALT for GPIO_ENET2_REF_CLK2	2022-08-06 15:31:23 +08:00
David Sidrane	bced1a3cb4	imxrt:Fix Ethernet Clocking	2022-08-06 15:31:23 +08:00
David Sidrane	6a2c1fb1de	imxrt:Kconfig add IMXRT_PHY_POLLING	2022-08-06 15:31:23 +08:00
David Sidrane	81f03a9151	imxrt:ETH Add Support for ETH2	2022-08-06 15:31:23 +08:00
David Sidrane	49d304257c	imxrt:All boards ARCH_PHY_INTERRUPT is a board property	2022-08-06 15:31:23 +08:00
David Sidrane	3af910f8b6	imxrt:Ethernet Add LAN8742A support	2022-08-06 15:31:23 +08:00
Petro Karashchenko	b3cd9090d1	drivers/net: make sure that net driver d_buf is 16-bit aligned ... Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-08-05 22:21:37 +08:00
raiden00pl	93584f8668	arch/stm32f0l0g0: add SPI3 support (STM32G0B0 chips)	2022-08-05 13:57:56 +08:00
David Sidrane	33efeeeafd	imxrt:EDMA add loop support ... imxrt:edma imxrt_dmach_{xfrsetup|getcount} DMACH_HANDLE *->DMACH_HANDLE imxrt:EDMA TCD Alignment of 32 Bytes to support Scatter/Gather	2022-08-05 09:44:36 +08:00
David Sidrane	1421bc58db	imxrt:Correct register usage in up_rtc_settime	2022-08-05 09:43:36 +08:00
David Sidrane	5e902861d9	imxrt:usdhc fix error when CONFIG_ARMV7M_DCACHE is off	2022-08-05 09:43:36 +08:00
David Sidrane	b9c6284750	imxrt:lowputc add extern "C"	2022-08-05 09:43:36 +08:00
Nathan Hartman	20bdd44e7b	Remove executable permission from source and build files.	2022-08-04 12:48:18 -03:00
Xiang Xiao	8582a12388	drivers: Reorganize the power related code layout ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-08-04 10:28:28 +03:00
Masayuki Ishikawa	8e7752c7da	arch: common: Fix up_check_tcbstack() for CONFIG_ARCH_ADDRENV=y ... Summary: - I noticed that ps shows incorrect stack usage when running getprime in the background. - With CONFIG_ARCH_ADDRENV=y, a user task including pthread allocates its stack in the user space that needs to be accessed with a correct address environment. - This commit fixes this issue. Impact: - CONFIG_ARCH_ADDRENV=y only Testing: - Tested with sabre-6quad:knsh on qemu-6.2 Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>	2022-08-04 11:13:16 +08:00
raiden00pl	981ad9fc1e	arch/stm32xx/Kconfig: simplify PWM options and unify them among stm32 chips	2022-08-03 23:43:19 +08:00
raiden00pl	935f110438	arch/stm32f7/stm32_tim.c: include the missing RCC header	2022-08-03 23:42:52 +08:00
raiden00pl	47dbad0a8b	arch/stm32/stm32_foc.c: fix some ADC and PWM ifdefs	2022-08-03 23:42:37 +08:00
Peter van der Perk	a6da6dcec6	LPC17_40 CAN driver SocketCAN support	2022-08-03 17:58:57 +08:00
chao.an	d501e01eef	arm/backtrace: use sp unwind if FRAME_POINTER is enabled on thumb mode ... GCC toolchain Bug 92172 - ARM Thumb2 frame pointers inconsistent with clang https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92172 Signed-off-by: chao.an <anchao@xiaomi.com>	2022-08-03 17:58:36 +08:00
Daniel P. Carvalho	40e6c8dca4	STM32L4 DAC: Added basic support for low level operations	2022-08-02 10:43:59 +08:00
Jari van Ewijk	a554b9ce89	NXP S32K1XX: fix LPI2C reset	2022-08-01 07:34:03 -04:00
Xiang Xiao	c26bb35843	Remove the private NULL, TRUE and FALSE macros ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-07-31 22:12:57 +03:00
Sergey Nikitenko	ec59125ad3	stm32wb/mbox: fixing ACL transmit buffer	2022-07-31 10:29:29 +08:00
Sergey Nikitenko	30a80a390d	stm32wb/ble: disable default CPU2 host config option	2022-07-31 10:29:29 +08:00
Sergey Nikitenko	9db4caca1d	stm32wb/nimble: workaround for unsupported HCI command	2022-07-31 10:29:29 +08:00
Sergey Nikitenko	cf594b2c81	stm32wb/mbox: renaming msg_buf->cmd_buf	2022-07-30 11:45:15 +08:00
Sergey Nikitenko	49af13c507	stm32wb/mbox: fixing txbuf queue	2022-07-30 11:45:15 +08:00
Michał Łyszczek	e887a4a5b7	stm32wl5: add lower half driver for IPCC ... Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>	2022-07-29 23:11:32 +08:00
chao.an	0d28168679	arm/allocateheap: fix multiple definition of 'up_allocate_heap' ... ld: arch/libarch.a(cxd56_allocateheap.c.obj): in function `up_allocate_heap': arch/arm/src/cxd56xx/cxd56_allocateheap.c:113: multiple definition of `up_allocate_heap'; arch/libarch.a(arm_allocateheap.c.obj): arch/arm/src/common/arm_allocateheap.c:110: first defined here Signed-off-by: chao.an <anchao@xiaomi.com>	2022-07-29 11:57:10 +03:00
chao.an	93f719bccb	arm/hostfs: fix build warning ... arch/arm/src/common/arm_hostfs.c: In function 'host_read': arch/arm/src/common/arm_hostfs.c:156:24: warning: passing argument 1 of 'up_invalidate_dcache' makes integer from pointer without a cast [-Wint-conversion] 156 | up_invalidate_dcache(buf, buf + count); | ^~~ | | | void * In file included from arch/arm/src/common/arm_hostfs.c:26: include/nuttx/cache.h:261:37: note: expected 'uintptr_t' {aka 'unsigned int'} but argument is of type 'void *' 261 | void up_invalidate_dcache(uintptr_t start, uintptr_t end); | ~~~~~~~~~~^~~~~ Signed-off-by: chao.an <anchao@xiaomi.com>	2022-07-29 08:52:59 +03:00
zhuyanlin	031c89db89	power: add PM_IDLE_DOMAIN to pm.h and remove definations ... Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2022-07-29 11:15:40 +08:00
Xiang Xiao	13a7ae3d06	arch: Call board_reset before up_irq_save and spin_trylock ... since board_reset may call some kernel functions which try to acquire the lock again Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-07-28 08:18:24 -04:00
raiden00pl	cce7b7ada6	stm32f7: add showprogress in __start	2022-07-28 20:07:31 +08:00
Sergey Nikitenko	82ad4b0e08	stm32wb: adding BLE support	2022-07-28 15:23:34 +08:00
Sergey Nikitenko	9db6aaa5c7	stm32wb: fixing IPCC 'putreg' calls	2022-07-28 15:23:34 +08:00
Jiuzhu Dong	9d4549d48b	arch: limit output maximum size stackdump when sp is not within stack ... Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>	2022-07-27 20:48:33 +08:00
Jiuzhu Dong	136b1d6d42	arch: using remain to ignore invalid stack content when sp is not within stack ... Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>	2022-07-27 20:48:33 +08:00
Jiuzhu Dong	5c8fd46126	arch/stack: rename do_stack_check with arch prefix ... Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>	2022-07-27 20:48:33 +08:00
Jiuzhu Dong	79597d0caf	arch/up_stack_check: using running_task to get correct task context ... Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>	2022-07-27 20:48:33 +08:00
Peter van der Perk	9e7e45df76	Evaluate n in preprocessor before masking	2022-07-25 23:47:05 +08:00
Peter van der Perk	ec118743ea	NX style fixes	2022-07-25 23:47:05 +08:00
Peter van der Perk	eae3f77673	Fix wrong comment style	2022-07-25 23:47:05 +08:00
Peter van der Perk	b3590f00b3	NXStyle and preprocessor fixes ... Co-authored-by: Jari van Ewijk <jari.vanewijk@nxp.com>	2022-07-25 23:47:05 +08:00
Jari van Ewijk	dd1096695d	Add initial support for NXP S32K3 MCU family ... Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>	2022-07-25 23:47:05 +08:00
raiden00pl	8eae3bb5ff	stm32f0l0g0/stm32_spi.c: fix receiving data for half duplex mode	2022-07-25 23:46:33 +08:00
raiden00pl	351c9dc837	stm32f0l0g0/stm32_spi.c: remove unused spi_readbyte function	2022-07-25 23:46:33 +08:00
raiden00pl	af4d65416a	stm32f0l0g0/stm32_spi.c: add missing SPI mode config and fix ifdef	2022-07-25 23:46:33 +08:00
raiden00pl	69986fad84	stm32f0l0g0/hardware/stm32_spi.h: remove unused definitions	2022-07-25 23:46:33 +08:00
raiden00pl	92b676479a	stm32l4/Kconfig: add support for STM32L476JG and STM32L476JE	2022-07-23 16:51:31 -03:00
curuvar	c21c7ac8dc	Added Adafruit QT Py RP2040 board. ... Added ability to configure indivdual UART, SPI and I2C pin location.	2022-07-23 18:25:38 +08:00
curuvar	421b8ae3e7	Ability to use newer pico-sdk with RP2040 builds (Issue #4919)	2022-07-23 14:36:52 +08:00
Fotis Panagiotopoulos	30f8d33bca	Fixed path calculation in BBS RAM.	2022-07-22 10:59:57 +08:00
ligd	df365008b2	arm_secure_irq: fix NVIC_IRQ_DBGMONITOR un-secure set failed ... NVIC_DEMCR.SDME is a read-only bit Signed-off-by: ligd <liguiding1@xiaomi.com>	2022-07-22 01:48:55 +03:00
Petro Karashchenko	2291f601ee	arch/arm/samv7: fix SPI 16-bit transactions in DMA mode ... Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-07-21 23:26:20 +08:00
Xiang Xiao	2166c98809	Add printflike and scanflike to all printf/scanf like functions ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-07-18 14:14:36 +03:00
Xiang Xiao	aad5fbd2fb	arch: Add up_nputs function to handle the non '\0' string correctly ... and change up_puts as a simple macro Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-07-17 17:31:19 +03:00
Michal Lenc	4484d04a8d	samv7: add RX DMA support to serial driver ... This commit adds RX DMA support to serial driver. The DMA is currently supported only for USART peripherals, not for UART. It uses two circular buffers which size can be setup by SAMV7_SERIAL_RXDMA_BUFFER option. The idle bus interrupt is enabled to ensures data are read even if the buffer is not yet full. The timeout can be setup by SAMV7_SERIAL_DMA_TIMEOUT option. This adds support only for RX transfers. Signed-off-by: Michal Lenc <michallenc@seznam.cz>	2022-07-16 15:39:20 +03:00
Michal Lenc	e3e282bd8a	samv7: add DMA API for circular buffers ... This commit adds functions sam_dmarxsetup_circular() and sam_dmarxstart_circular() that create API for operating with two or more circular buffers. This can be used for DMA operation with serial driver or ADC where ping pong buffers are required to successfully transfer the data at high speed. Signed-off-by: Michal Lenc <michallenc@seznam.cz>	2022-07-16 15:39:20 +03:00
Michal Lenc	89a2b51b96	samv7: add RS-485 mode support to USART driver ... This commit enhances SAMV7 serial driver with RS-485 mode available to USART peripherals. The hardware automatically sets RTS pin high when data are transfered and low then no transfer occurs. Only USART peripherals support this mode, UART peripherals do not. This mode can be enabled by configuration option SAMV7_USARTx_RS485MODE. Signed-off-by: Michal Lenc <michallenc@seznam.cz>	2022-07-16 15:39:20 +03:00
raiden00pl	8e5e6ab8cb	stm32/Kconfig: stm32_i2s needs SPI_DMA enabled	2022-07-16 11:10:01 +03:00
raiden00pl	a8e7f7742c	stm32f0l0g0/Kconfig: set default n for hidden options	2022-07-16 11:10:01 +03:00
raiden00pl	d307e5a7f5	stm32f0l0g0/Kconfig: hide STM32F0L0G0_SPI_DMA option and select it automatically	2022-07-16 11:10:01 +03:00
raiden00pl	1b45982521	stm32f0l0g0/Kconfig: remove the duplicated SPI DMA section	2022-07-16 11:10:01 +03:00
raiden00pl	e39afbf277	stm32/Kconfig: set default n for hidden options	2022-07-16 11:10:01 +03:00
raiden00pl	12273d0aa9	stm32/Kconfig: hide STM32_SPI_DMA option and select it automatically	2022-07-16 11:10:01 +03:00
raiden00pl	1616edbb81	stm32f7/Kconfig: hide STM32F7_SPI_DMA option and select it automatically	2022-07-16 11:10:01 +03:00
raiden00pl	6aef19617b	stm32h7/Kconfig: hide STM32H7_SPI_DMA option and select it automatically	2022-07-16 11:10:01 +03:00
raiden00pl	cb94579ab7	stm32wl5/Kconfig: hide STM32WL5_SPI_DMA option and select it automatically	2022-07-16 11:10:01 +03:00
raiden00pl	3c0a3dabfc	stm32f0l0g0/SPI: add support for half duplex, simplex rx and simplex tx modes	2022-07-16 02:00:53 +08:00
curuvar	d69d9eb0c9	Added I2C Slave to RP2040 ... Added length to I2C slave callback.	2022-07-16 01:56:52 +08:00
raiden00pl	2428438037	stm32f0l0g0/SPI: fix compilation for DMA enabled	2022-07-15 11:38:36 -03:00
raiden00pl	c7e6366e91	stm32f0l0g0/SPI: enable SPI for STM32G0	2022-07-15 11:38:36 -03:00
raiden00pl	f702c89c33	stm32f0l0g0/SPI: configure DMA support individually for each SPI	2022-07-15 11:38:36 -03:00
raiden00pl	056e11a3e5	stm32f0l0g0/SPI: only SPI1 and SPI2 are present in STM32 M0 devices	2022-07-15 11:38:36 -03:00
raiden00pl	47e29d9402	stm32f0l0g0: remove references to non-existent ADCs, only ADC1 present on STM32 M0/M0+ devices	2022-07-15 11:36:43 -03:00
Gustavo Henrique Nihei	e24621d545	arch: Convert DEBUGASSERT(false) into more intuitive DEBUGPANIC() ... Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2022-07-14 12:08:45 +08:00
Petro Karashchenko	24abf9d5d9	arch/arm/samv7: EMAC bugfixes ... 1. Fix error recovery mechanism during transmission error handling (enable transmission at the end). 2. Fix compilation / operation with CONFIG_SAMV7_EMAC_PREALLOCATE=y 3. Enable fully configured address space for transmission queues to allow sending packets with length more than 976 bytes. With partially configured address space the AHB error is generated during transmission of long packets. Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-07-12 18:34:37 +08:00
raiden00pl	5c1c18af03	stm32g0: add support for USART3 and USART4	2022-07-10 21:02:23 -03:00
raiden00pl	b179c46178	arch/stm32f0l0g0: add support for stm32l053	2022-07-09 23:37:33 +08:00
Nathan Hartman	849f760b77	Fix various typos	2022-07-08 02:15:54 +08:00
Xiang Xiao	3daa18b661	arch: Remove the unnecessary #if/#endif in assert ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-07-07 19:25:47 +03:00
Xiang Xiao	9ff0971d3f	arch: Correct the order of stack related information in assert ... forget to update in this patch: commit b02db04e00 Author: Xiang Xiao <xiaoxiang@xiaomi.com> Date: Sun Jun 5 17:10:19 2022 +0800 arch/assert: Keep the thread dump column order same as ps Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-07-07 19:25:47 +03:00
curuvar	aa6ec6518c	Added ADC to RP2040	2022-07-07 12:45:28 -03:00
Huang Qi	a4e867b8d4	arch/arm/Kconfig: Add description for ARM_THUMB to make it configurable ... Signed-off-by: Huang Qi <huangqi3@xiaomi.com>	2022-07-05 19:34:18 +08:00
Xiang Xiao	fcc48c2254	arch/arm: Don't include arch/arch.h in include/irq.h ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-07-04 13:25:56 +03:00
Xiang Xiao	3d1ce144df	arch: Move up_getsp from arch.h to irq.h ... since all other special register operation in irq.h Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-07-01 10:44:55 -03:00
curuvar	0c3db448bb	Added Adafruit Feather RP2040, Adafruit KB2040 and Added neopixel driver to support RP2040	2022-06-30 22:13:49 -07:00
Sergey Nikitenko	4285274c31	New stm32wb chip family	2022-07-01 12:13:58 +08:00
Nathan Hartman	a3688b0c3b	tiva: Add UART CTS/RTS support ... * arch/arm/src/tiva/common/tiva_lowputc.c (tiva_lowsetup): For each UART, if Kconfig enables RTS/CTS (e.g., CONFIG_UART0_IFLOWCONTROL and/or CONFIG_UART0_OFLOWCONTROL), configure the corresponding GPIO(s). * arch/arm/src/tiva/common/tiva_serial.c: (struct up_dev_s): If CONFIG_SERIAL_IFLOWCONTROL, add a bool field 'iflow'. If CONFIG_SERIAL_OFLOWCONTROL, add a bool field 'oflow'. This is inspired by the implementation for kinetis. (g_uart0priv, g_uart1priv, g_uart2priv, g_uart3priv, g_uart4priv, g_uart5priv, g_uart6priv, g_uart7priv): If Kconfig enables RTS/CTS for a UART (e.g., CONFIG_UART0_IFLOWCONTROL thru CONFIG_UART7_OFLOWCONTROL), set the corresponding iflow and/or oflow flag(s). (up_setup): Check the above-mentioned iflow and oflow flags and set or unset the RTSEN and/or CTSEN bits in the UART's CTL register to enable the feature.	2022-07-01 11:52:02 +08:00
Gustavo Henrique Nihei	5ce77fad1b	arch: Remove "0x" prefix preceding "%p" specifier on format string ... The "p" format specifier already prepends the pointer address with "0x" when printing. Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2022-06-30 22:08:58 +03:00
Huang Qi	bc8cf2c501	arch/arm/armv7-m: Fix error link argument for compiler-rt ... Fix: ``` ld.lld: error: unknown argument '-/home/huang/Work/vwear/prebuilts/clang/linux/arm/bin/../lib/clang-runtimes/armv7em_hard_fpv4_sp_d16/lib/libclang_rt.builtins-armv7em.a' ``` Signed-off-by: Huang Qi <huangqi3@xiaomi.com>	2022-06-28 12:38:36 +03:00
dependabot[bot]	4f8c8815d6	Spi driver for Stm32wl55 ... IRQ and DMA mode is not implemented	2022-06-28 10:38:03 +08:00
zouboan	fd8eaf4f42	arch/stm32_capture_lowerhalf.c: add lower half support of capture	2022-06-28 10:35:43 +08:00
Nimish Telang	4afd25b567	this flag is meaningless for the linker	2022-06-27 20:03:03 -03:00
zouboan	78535d0123	arch/stm32_capture: completion other slave mode selection	2022-06-25 14:35:17 +08:00
zouboan	20cd657a65	arch/stm32_capture: fix offset address of slave mode control register	2022-06-25 14:35:17 +08:00
Satoshi Togawa	667afb3b91	sama5: add config SAMA5_SYSTEMRESET in arch/arm/src/Kconfig ... SAMA5D2 and SAMA5D4 does not support external reset. Some SAMA5 board's Kconfig contain item SAMA5_SYSTEMRESET, but it is better in arch/arm/src/Kconfig.	2022-06-25 12:03:15 +08:00
curuvar	412539e66c	Added PWM support to rp2040	2022-06-23 10:17:40 -03:00
curuvar	75facdee72	Added PWM support for rp2040	2022-06-23 10:17:40 -03:00
Simon Filgis	cd1f90c25b	Fix can buffer calculaiton. Add two words to every msg buffer	2022-06-23 00:07:42 +08:00
Alan Carvalho de Assis	19fd0a5587	stm32xx: Fix RTC drift when using HSE ... When using HSE to clock RTC NuttX internal time is gaining 5.5 second per minute. Problem was NuttX using 7182 for one of the RTC division factors, it should have been 7812. The incorrect factors used are 7182 and 0xff. These are used in 3-4 places within Nuttx and other places as 7812 and 0xff. However, the STMicro app note AN4759 suggests using 7999 and 124, which is what I've used. Explanation: These 2 factors are used to divide the HSE clock (which at this point is 1 MHz) to 1 Hz for the RTC hardware. To test the 2 factors, add 1 to both numbers and multiply them together. The result needs to be as close as possible to 1 MHz. The suggested values of 7999 and 124 => 8000*125 = 1,000,000, the prime factors. So, the best fix for Nuttx would be these values. Issue discovered and fixed by Peter Moody	2022-06-21 17:58:10 +03:00
Satoshi Togawa	9f4691603f	sama5: Fix wrong comments.	2022-06-16 17:04:37 +03:00
chao.an	7790839eb0	arch/backtrace: correct the skip counter ... Signed-off-by: chao.an <anchao@xiaomi.com>	2022-06-16 21:09:14 +09:00
Michał Łyszczek	5490f8964f	stm32wl5: add support for internal FLASH ... This patch adds corrected implementation of FLASH memory to be used with progmem driver for use with mtd filesystems like nxffs or smartfs. Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>	2022-06-15 20:29:17 +08:00
Masayuki Ishikawa	cf91b403c9	arch: imx6: Enable imx_idle.c to reduce CPU load ... Summary: - I noticed that QEMU shows a high CPU load. - This commit re-adds imx_idle.c to avoid this issue. Impact: - None Testing: - Tested with sabre-6quad:smp with QEMU Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>	2022-06-14 09:18:44 +03:00
wangbowen6	9985e0a43e	arm/tlsr82: bugfix, tlsr82_flash_ioctl() return wrong value. ... Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>	2022-06-14 01:15:08 +08:00
Michał Łyszczek	288b57d5ca	stm32wl5: add EXTI support for GPIO ... This patch implements working support for EXTI GPIO. Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl> -- v1 -> v2: Suggested by: Petro Karashchenko - change (1 << n) to (1 << (n)) in macro definition - change 1 << X to (1 << X) in code - fix alignment v2 -> v3: Suggested by: Petro Karashchenko - I was supposed to change (1 << pin) to 1 << pin, not the other way around:)	2022-06-13 20:21:20 +08:00
Norman Rasmussen	e6376c72d7	Fix CONFIG_ALLSYMS for arm, risc-v and xtensa after #5496	2022-06-13 11:39:06 +08:00
zouboan	26a348a460	arch/arm: fix a typo in Toolchain.defs	2022-06-11 20:03:45 +08:00
Xiang Xiao	f1236da21c	fs: Make the binary(no process) mode as the default ... POSIX require file system shouldn't enable the \r and \n conversion by default Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-06-07 20:22:26 +03:00
Xiang Xiao	28b25e0391	arch: dump "<noname>" as the task name if CONFIG_TASK_NAME_SIZE equals 0 ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-06-07 20:17:23 +03:00
Xiang Xiao	2b2830c252	arch/assert: Replace twice strlcpy with single snprintf ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-06-07 20:17:23 +03:00
Xiang Xiao	b02db04e00	arch/assert: Keep the thread dump column order same as ps ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-06-07 20:17:23 +03:00
Xiang Xiao	c52a19c8dc	arch: Include nuttx/tls.h in *_assert.c ... to avoid error: "invalid use of undefined type 'struct task_info_s' Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-06-07 20:17:23 +03:00
ligd	118fd3902c	dump_task: also dump thread param when dump thread name ... Signed-off-by: ligd <liguiding1@xiaomi.com>	2022-06-07 20:17:23 +03:00
Michał Łyszczek	e54fe68bbf	stm32wl5: add new chip family ... This patch adds new chip family, stm32wl5x. This is bare minimum implementation of said chip. I've tested this by running nsh. There are only two chips in this family, stm32wl55 and stm32wl54. The only difference between them is that stm32wl55 has LORA. stm32wl5 is dual CPU (not core!). Right now only CPU1 is implemented. CPU0 has access to radio hardware (while CPU1 does not). Chip is designed so that CPU0 handles radio traffic while CPU1 does the heavy lifting with data - there is communication pipe between two CPUs. I plan to use nuttx on CPU1 and LORA from stm32cube on CPU0 so I don't have implementing CPU0 right now - once we have working LORA in nuttx this may change. Peripherals (except for radio) are shared so it's best to focus on CPU1 to initialize all peripherals so that CPU0 can only use them later. There is no real benefit to implement CPU0 if we don't have working LORA/radio support in nuttx. In time I will be implementing more and more things from this chip. Right now I would like this minimal implementation to be merged in case someone wants to work on this chip as well. Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl> --- patch v1->v2 - fixed formatting (suggested by Alan Carvalho de Assis) - rebased patch to master (previous patch was based on nuttx-10.2 and did not compile on master)	2022-06-07 22:28:32 +08:00
wangbowen6	af87921eda	arm/tlsr82: gpio driver bug fix and optimize. ... Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>	2022-06-07 22:26:36 +08:00
Jeonghyun Kim	9aa3edc11e	chip: stm32l4: Correct config mistype	2022-06-07 03:20:57 +08:00
Xiang Xiao	11e1a8b28b	arch: Define WCHAR_[MIN|MAX] in arch/include/limits.h ... follow up the below change: commit 6357523892 Author: Xiang Xiao <xiaoxiang@xiaomi.com> Date: Mon Nov 1 12:40:51 2021 +0800 arch: Add _wchar_t typedef like other basic types Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-06-03 22:25:49 +03:00
zhanghongyu	035d925864	devif: remove all devif_timer ... Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>	2022-06-02 20:11:50 -03:00
wangbowen6	acf21d2a8e	arm/tlsr82: support flash protection and voltage calibration. ... Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>	2022-06-02 15:25:48 +08:00
SPRESENSE	a25ac08774	boards: cxd56xx: Change pin initialization timing for camera ... Change pin initialization timing for camera from board power on to camera device power on for the following purposes. - avoid unnecessary power consumption - Make the corresponding pins available for other uses when camera is not in use	2022-05-30 20:38:47 +03:00
wangbowen6	360e319959	arm/tlsr82: ble performance optimize and problems solve. ... RF and system timer interrupt are used for ble. tlsr82_flash.c: 1. BLE will loss packets during flash operation beacause the interrupt is disabled and the operation take too long (especially erasing, about 100ms), so allow RF and system timer interrupt during flash operation; 2. Add sched_lock()/sched_unlock() to avoid the task switch in ble and system timer interrupt; flash_boot_ble.ld: 3. Because of 1, the code executes in RF and system timer interrupt must be in ram to avoid bus error. The sem_post() will be called and const variable g_tasklisttable will be accessed in RF and system timer interrupt handler; 4. To improve the performance, copy some frequently called function to ram as well, such as: sem_take(), sched_lock(), sched_unlock(), some lib functions, some zephyr ble functions and some tinycrypt functions; 5. The RF and system timer interrupt handler will call some libgcc functions, so copy all the libgcc functions to ram exclude _divdi3.o, _udivdi3.o and _umoddi3.o; tlsr82_serial.c 6. Make up_putc() be thread safe, add enter/leave_critical_section() in function uart_send_byte(); tc32_doirq.c 7. Increase the RF and system timer interrupt response priority; Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>	2022-05-30 19:52:38 +08:00
Xiang Xiao	7ec6b4c7dd	Change dpends on SCHED_[L|H]PWORK to SCHED_WORKQUEUE ... since the code could map the unsupported work to the supported one and remove select SCHED_WORKQUEUE from Kconfig since SCHED_[L|H]PWORK already do the selection Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-05-28 18:41:51 +03:00
klmchp	6bd2d172b0	Fix sama5d2 Kconfig errors and add missing pin definitions ... 1.Fix sama5d2 Kconfig. 2. Add missing pin definitions of sama5d2-xult board for sam_emacb and sam_lcd drivers.	2022-05-28 14:41:15 +08:00
Oki Minabe	f0fb530eaa	arch: imx6: add support kernel build and smp ... Summary: - add support BUILD_KERNEL and SMP for imx6 - prepare page tables of cpu1,2,3 - add sabre-6quad:knsh_smp config Impact: - imx6 Testing: - getprime, smp on sabre-6quad:knsh_smp w/ qemu Signed-off-by: Oki Minabe <minabe.oki@gmail.com>	2022-05-27 01:31:58 +08:00
chao.an	3f65b562bb	arch: inline up_interrupt_context() ... inline the up_interrupt_context() to avoid unnecessary stack pushes Signed-off-by: chao.an <anchao@xiaomi.com>	2022-05-26 04:36:07 +08:00
Alexey Matveev	684f2cbbac	Fix stm32 pwm HAVE_ADVTIM	2022-05-25 12:16:16 +03:00
Petro Karashchenko	7a6253cb89	arch/arm/samv7: Fix PWM operation for single channel mode ... The current SAMv7 PWM driver assumes that all PWM channels should work in sync mode, but that is a partial case of a generic PWM driver operation. Start SAMv7 PWM channels in async mode. The sync mode should be implemeted either using ioctl command or via a separate Kconfig option. Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-05-24 03:26:13 +08:00
wangbowen6	200109fd28	arm/tlsr82: optimize the adc driver. ... 1. Add vbat mode for chip internal voltage sample; 2. Add adc channel config; 3. Using DFIFO2 to get the sample value, follow telink sdk. 4. Add calibration function and config; Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>	2022-05-22 23:10:06 +08:00
Karel Kočí	a74c707da6	arch: arm: armv6-m: fix LTO build ... This imports changes from armv7-m.	2022-05-21 00:03:03 +08:00
YAMAMOTO Takashi	a9317b1895	cxd56xx: Implement up_textheap_heapmember	2022-05-20 21:16:42 +08:00
Sebastien Lorquet	517f179f8d	stm32h7: Adds the ability to choose the HSI divider, which must be indicated in board.h if used.	2022-05-18 11:59:07 -07:00
Xiang Xiao	b30e0a26ef	Move "-nostartfiles -nodefaultlibs" from Make.defs to Toolchian.defs ... and replace "-nostartfiles -nodefaultlibs" with "-nostdlib" Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-05-18 08:26:02 -04:00
Xiang Xiao	d3524d4f8b	arch/i2c: Change xxx_i2c_tousecs to xxx_i2c_toticks ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-05-15 23:22:01 +03:00
Xiang Xiao	f311228f80	arm/efm32: Fix typo error: CONFIG_EFM32_I2C_DYNTIMEOUT to CONFIG_EFM32_I2C_DYNTIMEO ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-05-15 19:18:09 +03:00
Xiang Xiao	1f920e55d3	Move warning option from Make.defs to Toolchain.defs ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-05-15 15:40:35 +03:00
Xiang Xiao	8b7c5b039d	arch: Move -fsanitize=kernel-address to ARCHOPTIMIZATION ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-05-15 15:40:35 +03:00
Xiang Xiao	51cf7ba05a	Remove FAR from arm/risc-v/xtensa/sim/x86 ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-05-15 13:55:58 +03:00
Xiang Xiao	2976accd9f	arch: Remove the extra space before the function prototype ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-05-15 13:55:58 +03:00
Xiang Xiao	1fb8c13e5e	Replace nxsem_timedwait_uninterruptible with nxsem_tickwait_uninterruptible ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-05-15 13:55:58 +03:00
Xiang Xiao	816ce73ab4	Replace nxsem_timedwait with nxsem_tickwait ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-05-15 13:55:58 +03:00
Petro Karashchenko	0fee5a2b84	nuttx: fix typos in comments ... Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-05-14 23:45:52 +08:00
Michal Lenc	6f6338cea0	imxrt/flexpwm: set number of modules based on configuration options ... Number of channels are now set based on enabled modules (channels) in configuration instead of the usage of static 4. Signed-off-by: Michal Lenc <michallenc@seznam.cz>	2022-05-13 12:55:45 -03:00
Michal Lenc	bdcf8b2b66	samv7/pwm: set number of channels based on configuration options ... Number of channels are now set based on enabled channels in configuration instead of the usage of static 4. Signed-off-by: Michal Lenc <michallenc@seznam.cz>	2022-05-13 12:55:45 -03:00
chao.an	701e56d4ae	arm/cortex-[a|r]: add performance counter implement ... Signed-off-by: chao.an <anchao@xiaomi.com>	2022-05-13 12:55:31 -03:00
chao.an	4da48c84ff	arm/cortex-[a|r]: add more functions of Performance Monitors Unit ... Reference: https://developer.arm.com/documentation/ddi0433/a/performance-monitoring-unit/performance-monitoring-register-descriptions Signed-off-by: chao.an <anchao@xiaomi.com>	2022-05-13 12:55:31 -03:00
chao.an	920e826a80	arm/cortex-r: rename PCMR_* to PMCR_* ... It should be PMCR (Performance Monitors Control Register) Signed-off-by: chao.an <anchao@xiaomi.com>	2022-05-13 12:55:31 -03:00
chao.an	34b124bc14	arm/cortex-r: add _pmu_* perfix for performance monitor functions ... Signed-off-by: chao.an <anchao@xiaomi.com>	2022-05-13 12:55:31 -03:00
Petro Karashchenko	f095bf8f39	arch/arm/samv7/sam_afec: fix ADC pin for channel 9 ... Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-05-13 11:17:37 -03:00
wangbowen6	f23ba7e761	arm/tlsr82: add hardware aes encrypt and decrypt support. ... Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>	2022-05-13 20:24:46 +08:00
Xiang Xiao	1ba316b5c7	arch: Remove board/libboard$(LIBEXT) from the rerequest of export_startup ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-05-12 23:34:31 +03:00
wangbowen6	bc61e71b94	crypto: change type uint32_t to size_t in aes_cypher() arguments. ... Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>	2022-05-12 22:28:54 +08:00
Ville Juven	47e85b68fe	arch/addrenv: Change text write enable/disable to generic mprot ... Implement a generic access rights modification procedure instead of the procedures that only do one thing (enable/disable write) to one section (text).	2022-05-12 22:28:31 +08:00
Matthew Trescott	f6f826c09a	Fix broken tiva_gpioirqclear	2022-05-12 14:49:35 +08:00
chao.an	04f7beea83	arm/tlsr82: fix kconfig warning ... arch/arm/src/tlsr82/Kconfig:272:warning: leading whitespace ignored Signed-off-by: chao.an <anchao@xiaomi.com>	2022-05-12 14:58:47 +09:00
wangbowen6	c39d3fa9e4	tlsr82/tc32: optimize the irq process ... 1. using armv6-m arm_irq(); 2. simplify the interrupt number get process; 3. To improve the performance, move common exception code to ram_code. Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>	2022-05-12 02:07:52 +08:00
wangbowen6	6caa8f1075	arm_createstack: fix warning for tc32 compiler. ... fix warning: common/arm_createstack.c: In function 'up_create_stack': common/arm_createstack.c:154:11: warning: format '%d' expects type 'int', but argument 3 has type 'size_t' Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>	2022-05-11 20:14:30 +03:00
wangbowen6	db1e6656dd	arm/tc32/Make.defs: filter-out arm_udelay.c ... tc32 architecture implement up_udelay by itself, so filter out arm_udelay.c. Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>	2022-05-11 21:57:01 +08:00
wangbowen6	28684f24b7	arm/tlsr82: pwm driver optimize and add pulse count support. ... 1. add pulse count support for pwm0; 2. add more detailed config for pwm; 3. pwm configuration and start process optimize; 4. tlsr82/Kconfig format; Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>	2022-05-11 13:15:44 +03:00
Xiang Xiao	0cf2330e41	arch/arm: Fix target 'arm_vectortab.o' given more than once in the same rule	2022-05-11 17:39:33 +09:00
Masayuki Ishikawa	1277bcfd15	arch: tiva: Fix TIVA_WITH_QEMU in Kconfig ... Summary: - TIVA_WITH_QEMU is used to run the NuttX with QEMU - The configuration should not depend on TIVA_ETHERNET - This commit fixes this issue Impact: - None Testing: - Tested with QEMU Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>	2022-05-11 15:09:34 +08:00
Xiang Xiao	0c8d3489e6	arch/arm: Fix target 'arm_fpuconfig.o' given more than once in the same rule ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-05-10 16:42:43 +03:00
Xiang Xiao	8634e8de64	Replace all sem_xxx with nxsem_xxx ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-05-10 15:08:36 +03:00
wangbowen6	73f7cc5855	tlsr82: first commit of telink tlsr82xx chip port. ... tlsr82: first commit of telink tlsr82xx chip port. - tc32 archtecture context switch; - tc32 backtrace; - timer, uart, pwm, gpio, adc driver; - flash, watchdog driver; - uart txdma/rxdma; - spi console driver; - add board bringup and reset; Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>	2022-05-09 12:33:39 +08:00
Zou Hanya	ce2a7d6d19	stm32 usbfs: Fix stm32_usbfs and add CONFIG_STM32_USBFS	2022-05-09 10:34:40 +08:00
Zou Hanya	654960da4b	stm32 usbfs: Add copy of stm32_usbdev	2022-05-09 10:34:40 +08:00
okayserh	2696aee11d	Fixed the bug that prevented the code from working in uninitialized ... state (wrong I2C write size). Some improvements of the code.	2022-05-09 10:34:29 +08:00
Xiang Xiao	1172ed306c	arch/arm: Remove arm_etherstub.c ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-05-08 16:58:50 +03:00
Xiang Xiao	fd468130e6	arm/common: Skip compile arm_[m|u]delay.c if CONFIG_[ALARM|TIMER]_ARCH is true ... since up_[m|u]delay provide in the common code in this case Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-05-08 16:58:50 +03:00
okayserh	476770e9fd	Added functionality for Audio support with the STM32F746 Discoboard ... In particular additions to wm8994.h and filled functionality into wm8994.c. Resolved a few more remarks from review.	2022-05-07 11:52:51 -03:00
Xiang Xiao	e84e5f0e1d	arch: Add gcov related config for arm/risc-v/xtensa ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-05-06 14:43:57 -03:00
Oki Minabe	3983efa47e	armv7-a: smp: allocate page table for each cpu ... Summary: - In case of SMP and ADDRENV, allocate the page table for each cpu - Each cpu holds separated addrenv and MMU setting Impact: - armv7-a Testing: - sabre-6quad:smp w/ qemu - sabre-6quad:knsh w/ qemu - sabre-6quad:knsh_smp w/ qemu (WIP) Signed-off-by: Oki Minabe <minabe.oki@gmail.com>	2022-05-06 18:30:20 +09:00
JacobCrabill	0a37bd8d4f	stm32: SocketCAN: allow non-late netdev initialization	2022-05-06 08:54:58 +02:00
JacobCrabill	b6d9eab7c9	stm32h7: Add FDCAN3_BASE to memorymap.h ... Note that pinmap.h, irq.h, fdcan.h still need to be updated with proper register definitions for the FDCAN3 peripheral present in STM32H7[2|3][3|5] MCUs	2022-05-06 08:54:58 +02:00
JacobCrabill	f406afdc42	arch/stm32h7: Add FDCAN SocketCAN driver ... Adds an FDCAN driver for STM32H7 MCUs using the SocketCAN interface	2022-05-06 08:54:58 +02:00
Oki Minabe	4fa21c4719	armv7-a: Inner Shareable TLB maintenance operations ... Summary: - Use Inner Shareable for TLB maintenance operations - Add config option as CONFIG_ARM_HAVE_MPCORE - This PR is in preparation for smp with kernel build Impact: - armv7-a Testing: - sabre-6quad:smp w/ qemu - sabre-6quad:knsh_smp w/ qemu (WIP) Signed-off-by: Oki Minabe <minabe.oki@gmail.com>	2022-05-06 15:26:59 +09:00
chao.an	0c223998c7	arm/cortex-m/toolchain: try print runtime library only in clang ... fix compile warning: make: arm-nuttx-elf-gcc: Command not found Signed-off-by: chao.an <anchao@xiaomi.com>	2022-05-05 17:31:12 +02:00
Simon Filgis	6e8c32e778	MCAN_INT_ACKE must be on the list of MCAN_TXERR_INTS to be properly handeled	2022-05-04 01:38:25 +08:00
Anton Potapov	862b815f87	Restore lost flash define for stm32.	2022-05-03 23:07:15 +08:00
Xiang Xiao	972a260391	arch/arm: Remove FAR and CODE from chip folder(3) ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-05-03 16:50:52 +03:00
Xiang Xiao	44ad6d0a23	arch/arm: Remove FAR and CODE from chip folder(2) ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-05-03 16:50:52 +03:00
Xiang Xiao	03c31d332f	arch/arm: Remove FAR and CODE from chip folder(1) ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-05-03 16:50:52 +03:00
Ville Juven	248b738f25	arm_addrenv: Add stubs for modifying permissions ... Adds stubs for up_addrenv_text_enable/disable_write. These don't have to do anything as the ARM MMU allows setting access per mode. Currently the settings for user .text area grants the kernel write access, but revokes user write access.	2022-05-03 21:25:25 +09:00
Oki Minabe	0ba891c1b0	armv7-a: smp: fix stack coloration ... Summary: - The stack pointer is subtracted to alloc xcptcontext area in the __cpu?_start block - Fix the stack coloration overrun to the previous cpu's xcpt area Impact: - armv7-a's smp configuration Testing: - smp and ostest on sabre-6quad:smp w/ qemu Signed-off-by: Oki Minabe <minabe.oki@gmail.com>	2022-05-03 19:12:04 +08:00
Xiang Xiao	f77a0ec7fa	arch: Move -finstrument-functions from Make.defs to Toolchain.defs ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-05-01 23:54:15 +03:00
Xiang Xiao	1fde7e17bb	arch: Move -fstack-protector-all from Make.defs to Toolchain.defs ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-05-01 23:54:15 +03:00
Xiang Xiao	aeb9c5d822	boards: Move -fno-strict-aliasing from Make.defs to Toolchain.defs ... and migrate MAXOPTIMIZATION into ARCHOPTIMIZATION Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-05-01 11:36:41 +03:00
chao.an	5db447623d	arm/cxd56xx/lc823450/rp2040: replace arch testset to board implement ... This patch to resolve the regression which leads to the breakage of spresense:smp Signed-off-by: chao.an <anchao@xiaomi.com>	2022-05-01 06:38:25 +09:00
chao.an	3ec2f70046	arch/arm/Make.defs: unify arch common source include ... Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-30 21:50:16 +08:00
chao.an	8951b0135b	arch/cortex-[a|r]/Make.defs: unify arch common source include ... Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-30 21:50:16 +08:00
chao.an	5677fe2153	arch/cortex-m/Make.defs: unify arch common source include ... Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-30 21:50:16 +08:00
chao.an	a560eb5f8d	arch/arm/Make.defs: unify common source include ... Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-30 21:50:16 +08:00
Xiang Xiao	94cb0c6072	arch: Move -nostdinc++ to Tooolchain.defs ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-04-29 21:08:14 -03:00
Simon Filgis	385519302e	Corrected typo in sam_spi.c. Debaugcall needs cs not if as ref... ... Signed-off-by: Simon Filgis <simon@ingenieurbuero-filgis.de>	2022-04-30 03:13:38 +08:00
Oki Minabe	c38234e342	armv7-a/r: use cps instruction to change cpu mode ... Summary: - Use CPS instruction to change cpu mode for code simplification - CPS which changes cpu mode is available in armv6 and above Impact: - armv7-a/r Testing: - smp and ostest on sabre-6quad:smp w/ qemu Signed-off-by: Oki Minabe <minabe.oki@gmail.com>	2022-04-30 03:13:22 +08:00
Ville Juven	b3baf95835	UMM: Implement getter for address environment heap start vaddr ... Using the Kconfig macro does not work for RISC-V target, as there the user heap follows .data/.bss and does not obey any Kconfig provided boundary. Added stubs for ARM and Z80 also.	2022-04-29 23:13:16 +08:00
Sergey Nikitenko	19c5ac9135	stm32l4 fix ECCR comment	2022-04-29 09:30:09 +03:00
Sergey Nikitenko	3cc8d7d52a	stm32l4 rtcc register fixes	2022-04-29 09:30:09 +03:00
Sergey Nikitenko	0b9a36d142	stm32l4 fix tim channel range checking	2022-04-29 09:30:09 +03:00
Sergey Nikitenko	541b03b787	stm32l4 TIM register fixes	2022-04-29 09:30:09 +03:00
Sergey Nikitenko	57c64d327e	stm32l4 FLASH_CR_FSTPG register fix	2022-04-29 09:30:09 +03:00
Sergey Nikitenko	50fb3b5dc0	stm32l4 fixing proper register name RCC_APB1ENR1_PWREN	2022-04-29 09:30:09 +03:00
Sergey Nikitenko	b73e89a674	stm32l4 RCC multi-bit field fixes	2022-04-29 09:30:09 +03:00
Sergey Nikitenko	7e4193c4a3	stm32l4 remove useless RTCPRE setup	2022-04-29 09:30:09 +03:00
Sergey Nikitenko	9850766d07	stm32l4 RCC SW/SWS comment fixes	2022-04-29 09:30:09 +03:00
Sergey Nikitenko	3da7706db8	stm32l4+ DMAMUX register fix	2022-04-29 09:30:09 +03:00
chao.an	042640abbf	arch/arm: add support for GCC LTO ... 1. Enable GCC link-time optimizer 2. Enable use of a linker plugin during link-time optimization Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-27 23:42:54 +08:00
chao.an	db54b0b836	arm/assert: fix build warning on clang ... common/arm_assert.c:80:14: warning: format specifies type 'unsigned int' but the argument has type 'uint32_t' (aka 'unsigned long') [-Wformat] stack, ptr[0], ptr[1], ptr[2], ptr[3], ^~~~~ include/debug.h:119:59: note: expanded from macro '_alert' __arch_syslog(LOG_EMERG, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__) ~~~~~~ ^~~~~~~~~~~ Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-27 14:18:42 +08:00
Xiang Xiao	8f8ee25a9c	boards: Move -g from Make.defs to Toolchain.defs ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-04-25 16:23:03 +03:00
Xiang Xiao	75326e563d	boards: Move -fno-common from Make.defs to Toolchain.defs ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-04-25 07:57:29 +03:00
Xiang Xiao	5a565e753c	pm: Move pm_initialize call from driver_initialize to xxx_pminitialize ... since it's too late with the below commit: ommit a594a5d7a8 Author: chao.an <anchao@xiaomi.com> Date: Mon Apr 11 19:44:26 2022 +0800 sched/init: drivers_initialize() should be late than up_initialize() up_initialize | ->up_serialinit | ->uart_register /* ("/dev/console", &CONSOLE_DEV); */ drivers_initialize | ->syslog_console_init | ->register_driver /* ("/dev/console", &g_consoleops, 0666, NULL); */ Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-04-22 14:36:27 +03:00
chao.an	1c8e12406e	compile/opt: add config DEBUG_LINK_MAP ... Selecting this option will pass "-Map=$(TOPDIR)$(DELIM)nuttx.map" to ld when linking NuttX ELF. That file can be useful for verifying and debugging magic section games, and for seeing which pieces of code get eliminated with DEBUG_OPT_UNUSED_SECTIONS. Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-22 01:37:23 +08:00
chao.an	64d7326ed5	compile/opt: add config DEBUG_OPT_UNUSED_SECTIONS ... Enable this option to optimization the unused input sections with the linker by compiling with " -ffunction-sections -fdata-sections ", and linking with " --gc-sections ". Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-22 01:37:23 +08:00
Xiang Xiao	1320e5add4	arch/arm: Move the duplicated assembly code to common folder ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-04-21 12:56:34 +03:00
Xiang Xiao	ebf1093cff	arch/arm: Switch the context of save and restore from assembler to c ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-04-21 12:56:34 +03:00
chao.an	875c5dac75	arm/armv[7|8]m: compare of hardware fp registers should skip REG_FP_RESERVED ... Fix fpu test break Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-21 14:55:54 +09:00
chao.an	0315283c21	arch/clang: add support for Clang LTO ... add support of Clang's Link Time Optimization (LTO) on NuttX build system Reference: https://gcc.gnu.org/onlinedocs/gccint/LTO-Overview.html https://llvm.org/docs/LinkTimeOptimization.html Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-21 01:21:54 +08:00
chao.an	67fbfda974	arch/armv6-m: add support of LLVM Clang ... Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-21 01:21:54 +08:00
Alin Jerpelea	af98967439	arch: arm: stm32l4: remove empty files ... during contribution empty files have been pushed. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>	2022-04-20 21:05:45 +08:00
Alin Jerpelea	73cd86dad7	arch: arm: phy62xx: Add Apache license to files ... In the initial contribution those files were missing the license Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>	2022-04-20 21:05:45 +08:00
Alin Jerpelea	22ceda26bb	arch: arm: lpc43xx: Add Apache license to files ... In the initial contribution those files were missing the license Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>	2022-04-20 21:05:45 +08:00
Alin Jerpelea	4e19a97916	arch: arm: imxrt: Add Apache license to files ... In the initial contribution those files were missing the license Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>	2022-04-20 21:05:45 +08:00
Alin Jerpelea	208b892efe	arch: arm: cxd56xx: Add Apache license to files ... In the initial contribution those files were missing the license Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>	2022-04-20 21:05:45 +08:00
zhuyanlin	8d756a75a2	armv7/r:cp15_cache_all: fix error in LineSize 'r5' mask ... r5 = r3 & r1 Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2022-04-20 08:06:58 +09:00
chao.an	2df591b3bb	arch/armv7-a/r: Unify the toolchain definition of eabi for linux and windows ... Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-19 23:17:27 +08:00
chao.an	4a085e1cdb	arch/arm/armv6-m: Unify the toolchain definition of eabi for linux and windows ... Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-19 23:17:27 +08:00
chao.an	2246afcdd8	arch/armv7-m: Unify the toolchain definition of eabi/clang/iar for linux and windows ... Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-19 23:17:27 +08:00
chao.an	a79bf8c9eb	arch/armv8-m: Unify the toolchain definition of eabi/clang for linux and windows ... Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-19 23:17:27 +08:00
Ville Juven	5c951d8c4a	arm/arm_assert.c Fix dumping of status from ISR ... The status dump did not work if the first fault triggers before the first context switch (during nx_start()).	2022-04-19 15:28:09 +03:00
chao.an	b110c984b1	arch/armv7-[a|r]: correct the handing of group env switch ... This PR resolved 2 issues: 1. CURRENT_REGS is not set correctly on swint handling 2. group env is not changed properly Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-19 12:10:25 +03:00
Xiang Xiao	96fa8be5f5	arch/armv[7|8]-m: Compare all FPU registers in up_fpucmp ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-04-19 11:09:36 +03:00
Xiang Xiao	d80c2d7419	arch/arm: Remove all lazy fpu related code ... since it is broken and inefficient, and then removed by: commit dc961baaea Author: chao.an <anchao@xiaomi.com> Date: Thu Apr 14 18:07:14 2022 +0800 arm/armv7-[a|r]: move fpu save/restore to assembly handler Save/Restore FPU registers in C environment is dangerous practive, which cannot guarantee the compiler won't generate the assembly code with float point registers, especially in interrupt handling Signed-off-by: chao.an <anchao@xiaomi.com> commit 8d66dbc068 Author: chao.an <anchao@xiaomi.com> Date: Thu Apr 7 13:48:04 2022 +0800 arm/armv[7|8]-m: skip the fpu save/restore if stack frame is integer-only Signed-off-by: chao.an <anchao@xiaomi.com> Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-04-19 11:09:36 +03:00
Xiang Xiao	7c5b2e3305	arch/arm: Remove FAR and CODE from common/ and arm*/ folder ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-04-19 00:23:59 +03:00
Xiang Xiao	84b0453ef3	arch/arm: Remove unneeded group_addrenv call which handled by arm_doirq ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-04-18 22:18:32 +03:00
chao.an	29005bd79f	board/arch_fpu*: move arch_[get|cmp]fpu to common arch ... rename the arch api: arch_getfpu -> up_saveusercontext arch_cmpfpu -> up_cmpfpu Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-18 22:22:16 +08:00
chao.an	5bdfae66ce	arch/arm: export arm_saveusercontext() ... rename arm_saveusercontext() -> up_arm_saveusercontext() Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-18 22:22:16 +08:00
chao.an	bdbbdbe242	arm/a1x: fix compile break ... Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-18 10:02:17 +08:00
Xiang Xiao	ef1a98dd00	Remove the unneeded void cast ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-04-17 23:32:05 +03:00
Xiang Xiao	32ee2ae407	Remove the unneeded worker_t cast ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-04-17 23:32:05 +03:00
Xiang Xiao	373363d750	arch/arm: Move arm_signal_dispatch.c to common folder ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-04-17 23:30:41 +03:00
wangbowen6	91d02f5db8	arm/arch: using __builtin_frame_address(0) implement up_getsp(). ... Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>	2022-04-18 00:49:15 +08:00
chao.an	c08d9047b2	arch/Toolchain.defs: replace all ${/$} with $(/$) ... Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-17 00:58:34 +08:00
chao.an	aed21ba0bc	arch/armv[7|8]m: enhance the clang support ... Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-17 00:58:34 +08:00
okayserh	3a015d56b0	Fixed a compile error, presumably caused by C&P error.	2022-04-16 19:21:10 +08:00
Petro Karashchenko	09b3fb25ab	drivers: remove unimplemented open/close/ioctl interfaces ... Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-04-15 16:56:25 +08:00
Richard Tucker	1b13d1b440	arch/arm/src/sam34/Kconfig: fix typo in device name	2022-04-15 02:22:01 +08:00
Richard Tucker	de66e18d6f	arch/arm/src/sam34/sam_hsmci.c: SAM3X GPIO setup	2022-04-15 02:22:01 +08:00
Richard Tucker	929556d750	arch/arm/src/sam34/sam_hsmci: DMA also present on SAM3X chips	2022-04-15 02:22:01 +08:00
Richard Tucker	be0bcac91b	arch/arm/src/sam34/sam_hsmci.c: DMA setup before write is required	2022-04-15 02:22:01 +08:00
Richard Tucker	bc7f4b2375	arch/arm/src/sam34/sam_hsmci.c: delay required after sending command	2022-04-15 02:22:01 +08:00
chao.an	dc961baaea	arm/armv7-[a|r]: move fpu save/restore to assembly handler ... Save/Restore FPU registers in C environment is dangerous practive, which cannot guarantee the compiler won't generate the assembly code with float point registers, especially in interrupt handling Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-14 22:33:10 +08:00
Xiang Xiao	a94b7b9cca	arm/rtl8720c: Remove up_getsp which is already implemented in arch/arm/arch.h ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-04-14 16:35:52 +03:00
chao.an	b3d47e246f	arch/stack_color: correct the stack top of running task ... This PR to ensure the stack pointer is locate to the stack top Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-14 16:48:19 +08:00
chao.an	0c79ad9d8d	arch/[arm|sparc]: replace INT32_ALIGN_* to STACK_ALIGN_* ... Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-14 16:48:19 +08:00
Abdelatif Guettouche	6d12ee19e2	arch: Move the DUMP_ON_EXIT logic after nxtask_exit. ... Otherwise we will try to dump the state of the current task, however the exit handler has already started doing some cleanup and invalidated its group. Accessing the group from dumponexit will crash. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2022-04-13 21:59:23 +08:00
Abdelatif Guettouche	d6c952c56f	arch: Fix compile error when enabling CONFIG_DUMP_ON_EXIT ... "error: incompatible types when assigning to type 'struct filelist *' from type 'struct filelist' filelist = tcb->group->tg_filelist;" Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2022-04-13 21:59:23 +08:00
chao.an	0d7ea348d5	arm/armv8-m: indicating no low-overhead-loop predication by default ... Fix usage fault on clang version 13.0.0 (-Ofast): ------------------------------------------------------------------ | arm_hardfault: Hard Fault escalation: | arm_usagefault: PANIC!!! Usage Fault: | arm_usagefault: IRQ: 3 regs: 0x3c58c510 | arm_usagefault: BASEPRI: 00000080 PRIMASK: 00000000 IPSR: 00000003 CONTROL: 00000004 | arm_usagefault: CFSR: 00020000 HFSR: 40000000 DFSR: 00000000 BFAR: 01608050 AFSR: 00000000 | arm_usagefault: Usage Fault Reason: | arm_usagefault: Invalid state | up_assert: Assertion failed at file:armv8-m/arm_usagefault.c line: 113 task: lpwork | backtrace: | [ 2] [<0x2c58124a>] up_backtrace+0xa/0x2e2 | [ 2] [<0x2c56f7cc>] sched_dumpstack+0x28/0x66 | [ 2] [<0x2c580cd0>] up_assert+0x62/0x254 | [ 2] [<0x2c56ab8a>] _assert+0/0xa | [ 2] [<0x2c55575a>] nxsched_add_prioritized+0x38/0xa2 | [ 2] [<0x2c555894>] nxsched_add_blocked+0x2e/0x44 | [ 2] [<0x2c580748>] up_block_task+0x2a/0x96 | [ 2] [<0x2c5569ea>] nxsem_wait+0x64/0xb4 | [ 2] [<0x2c556a40>] nxsem_wait_uninterruptible+0x6/0x10 | [ 2] [<0x2c559b9a>] work_thread+0x1c/0x48 ------------------------------------------------------------------- usage fault on 0x2c55575a: ------------------------------------ |2c555722 <nxsched_add_prioritized>: |; { |2c555722: 80 b5 push {r7, lr} |... |2c55575a: 2f f0 17 c0 le 0x2c555732 <nxsched_add_prioritized+0x10> @ imm = #-44 |... ------------------------------------ Arm v8-M Architecture Reference Manual: C2.4.103 LE, LETP B3.28 Low overhead loops: An INVSTATE UsageFault is raised if a LE instruction is executed and FPSCR.LTPSIZE does not read as four. When a new floating-point context is created and FPCCR.ASPEN is set to zero it is the responsibility of software to correctly initialize FPSCR.LTPSIZE. Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-13 09:39:22 +08:00
chao.an	ff210e1c2d	arch/stack_color: correct the end address of stack color ... The different optimization of compilers will cause ambiguity in obtaining sp through up_getsp() in arm_stack_color(), if compile with clang and enable the optimization flag (-Ofast), up_getsp() call will be earlier than push {r0-r9,lr}, the end address of color stack will overlap with saved registers. Compile line: clang --target=arm-none-eabi -c "-Ofast" -fno-builtin -march=armv8.1-m.main+mve.fp+fp.dp \ -mtune=cortex-m55 -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -D__NuttX__ -common/arm_checkstack.c -o arm_checkstack.o Assembler code: llvm-objdump -aS arm_checkstack.o ------------------------------------ |00000000 <arm_stack_color>: |; start = INT32_ALIGN_UP((uintptr_t)stackbase); | 0: c2 1c adds r2, r0, #3 | 2: 22 f0 03 02 bic r2, r2, #3 |; end = nbytes ? INT32_ALIGN_DOWN((uintptr_t)stackbase + nbytes) : | 6: 19 b1 cbz r1, 0x10 <arm_stack_color+0x10> @ imm = #6 | 8: 08 44 add r0, r1 | a: 20 f0 03 00 bic r0, r0, #3 | e: 00 e0 b 0x12 <arm_stack_color+0x12> @ imm = #0 |; __asm__ | 10: 68 46 mov r0, sp <--- fetch the sp before push {r7 lr} | 12: 80 b5 push {r7, lr} <--- sp changed |; nwords = (end - start) >> 2; | 14: 80 1a subs r0, r0, r2 | 16: 80 08 lsrs r0, r0, #2 |; } | 18: 08 bf it eq | 1a: 80 bd popeq {r7, pc} | 1c: 4b f6 ef 63 movw r3, #48879 | 20: cd f6 ad 63 movt r3, #57005 | 24: a0 ee 10 3b vdup.32 q0, r3 |; while (nwords-- > 0) | 28: 20 f0 01 e0 dlstp.32 lr, r0 |; *ptr++ = STACK_COLOR; <--- overwrite | 2c: a2 ec 04 1f vstrw.32 q0, [r2], #16 | 30: 1f f0 05 c0 letp lr, 0x2c <arm_stack_color+0x2c> @ imm = #-8 |; } | 34: 80 bd pop {r7, pc} ------------------------------------ Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-13 09:37:54 +08:00
Xiang Xiao	df5a8a53ae	arch/arm: Move FPU initialization to common place ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-04-12 23:35:06 +03:00
SPRESENSE	39f7c4aea0	arch: cxd56xx: Fix critical section in scu driver ... Add critical section to scu one-shot sequencer.	2022-04-12 07:55:00 +09:00
SPRESENSE	e725829547	cxd56xx/cxd56_emmc.c: Fix compile warning ... Add necessary include header named debug.h for using ferr and finfo.	2022-04-12 07:55:00 +09:00
SPRESENSE	5be940080b	arch: cxd56xx: update loader and gnssfw version ... Update loader and gnssfw to version 2.2.20585	2022-04-12 07:55:00 +09:00
Xiang Xiao	c235c0fa43	boards/lx_cpu: Enable up_perf API ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-04-08 21:02:13 -03:00
Xiang Xiao	1f7b49d700	boards/nucleo-h743zi2: Enable up_perf API ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-04-08 21:02:13 -03:00
chao.an	8d66dbc068	arm/armv[7|8]-m: skip the fpu save/restore if stack frame is integer-only ... Signed-off-by: chao.an <anchao@xiaomi.com>	2022-04-08 14:28:41 +09:00
Jiuzhu Dong	d87cf8d4ca	fs/poll: change format for type pollevent_t ... Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>	2022-04-07 12:14:06 +08:00
zhuyanlin	6a761ff087	arch:tcbinfo: update tcbinfo as xcpcontext update ... Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2022-04-05 13:33:00 +02:00
Petro Karashchenko	d08fbca679	nuttx: unify FAR attribute usage across the code ... Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-04-04 21:32:58 +08:00
Michael Jung	e3926ecb16	stm32u5: stm32_stdclockconfig fixes ... Fix stm32_stdclockconfig for stm32u585xx to the extend that the B-U585I-IOT02A board's clock tree can be configured. This board uses the MSIS as PLL1's input clock and the LSE to autotrim the MSIS.	2022-04-03 23:20:03 +03:00
wangbowen6	bcb2530b18	arm/chip: add backtrace support for all chips that support thumb instruction set. ... Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>	2022-04-03 00:22:57 +08:00
raiden00pl	b487101b87	stm32: add support for up_perf	2022-04-02 10:34:35 -03:00
Gustavo Henrique Nihei	e1f28c19c2	arch/arm: Make CXX exception and RTTI depend on Kconfig options ... Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2022-03-30 11:19:29 +08:00
chao.an	a98a599cb9	arm/cortex-[a|r]: IRQ Switch return should with shadow SPSR ... The SPSR is used to store the current value of the CPSR when an exception is taken so that it can be restored after handling the exception. Each exception handling mode can access its own SPSR. User mode and System mode do not have an SPSR because they are not exception handling modes. Signed-off-by: chao.an <anchao@xiaomi.com>	2022-03-30 08:12:26 +09:00
ligd	0f02791ae6	armv8-m: add wake_func arm_should_generate_nonsecure_busfault ... Signed-off-by: ligd <liguiding1@xiaomi.com>	2022-03-28 22:52:28 +08:00
ligd	60fc933261	armv8-m: make the securefault handled by non-securefult ... tee is secure cpu and ap is non-secure cpu. The crash PC can get by IP (R12). [ EMERG] [tee] arm_hardfault: Hard Fault escalation: [ EMERG] [tee] arm_securefault: PANIC!!! Secure Fault: [ EMERG] [tee] arm_securefault: IRQ: 3 regs: 0x2400ff00 [ EMERG] [tee] arm_securefault: BASEPRI: 000000e0 PRIMASK: 00000000 IPSR: 00000003 CONTROL: 0000000c [ EMERG] [tee] arm_securefault: CFSR: 00000000 HFSR: 40000000 DFSR: 00000000 [ EMERG] [tee] arm_securefault: BFAR: 08006008 AFSR: 00000000 SFAR: 3c049ea0 [ EMERG] [tee] arm_securefault: Secure Fault Reason: [ EMERG] [tee] arm_securefault: Attribution unit violation [ EMERG] [tee] arm_securefault_handled_by_ns: Non-sec sp 3c475678 [ EMERG] [ap] arm_busfault: PANIC!!! Bus Fault: [ EMERG] [ap] arm_busfault: IRQ: 5 regs: 0x3c475608 [ EMERG] [ap] arm_busfault: BASEPRI: 000000e0 PRIMASK: 00000000 IPSR: 00000005 CONTROL: 00000004 [ EMERG] [ap] arm_busfault: CFSR: 00000100 HFSR: 40000000 DFSR: 00000000 BFAR: 08006008 AFSR: 20000000 [ EMERG] [ap] arm_busfault: Bus Fault Reason: [ EMERG] [ap] arm_busfault: Instruction bus error [ EMERG] [ap] up_assert: Assertion failed at file:armv8-m/arm_busfault.c line: 105 task: nsh_main [ EMERG] [ap] backtrace: [ EMERG] [ap] [ 9] [<0x2c565246>] up_backtrace+0xa/0x168 [ EMERG] [ap] [ 9] [<0x2c550118>] sched_dumpstack+0x1c/0x60 [ EMERG] [ap] [ 9] [<0x2c5645d6>] up_assert+0x4e/0x324 [ EMERG] [ap] [ 9] [<0x2c54a98e>] _assert+0x2/0x10 [ EMERG] [ap] [ 9] [<0x2c5636d4>] arm_busfault+0xc8/0x15c [ EMERG] [ap] [ 9] [<0x2c523070>] irq_dispatch+0x40/0x11c [ EMERG] [ap] [ 9] [<0x2c563424>] arm_doirq+0x28/0x3c [ EMERG] [ap] [ 9] [<0x2c55c892>] exception_common+0x4a/0xac [ EMERG] [ap] [ 9] [<0x2c58668e>] nsh_parse_command+0x976/0x12b4 [ EMERG] [ap] [ 9] [<0x2c849cee>] write+0x52/0x74 [ EMERG] [ap] [ 9] [<0x2c58c0ac>] nsh_session+0x2c/0x1c8 [ EMERG] [ap] [ 9] [<0x2c58d82c>] nsh_consolemain+0x28/0x54 [ EMERG] [ap] [ 9] [<0x2c590352>] nsh_main+0x2a/0x48 [ EMERG] [ap] [ 9] [<0x2c5500da>] cxx_initialize+0x2a/0x4c [ EMERG] [ap] [ 9] [<0x2c550090>] nxtask_startup+0x14/0x34 [ EMERG] [ap] [ 9] [<0x2c52966a>] nxtask_start+0x92/0xb8 [ EMERG] [ap] arm_registerdump: R0: 3c049ea0 R1: 00000004 R2: 3c448f98 R3: 00000000 [ EMERG] [ap] arm_registerdump: R4: 3c476a98 R5: 3c049ea0 R6: 00000000 FP: 3c476aac [ EMERG] [ap] arm_registerdump: R8: 2c5873c9 SB: 3c049ea0 SL: 3c2e98fc R11: 3c284c2c [ EMERG] [ap] arm_registerdump: IP: 2c58ba4a SP: 3c4756e0 LR: 3c049ea4 PC: 00000000 [ EMERG] [ap] arm_registerdump: xPSR: 610f0000 BASEPRI: 000000e0 CONTROL: 00000004 [ EMERG] [ap] arm_registerdump: EXC_RETURN: ffffffa8 [ EMERG] [ap] arm_dump_stack: IRQ Stack: [ EMERG] [ap] arm_dump_stack: sp: 3c41c900 Signed-off-by: ligd <liguiding1@xiaomi.com>	2022-03-28 22:52:28 +08:00
Huang Qi	ad1098d413	arch/armv7-a: Fix a typo in Toolchain.defs ... Signed-off-by: Huang Qi <huangqi3@xiaomi.com>	2022-03-28 12:42:43 +03:00
lishaoen	aa0c9fd788	nuttx: Add new config ARM_HAVE_MVE for MVE instruction ... Signed-off-by: lishaoen <lishaoen@xiaomi.com>	2022-03-28 08:51:24 +03:00
Xiang Xiao	8c8c60f70a	arch: Add -fsanitize=kernel-address to ARCHCPUFLAGS if CONFIG_MM_KASAN=y ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-03-27 23:01:47 +03:00
ligd	e87d262c7f	arch/Toolchain.defs: add wildcard for EXTRA_LIBS ... VELAPLATFO-1491 Signed-off-by: ligd <liguiding1@xiaomi.com>	2022-03-27 22:53:58 +03:00
Xiang Xiao	a2e079fdd2	arch/arm: Change arm_arch.h to arm_internal.h in arm_perf.c ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-03-27 22:31:43 +03:00
Anthony Merlino	baeb2e9af7	stm32h7: Addresses tickless PR review comments	2022-03-28 00:33:26 +08:00
Anthony Merlino	896435e7c9	Fixes formatting	2022-03-28 00:33:26 +08:00
Anthony Merlino	c3745c8441	Adjust up_timer_getmask to handle 16-bit timers correctly.	2022-03-28 00:33:26 +08:00
Anthony Merlino	30f6dbc613	Throw compile time error if tickless timer is set to TIM6/TIM7	2022-03-28 00:33:26 +08:00
Anthony Merlino	95199f4790	stm32h7 timer: Clean up some bit operations to make them more readable.	2022-03-28 00:33:26 +08:00
Anthony Merlino	e5c8bb9b34	stm32h7: Fix a bunch of tickless issues.	2022-03-28 00:33:26 +08:00
Anthony Merlino	2fad06008a	stm32h7: Adds tickless support.	2022-03-28 00:33:26 +08:00
ligd	f623ac0f13	armv7-m/armv8-m: move up_pref* api to common place ... Signed-off-by: ligd <liguiding1@xiaomi.com> Signed-off-by: chao.an <anchao@xiaomi.com>	2022-03-26 13:39:18 +02:00
Huang Qi	9cffc105c8	arch: Show assigned cpu in dump task ... Signed-off-by: Huang Qi <huangqi3@xiaomi.com>	2022-03-23 22:18:15 +08:00
chao.an	7b73606300	arm/schedulesigaction: update the SP to signal context top ... Signed-off-by: chao.an <anchao@xiaomi.com>	2022-03-23 19:08:37 +09:00
chao.an	a770ff2017	arm/vfork: update the SP to stack top ... Signed-off-by: chao.an <anchao@xiaomi.com>	2022-03-23 19:08:37 +09:00
Xiang Xiao	9ae0dcd4a2	arch/arm: Remove the code copy register from xcpt to stack ... since xcpt always point to the stack after the below change: commit 7b9978883c Author: chao.an <anchao@xiaomi.com> Date: Tue Mar 1 01:06:24 2022 +0800 arch/arm: optimize context switch speed The current context save implementation saves registers of each task to xcp context, which is unnecessary because most of the arm registers are already saved in the task stack, this commit replace the xcp context with stack context to improve context switching performance and reduce the tcb space occupation of tcb instance. Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-03-23 19:08:37 +09:00
Petro Karashchenko	68902d8732	pid_t: unify usage of special task IDs ... Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-03-22 21:22:32 +08:00
Harri Luhtala	2ee12b2c5d	arch/arm/src/stm32l4: peripheral voltage monitor support for vddio2 ... Signed-off-by: Harri Luhtala <harri.luhtala@haltian.com>	2022-03-22 21:08:29 +08:00
Petro Karashchenko	757d01d915	progmem: eliminate PROGMEM_ERASESTATE configuration option ... Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-03-22 10:01:41 -03:00
smartether	7fbadb5c16	fixed mpu9250 not work on i2c bus issue. ... 1,set rp2040 FIFO_MAX_SIZE to 16.ref: pico sdk -> static inline size_t i2c_get_write_available(i2c_inst_t *i2c) { const size_t IC_TX_BUFFER_DEPTH = 16; return IC_TX_BUFFER_DEPTH - i2c_get_hw(i2c)->txflr; }	2022-03-21 12:07:03 +08:00
Petro Karashchenko	3fff4508c7	netinitialize: call xxx_netinitialize unconditionally ... The xxx_netinitialize is defined to a function only if CONFIG_NET=y and CONFIG_NETDEV_LATEINIT=n. Otherwise it is defined to an empty macro. Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-03-19 17:41:33 +08:00
Huang Qi	edef327655	arch/arm: Move ARCHCPUFLAGS to Toolchain.defs ... Signed-off-by: Huang Qi <huangqi3@xiaomi.com>	2022-03-19 02:24:00 +08:00
Petro Karashchenko	c1fb14ccaa	boards/arm/samv7/same70-qmtech: add /dev/timer0 support ... Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-03-19 02:21:03 +08:00
wangbowen6	7de7ba1b7e	phy62xx_exception: using armv6-m exception_common code. ... Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>	2022-03-18 20:01:00 +08:00
chao.an	19119a9c43	arch/arm: set the SP to stack top ... fix the stack imbalance Signed-off-by: chao.an <anchao@xiaomi.com>	2022-03-18 07:56:51 +09:00
Petro Karashchenko	c3bae60c57	drivers/can: optimize can driver reader side ... Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-03-17 15:43:15 +08:00
SPRESENSE	c05ace557f	arch: cxd56xx: Fix critical section in serial transmission ... Fix an issue that the serial transmission buffers are corrupted because serial transmission are not protected by critical section in non-smp mode.	2022-03-16 20:23:41 +09:00
Petro Karashchenko	985829190e	arch/arm/samv7/sam_tc: implement timer driver support ... Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-03-16 03:19:57 +08:00
Matthew Trescott	8c471db932	Corrections to Tiva KConfig	2022-03-15 11:32:31 -04:00
Matthew Trescott	bc80bbddc7	Add Tiva CAN driver	2022-03-15 11:32:31 -04:00
chao.an	81130bc692	arch/arm: remove unused arm_copyfullstate/arm_copyarmstate ... Signed-off-by: chao.an <anchao@xiaomi.com>	2022-03-15 23:03:51 +09:00
chao.an	7b9978883c	arch/arm: optimize context switch speed ... The current context save implementation saves registers of each task to xcp context, which is unnecessary because most of the arm registers are already saved in the task stack, this commit replace the xcp context with stack context to improve context switching performance and reduce the tcb space occupation of tcb instance. Signed-off-by: chao.an <anchao@xiaomi.com>	2022-03-15 23:03:51 +09:00
Petro Karashchenko	b04447d066	timer_lowerhalf: minor improvements ... Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-03-15 10:30:48 +08:00
Xiang Xiao	b6bc460b2c	arch: Make the comment and definition of CONFIG_SYS_RESERVED correctly ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-03-14 22:51:00 +02:00
chao.an	ea42981cc6	syscall/names: export the syscall name in STUB module ... Signed-off-by: chao.an <anchao@xiaomi.com>	2022-03-14 21:37:53 +02:00
chao.an	d398ffb930	arm/armv7-a/r: unified syscall registers dump ... Signed-off-by: chao.an <anchao@xiaomi.com>	2022-03-14 21:37:53 +02:00
chao.an	7c02432f0e	arm/armv7-a/r: set the default CPU mode to System ... In SVC mode, the banked register will be inconsistent with the user mode register: arch/arm/src/armv7-a/arm_vectors.S 276 .globl arm_syscall 277 .globl arm_vectorsvc 278 .type arm_vectorsvc, %function 279 280 arm_vectorsvc: ... 286 sub sp, sp, #XCPTCONTEXT_SIZE // < SVC mode SP ... 308 stmia r0, {r13, r14}^ // < USR mode SP/LR ... [ 2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 4 [ 2.200000] [ 4] [ ALERT] R0: 00000004 80001229 00000001 80202018 00000000 00000000 00000000 802027d0 [ 2.200000] [ 4] [ ALERT] R8: 00000000 00000000 00000000 00000000 00000000 802027d0 1080f710 1080f710 [ 2.200000] [ 4] [ ALERT] CPSR: 00000073 [ 2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708 [ 2.200000] [ 4] [ ALERT] R0: 1 80202018 1 80202018 0 0 0 802027d0 [ 2.200000] [ 4] [ ALERT] R8: 0 0 0 0 0 802027d0 1080f710 80001229 [ 2.200000] [ 4] [ ALERT] CPSR: 00000070 SVC SP is 0x80202708 USR SP is 0x802027d0 0x802027d0 - 0x80202708 should be XCPTCONTEXT_SIZE [ 2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 51 [ 2.200000] [ 4] [ ALERT] R0: 00000033 00000000 80202780 00000000 00000000 00000000 00000000 80202710 [ 2.200000] [ 4] [ ALERT] R8: 00000000 00000000 00000000 00000000 00000000 80202710 800039d5 800039b2 [ 2.200000] [ 4] [ ALERT] CPSR: 00000070 [ 2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708 [ 2.200000] [ 4] [ ALERT] R0: 2b 0 80202780 0 0 0 0 80202710 [ 2.200000] [ 4] [ ALERT] R8: 0 0 0 0 0 10843d80 800039d5 10801425 [ 2.200000] [ 4] [ ALERT] CPSR: 00000073 SVC SP is 0x80202708 USR SP is 0x80202710 SP overlap in SVC and USR mode This commit change the default CPU mode to System and ensure the consistency of SP/LR in USR/SYS mode during syscall. Signed-off-by: chao.an <anchao@xiaomi.com>	2022-03-14 19:54:53 +09:00
Xiang Xiao	54e630e14d	arch: Merge up_arch.h into up_internal.h ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-03-14 09:32:17 +02:00
Xiang Xiao	c96c96a399	drivers: Merge the common driver initialization into one place ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-03-13 11:24:48 -03:00
Xiang Xiao	39fb09738d	arch: Move [arm|xtensa]_intstack_[alloc|top] to common header file ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-03-11 23:08:07 +02:00
Xiang Xiao	17d1a48fc9	arch: Remove up_puts prototype from up_inernal.h ... since it's defined in include/nuttx/arch.h now Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-03-11 23:08:07 +02:00
Petro Karashchenko	fc9e2d272e	arch/arm/arm[-a|-r]: fix typos in comments ... Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-03-11 11:08:01 +08:00
Xiang Xiao	29cb85ba17	arch/stm32: Fix compiler warning ... chip/stm32_i2s.c:1949:12: error: conflicting types for built-in function 'roundf'; expected 'float(float)' [-Werror=builtin-declaration-mismatch] 1949 | static int roundf(float num) | ^~~~~~ Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-03-10 19:46:01 +02:00
Xiang Xiao	a07dc2363e	c5471/c5471_irq.c: Fix error: '__builtin_memcpy' forming offset [4, 31] is out of the bounds [0, 4] of object '_svectors' with type 'int' ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-03-10 19:46:01 +02:00
Huang Qi	69cfe8d626	arch/arm: Support setjmp/longjmp for all socs ... After check the official specification of ARM ISA and Thumb ISA, the arch_setjmp_thumb.S are written by arm unified assembly language, so it easy to make it works for ARM and thumb ISA. Signed-off-by: Huang Qi <huangqi3@xiaomi.com>	2022-03-09 17:13:21 +02:00
Richard Tucker	4888be37e3	arch/arm/src/sam34/sam_dmac.c: Fix compilation error	2022-03-09 10:18:32 +08:00
Huang Qi	bfedbf1c05	arm/imx6: Enable setjmp test in ostest ... Signed-off-by: Huang Qi <huangqi3@xiaomi.com>	2022-03-08 21:00:29 +08:00
Huang Qi	cfff115f21	arm: Move setjmp to common place ... Since some Cortex A core supports thumb mode also, thus they can share same implementation. Signed-off-by: Huang Qi <huangqi3@xiaomi.com>	2022-03-08 21:00:29 +08:00
Juha Niskanen	779665c704	arch/arm/src/stm32l4: STM32L4+ might need flash data cache corruption workaround ... Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>	2022-03-04 14:00:20 +08:00
Oleg Evseev	625d230d28	arch/arm/src/stm32f7/stm32_can.c: fix CAN3 receiving ... by fixing filter initialization. STM32F7 CAN3 works in single peripheral configuration and there is only 14 filter banks: 0-13. Previously not available 14 indexed filter (CAN_NFILTERS/2) was wrongly used for for receiving to FIFO. Now zero indexed filter is correctly used instead.	2022-03-03 14:31:37 -03:00
zhuyanlin	5af1b671b6	armv7-a/armv7-r:cache: modify hardcode in cache set/way operation ... Some chip not use the default cache size & way , read from CCSIDR instead of hardcode. Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2022-03-03 14:11:31 +08:00
Masayuki Ishikawa	2a434fe1fa	arch: imx6: Add the pgheap for imx6 ... Summary: - This commit adds the pgheap for imx6 Impact: - None Testing: - Tested with sabre-6quad:netknsh (not merged yet) Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>	2022-03-01 12:18:47 +08:00
Xiang Xiao	da954956e7	Simplify DEFAULT_SMALL usage in Kconfig ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-03-01 03:15:01 +08:00
chao.an	0961f12e28	arm/phy62xx: remove unused private header ... Signed-off-by: chao.an <anchao@xiaomi.com>	2022-03-01 00:33:58 +08:00
Masayuki Ishikawa	56e0e6a5ec	arch: imx6: Remove sem_t from imx_serial.c ... Summary: - I noticed that when exiting getprime, DEBUGASSERT happens in nxsem_wait() - Finally, I found that up_putc() uses nxsem_wait() - This commit fixes this issue by removing the semaphore. - Also, up_putc() now calls imx_lowputc() Impact: - None Testing: - Tested with sabre-6quad:netknsh (not merged yet) Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>	2022-02-28 16:09:01 +08:00
Masayuki Ishikawa	a75d905760	arch: imx6: Refactor imx_lowputc() ... Summary: - Remove '\n' -> '\r\n' conversion - Remove waiting for FIFO empty after sending a character - Remove CONFIG_DEBUG_FEATURES Impact: - None Testing: - Tested with sabre-6quad:netknsh (not merged yet) Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>	2022-02-28 16:09:01 +08:00
Xiang Xiao	872c570343	arch: Align the implementation of stack related functions ... arm: Avoid call k[u]mm_memalign to save the code size ceva: Correct stack_base_ptr usage(top of stack v.s. bottom of stack) mips: Correct the stack alignment in up_use_stack misoc: Correct the stack alignment in up_use_stack or1k: Correct the stack alignment in up_use_stack Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-02-28 15:05:41 +08:00
Xiang Xiao	3bf416e8b8	arch: Move STACK_ALIGNMENT definition to up_internal.h ... to avoid the same macro duplicate to many place Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-02-28 15:05:41 +08:00
Xiang Xiao	44bd3212d4	arch: Remove SYS_RESERVED from Kconfg ... let's arch define the correct value instead Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-02-27 22:54:13 +08:00
Xiang Xiao	087b9e5ff3	arch: Move the content from svcall.h to syscall.h ... and remove svcall.h Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-02-27 22:54:13 +08:00
Xiang Xiao	0c7517e579	arch: Remove the duplicated syscall.h in each arch ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-02-27 22:54:13 +08:00
chao.an	b57e0b6118	arm/armv7-a/r: check ARMV7A_DECODEFIQ on dataabort ... Signed-off-by: chao.an <anchao@xiaomi.com>	2022-02-27 17:25:22 +09:00
chao.an	c369e47107	arm/armv7-a/r: handle swi on interrupt stack ... Signed-off-by: chao.an <anchao@xiaomi.com>	2022-02-27 17:25:22 +09:00
lp.xiao	fac10b6ebd	stm32f103re has a dac module.but the pinmap file has no corresponding definition	2022-02-27 14:39:17 +08:00
Xiang Xiao	b95022f8de	arm/armv7-a: Remove CONFIG_SMP guard from arm_scu.c ... since ACTLR.SMP need enable to make cache work on Cortex A7: https://developer.arm.com/documentation/ddi0464/f/CHDBIEIF Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-02-26 14:15:30 +09:00
Masayuki Ishikawa	de95a8550f	arch, board: Add thumb support to i.MX6 ... Summary: - This commit adds thumb support to i.MX6 - Also, applies the same coding style to arch_elf.c Impact: - i.MX6 only Testing: - Tested with sabre-6quad:smp (QEMU, Dev board) - Tested with sabre-6quad:netnsh (QEMU) - Tested with sabre-6quad:netknsh (QEMU, not merged yet) Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>	2022-02-25 10:51:12 +08:00
Xiang Xiao	25213c42a5	arch/arm: Remove the empty spinlock.h file ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-02-25 09:18:53 +09:00
Anton Potapov	9603b8f67c	Add DAC2 configuration for stm32f405.	2022-02-24 12:09:41 -05:00
Xiang Xiao	d7fe0127b0	Replece clock_gettime(CLOCK_REALTIME) with clock_systime_timespec if suitable ... it's better to call the kernrel api insteaad user space api in kernel Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-02-24 01:06:36 +08:00