Commit Graph

22056 Commits

Author SHA1 Message Date
Xu Xingliang
b09b429308 arch/arm64: use serr for error log
Signed-off-by: Xu Xingliang <xuxingliang@xiaomi.com>
2024-06-18 09:44:26 -03:00
Yanfeng Liu
28ae3b3849 arch/risc-v: revise MMIO for rv64ilp32
This revises `getregXX` and `setregXX` for rv64ilp32 to overcome
the limitation of compiler generated addresses and reach devices
in a larger range.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-06-18 10:50:49 +08:00
Stuart Ianna
66df96e384 arch/risc-v/include/elf.f: Support coredump for rv32 and rv64 targets.
Adds the missing elf_gregset_t type definition so pr_regs field can be
resolved. Coredumps can be produced for both 32 and 64 bit targets.
2024-06-18 10:41:56 +08:00
Nicolas Lemblé
50fadb93f2 arch/xmc4 uart driver fix 2024-06-18 00:17:07 +08:00
Lup Yuen Lee
008803865f boards/risc-v: Add support for Milk-V Duo S SBC (SOPHGO SG2000 SoC)
This PR adds support for Milk-V Duo S 64-bit RISC-V SBC, based on SOPHGO SG2000 SoC (T-Head C906 Core). Most of the code is derived from NuttX for Ox64 BL808. The source files are explained in the articles here: https://github.com/lupyuen/nuttx-sg2000

Modified Files:

`boards/Kconfig`: Added Milk-V Duo S board

`arch/risc-v/src/sg2000/sg2000_timerisr.c`: Fixed MTIMER_FREQ for sleep() to work correctly

New Files in boards/risc-v/sg2000/milkv_duos:

`src/sg2000_appinit.c`: Startup Code

`include/board.h`: Milk-V Duo S Definitions

`include/board_memorymap.h`: Memory Map

`src/etc/init.d/rc.sysinit`, `rcS`: Startup Script

`src/.gitignore`: Ignore the tmp filesystem

`scripts/ld.script`: Linker Script

`scripts/Make.defs`: Milk-V Duo S Makefile

`src/Makefile`: Milk-V Duo S Makefile

`Kconfig`: Milk-V Duo S Config

`configs/nsh/defconfig`: Build Config for `milkv_duos:nsh`

Updated Documentation:

`platforms/risc-v/sg2000/index.rst`: New page for SOPHGO SG2000 SoC

`platforms/risc-v/sg2000/boards/milkv_duos/index.rst`: Building and booting NuttX for Milk-V Duo S
2024-06-18 00:13:35 +08:00
Lee Lup Yuen
8e30c13441 arch/risc-v: Add support for SOPHGO SG2000 SoC (T-Head C906)
This PR adds support for the SOPHGO SG2000 SoC, based on T-Head C906 64-bit RISC-V Core. This will be used by the upcoming port of NuttX for Milk-V Duo S SBC.

Most of the code was derived from NuttX for Ox64 BL808. The source files are explained in the articles here: https://github.com/lupyuen/nuttx-sg2000

Modified Files in arch/risc-v:

`Kconfig`: Added ARCH_CHIP_SG2000 for SG2000 SoC

New Files in arch/risc-v:

`include/sg2000/chip.h`: SG2000 Definitions

`include/sg2000/irq.h`: External Interrupts

`src/sg2000/chip.h`: Interrupt Stack Macro

`src/sg2000/sg2000_allocateheap.c`: Kernel Heap

`src/sg2000/sg2000_head.S`: Linux Header and Boot Code

`src/sg2000/sg2000_irq.c`: Configure Interrupts

`src/sg2000/sg2000_irq_dispatch.c`: Dispatch Interrupts

`src/sg2000/sg2000_memorymap.h`: Memory Map

`src/sg2000/sg2000_mm_init.c`, `sg2000_mm_init.h`: Memory Mgmt

`src/sg2000/sg2000_pgalloc.c`: Page Allocator

`src/sg2000/sg2000_start.c`: Startup Code

`src/sg2000/sg2000_timerisr.c`: Timer Interrupt

`src/sg2000/hardware/sg2000_memorymap.h`: PLIC and UART Base Address

`src/sg2000/hardware/sg2000_plic.h`: PLIC Register Addresses

`src/sg2000/Kconfig`: SG2000 Config

`src/sg2000/Make.defs`: Makefile
2024-06-17 09:41:29 +08:00
Devansh Purohit
16d14218fc ESP32S3 bootloader.mk file has a typo error. In the file CONFIG_ESP32S2_MCUBOOT_VERSION config variable is declared, while the correct config variable for esp32s3 bootloader.mk file is CONFIG_ESP32S3_MCUBOOT_VERSION which is defined in the .config file when the config is generated for ESP32S3-devkit board. 2024-06-16 23:36:54 +08:00
Inochi Amaoto
e37348aeba arch/risc-v: Add support for S-mode flat build
There is no need to use kernel build for S-mode all the time. As cpu
scratch is supported for non kernel mode build, it is possible to use
flat build for S-mode.

Add flat build support for risc-v S mode.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-06-14 19:52:00 +08:00
Yanfeng Liu
8ebc3aa9e8 arch/risc-v: initial qemu-rv64ilp32 support
This applies uintreg_t in risc-v commons and fixes araised ci issues
for multiple devices. The FLAT build runs on qemu-rv64ilp32 target.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-06-14 19:50:00 +08:00
Yanfeng Liu
33afbaadb9 arch/risc-v: add rv64ilp32 toolchain
This adds support of rv64ilp32 toolchain available from Github repo
`ruyisdk/riscv-gnu-toolchain-rv64ilp32`. With this 32-bit nuttx can
be generated for RV64 devices.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-06-14 19:50:00 +08:00
Neale Ferguson
73b15a87dc Fix SHMODULEFLAGS so that we link dynamically correctly
* arch/risc-v/src/common/Toolchain.defs
  arch/xtensa/src/lx6/Toolchain.defs
  arch/xtensa/src/lx7/Toolchain.defs
  - Define SHMODULEFLAGS etc. for sotest/dynload
  - Add --entry=__start to SHMODULEFLAGS

* boards/arm64/qemu/qemu-armv8a/scripts/Make.defs
  boards/sim/sim/sim/scripts/Make.defs
  - Define SHMODULEFLAGS etc. for sotest/dynload
2024-06-12 23:21:16 -03:00
Neale Ferguson
5033966d8c Add flags for building shared objects for architectures supporting dynamic loading
* arch/arm/src/common/Toolchain.defs
  arch/risc-v/src/common/Toolchain.defs
  boards/sim/sim/sim/scripts/Make.defs
  - Add SHCCFLAGS and SSHLDFLAGS
2024-06-12 23:21:16 -03:00
Eren Terzioglu
0cf7676aca esp32[c3|c6|h2]: Add SPI Slave support 2024-06-12 22:53:19 -03:00
chao an
04eeef06a7 arch/tricore: update the function prototype as mainline
Signed-off-by: chao an <anchao@lixiang.com>
2024-06-12 23:36:11 +08:00
Eren Terzioglu
62af2993a4 esp32h2: Change delimiter constant with variable 2024-06-12 23:35:24 +08:00
Eren Terzioglu
99ea8b7832 esp32[c3|c6|h2]: Add gspi master support 2024-06-12 23:35:24 +08:00
jfbblue0922
73949ac223 add stm32h755II chip 2024-06-12 16:22:52 +08:00
Tiago Medicci Serrano
6c3eeb7d5c espressif: Remove outdated config about IDF bootloader
For newer devices, IDF bootloader is not supported because the
devices are able to boot directly into NuttX or use MCUBoot to
enable OTA and security features.
2024-06-12 16:11:56 +08:00
Tiago Medicci Serrano
480ad6b631 esp: Make the legacy bootloader (IDF bootloader) option visible
This commit enables users to select the legacy bootloader (IDF
bootloader) in `menuconfig` directly. Please note, that this is a
legacy option intended to support devices already deployed and it
isn't recommended for new designs.
2024-06-12 16:11:56 +08:00
adriendesp
6f49637e23 Added xmc4_vadc.c to Make.defs 2024-06-11 20:19:49 +08:00
Matheus Catarino
c6eea4ad8b add LDC2 (dlang) support
*Note:* ldmd2 is ldc2-wrapper, allow using dmd frontend flags.
      This support may be extended to gdc (gnu) if nuttx developers demand it
  or are interested in it.
2024-06-06 09:32:56 +08:00
Jani Paalijarvi
b32a1dfd3d risc-v/mpfs: Add error handling for PMP conf
Check return value of mpfs_board_pmp_setup() and
jump to mpfs_board_pmp_error() in case of error.

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2024-06-05 12:07:02 -03:00
Takuya Miyashita
072890c1bf arch/arm/src/armv7-m/arm_vectors.c : Add the address alignment.
Add the address alignment to keep the constraint of ARMv7-M architecture same as RAM vector.

ARMv7-M architecture describes the vector table address alignment as following.
The Vector table must be naturally aligned to a power of two
whose alignment value is greater than or equal to (Number of Exceptions supported x 4),
with a minimum alignment of 128 bytes.

I wonder why the implementation of arm_vectors.c does not follow
this constraint of address alignment about ARMv7-M architecture.
Although RAM vector is taken care about it.

I think, as the result it was done by linker script on each board.
At our system, NuttX will be started by bootloader.
To fix the address of entry point(__start) I set the address of entry point to beginning of binary,
so the beginning of binary is not a vector table.
At this case, keeping the address alignment constraint of arm_vectors.c is needed.
2024-06-05 21:47:57 +08:00
Almir Okato
4178f3ede4 esp32s2: remove legacy bootloader support
Deprecate Legacy Boot for ESP32-S2.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2024-06-04 18:53:14 -03:00
Almir Okato
16f8966fa9 esp32s2: add simple boot support
The Simple Boot feature for Espressif chips is a method of booting
that doesn't depend on a 2nd stage bootloader. Its not the
intention to replace a 2nd stage bootloader such as MCUboot and
ESP-IDF bootloader, but to have a minimal and straight-forward way
of booting, and also simplify the building.

This commit also removes deprecated code and makes this bootloader
configuration as default for esp32s2 targets and removes the need
for running 'make bootloader' command for it.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2024-06-04 18:53:14 -03:00
Eren Terzioglu
24af23e49c esp32[c3]: Add XTWDT support 2024-06-04 17:42:07 -03:00
Takuya Miyashita
146975d069 arch: cxd32xx: Add cxd32xx SoC support
Supported drivers
 - Serial(PL011), Timer, NVIC
2024-06-04 22:21:56 +08:00
adriendesp
6f50847278 arch/xmc4 Add partial vadc support : Background request source 2024-06-04 09:42:54 -03:00
liqinhui
45fc68e904 sim/net: Support to set the MTU of the sim netdevice.
Signed-off-by: liqinhui <liqinhui@xiaomi.com>
2024-06-02 09:31:37 -03:00
Stuart Ianna
e3056c781e arch/risc-v/riscv_mtimer: Update the mtimecmp value once per interrupt event.
Cache the next timeout value in the drivers instance and update the mtimecmp value once. This is advantageous as the opensbi ecall to set the timer is expensive in systems which don't have the supervisor mode timer extension.
2024-06-02 09:28:19 -03:00
raiden00pl
37b3dc11a5 Kconfig: move LTO options to Build Setup menu
LTO is optimization option so it's more appropriate to place it
in the same place as other optimization options
2024-06-02 09:26:35 -03:00
Ville Juven
e6973c764c riscv/syscall: Optimize user service call performance
This patch changes how user service calls are executed:
Instead of using the common interrupt logic, execute the user service
call directly.

Why? When a user makes a service call request, all of the service call
parameters are already loaded into the correct registers, thus it makes
no sense to first clobber them and then reload them, which is what the
old logic does. It is much more effective to run the system call directly.

During a user system call the interrupts must be re-enabled, which the
new logic does as soon as we know the exception is a user service call
request.

This patch does NOT change the behavior of reserved system calls (like
switch_context), only the user service call request is affected.
2024-06-01 10:40:53 -03:00
Ville Juven
a5574d9485 risc-v_percpu: Add TCB to the per CPU structure
Also, convert the type to union; we don't need the list element once
the item has been popped from the free list (the linkage is never needed
when the item is in use).
2024-06-01 10:40:53 -03:00
Ville Juven
6bad48e4c7 riscv_syscall.S: Remove duplicated code
Return from exception is common code for both system calls and
exceptions
2024-06-01 10:40:53 -03:00
Jouni Ukkonen
a5cd1cf89b imx9: map flexspi peripheral interface
Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-05-31 10:22:27 +08:00
Jouni Ukkonen
8382916d26 Map iMX93 OCRAM memory to mmu
Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-05-31 10:22:27 +08:00
Jouni Ukkonen
e8de8cf60a Add S3MUA base address for Security Enclave
Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-05-31 10:22:27 +08:00
Stuart Ianna
1f02c05c6d arch/litex/litex_arch_alarm: Support tickless schedular with arch alarm.
This provides an alternate tickless scheduling method, which uses the riscv
mtimer as a timebase, allowing the time and timeh registers to used
throughout an application.

The exiting tickless method, using Litex's timer0 has been left in place, as
it is a more performant option, but currently has the potential issue
identified in #11189.
2024-05-31 10:21:44 +08:00
Ville Juven
c1f3245167 riscv-v/fork.S: Fix clobbering of s0 in fork()
Value of s0 (callee-saved) must be preserved through the call, use
a0 (caller-saved) to calculate the original SP instead.
2024-05-31 02:29:48 +08:00
xuxin19
275ec7102c cmake:bugfix CMake compilation options settings should not use strings
when repeatedly enabling and disabling string-controlled configurations,
the generated toolchain configuration may be incorrect.

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-05-30 10:02:10 -03:00
simbit18
fde641fac9 Fix Kconfig style
correct block name board
Remove extra TABs
Add comments
2024-05-29 17:15:57 -03:00
hujun5
c06c10f6f3 armv6/7/8-m: use ISB instruction immediately after the MSR instruction
when changing the stack pointer, software must use an
ISB instruction immediately after the MSR instruction.
This ensures that instructions after the ISB instruction
execute using the new stack pointer.

https://developer.arm.com/documentation/101928/0101/The-Cortex-M85-Processor--Reference-Material/Programmer-s-model/Core-registers/CONTROL-register?lang=en

" When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction. This ensures that instructions after the ISB instruction execute using the new stack pointer."

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-05-29 14:16:55 -03:00
Michal Lenc
649ccb2d45 samv7: add support for user signature area in embedded flash
Embedded flash can have user signature area on SAMv7. This is a 512
bytes large page whose data are not erased by asserting ERASE pin or by
software ERASE command.

This commit adds arch to board interface for this area. It is possible
to perform read, write and erase operation. SAMV7_USER_SIGNATURE option
has to be set in the configuration.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-05-28 16:28:33 -03:00
David Sidrane
e0396327a2 armv7-r:MPU fix CONFIG naming to include ARM 2024-05-25 12:06:52 +08:00
David Sidrane
602e69a810 armv8-m:MPU fix CONFIG naming to include ARM 2024-05-25 12:06:52 +08:00
David Sidrane
53307ea9b2 armv7-m:MPU fix CONFIG naming to include ARM 2024-05-25 12:06:52 +08:00
Jani Paalijarvi
cfa544357e mpfs_mpu: Check that size is valid for MPUCFG
The size must be power-of-two for NAPOT according to the the PMP spec.

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2024-05-24 21:32:55 +08:00
Jani Paalijarvi
9d4bd915eb riscv_pmp.c: Check that size is power of two for NAPOT
The size must be power-of-two according to the the PMP spec.

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2024-05-24 21:32:55 +08:00
YAMAMOTO Takashi
b3513c0811 esp32s2/esp32s3 textheap: do not require RTC heap
Unlike esp32, kmm memory is executable.
2024-05-24 21:31:42 +08:00
dongjiuzhu1
00cf0ada4f Revert "arch/sim: temporary remove vfork test to fix cibreak on arch sim"
This reverts commit 8e9f24e02e.
2024-05-24 15:41:20 +08:00
Eren Terzioglu
ea9eea4096 esp32[c3|c6|h2]: Add MWDT1 support 2024-05-24 13:59:03 +08:00
Eren Terzioglu
aa0bb55529 esp32[c3|c6|h2]: Add RWDT support 2024-05-24 13:59:03 +08:00
Eren Terzioglu
44e118eaf2 esp32[c3]: Add RTC IRQ support 2024-05-24 13:59:03 +08:00
Petro Karashchenko
d144a2a80b arch/arm/samv7: enforce compilation error for incompatible configuration options
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-05-23 15:16:00 +08:00
Petro Karashchenko
357f8093ac arch/arm/samv7: fix U(S)ART clock enable for 1-wire
By default U(S)ART clocks are enabled in sam_lowput.c but
configuration check from sam_config.h may override USART configuration
and prevent clocks from been enabled.

This commit fix inconsistency in U(S)ART pinmux and clock configuration

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-05-23 15:15:46 +08:00
Petro Karashchenko
59a23768c5 arch/arm/samv7: remove duplicated prototypes
sam_lowputc.h is almost identical to sam_start.h so remove
one of the headers

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-05-23 15:15:21 +08:00
Yanfeng Liu
f8749ef0e0 arch/risc-v: guard tcb->name usage
Add guard for tcb->name field usage as it is not always available.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-05-22 19:06:07 +08:00
Yanfeng Liu
7db71c8ee4 ci/riscv: fix unused var in esp_twai.c
This is to fix issue in [this log](https://github.com/apache/nuttx/actions/runs/9173629303/job/25222879619):

```
Configuration/Tool: esp32c3-generic/twai esp32c6-devkitm/twai esp32c6-devkitc/twai  esp32h2-devkit/twai
Error: common/espressif/esp_twai.c:242:7: error: variable 'ret' set but not used [-Werror=unused-but-set-variable]
```

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-05-22 16:40:13 +08:00
Eero Nurkkala
2f753a48c7 arm64: s/ARCH_BOOT_EL3/ARCH_ARM64_EXCEPTION_LEVEL/g
Search and replace ARCH_BOOT_EL3 with more generic
ARCH_ARM64_EXCEPTION_LEVEL that holds the EL level
in an integer variable.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-05-21 09:02:35 +08:00
Eero Nurkkala
1d3ce6b527 arm64/imx9: provide EL3 bootloader support for iMX9
This provides a capable bootloader that may be run from OCRAM.
The OCRAM contains regions that are always zero, so the linker
file avoids those with best effort.

iMX9 infrastructure expects:
  - 0x20480000 (Start of OCRAM, AHAB)
  - 0x2049a000 (NuttX or SPL)
  - 0x204e0000 (ARM Trustzone, not used)

When started from SD-card, the offsets are:
  - 0x1f000 with AHAB
  - 0xa000  without AHAB

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-05-21 09:02:35 +08:00
Eero Nurkkala
1c308296a1 arm64: provide EL3 interrupt support via FIQs
Value 1021, when read from ICC_IAR0_EL1 means:

"The GIC returns this value in response to a read of ICC_IAR0_EL1 or ICC_HPPIR0_EL1 at EL3,
to indicate that the interrupt being acknowledged is one which is expected to be handled at
Non-secure EL1 or EL2. This INTID is only returned when the PE is executing at EL3 using
AArch64 state, or when the PE is executing in AArch32 state in Monitor mode."

When this happens:
  - FIQ is fired on group0
  - IRQ is pending at group1

So simply check and handle the interrupt. In short, this provides interrupt support for
EL3.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-05-21 09:02:35 +08:00
Eero Nurkkala
505f57dd00 arm64: introduce MMU support for EL3
Currently MMU supports only EL1.  Introduce EL3 support as well.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-05-21 09:02:35 +08:00
Eero Nurkkala
0f9a262311 arm64: provide EL3 support
This provides means to run NuttX completely in EL3.  This may
be useful with NuttX based bootloaders that are executed from
OCRAM.  Instead of SPL/U-boot combo, NuttX may replace SPL
completely.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-05-21 09:02:35 +08:00
Eero Nurkkala
ae00569ef9 imx9_clockconfig: fix a thinko
putreg32() arguments were swapped.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-05-21 09:02:35 +08:00
YAMAMOTO Takashi
1ee279c292 nuttx kconfig: rename a few recently-added options
from:
ARCH_TEXT_HEAP_SEPARATE_DATA_ADDRESS
ARCH_TEXT_HEAP_WORD_ALIGNED_READ

to:
ARCH_HAVE_TEXT_HEAP_SEPARATE_DATA_ADDRESS
ARCH_HAVE_TEXT_HEAP_WORD_ALIGNED_READ
2024-05-21 01:11:44 +08:00
YAMAMOTO Takashi
d196f800b0 Add a few optional text heap APIs to support esp32s3
esp32s3's Internal SRAM 1 and External Memory have two separate mappings
for instructions and data.
2024-05-21 01:11:44 +08:00
dongjiuzhu1
8e9f24e02e arch/sim: temporary remove vfork test to fix cibreak on arch sim
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
2024-05-20 12:00:39 +08:00
yinshengkai
20ebe0e64c Replace all asserts in kernel code with ASSERT
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-05-17 10:18:16 -03:00
jfbblue0922
72c1f779d1 add stm32h755II chip 2024-05-17 10:16:39 -03:00
Tiago Medicci Serrano
a00fbbeb9f espressif: Add option to disable the GIT_DEPTH to pull submodules
By default, submodules are cloned with `--depth=1`. This continues
to be true if `DISABLE_GIT_DEPTH` environment variable is not
defined (and it is not defined by default). But, if defined the
submodules will be fully cloned (without the `--depth` parameter).
2024-05-17 19:10:46 +08:00
Peter van der Perk
015e7cd607 imxrt: 1170 MPU config ensure no lockups can occur 2024-05-17 19:09:09 +08:00
simbit18
fb31f06a2f Fix Kconfig style
Remove spaces from Kconfig files
Add TABs
Replace help => ---help---
Add comments
2024-05-17 19:06:11 +08:00
Jukka Laitinen
9257af55f1 risc-v/mpfs: Change linker symbols _ssbi_ddr and _esbi_ddr into _ssbi_ram and _esbi_ram
The original names are confusing; the symbols' addresses point to the start and end of the
sbi executable ram area. This may also reside in l2lim and not in ddr, depending on the
configuration, and this is defined in the linker script.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-05-16 17:14:43 -03:00
Rdk-T
63294c5da2 add Port selection on xmc4800
Base ecat option on chip instead of board (allow custom boards to use the ecat)

add GPIO_ECAT alternative configs
2024-05-15 11:57:57 -03:00
yangsen5
33b5e1414c arch/sim_encoder: g_bufsize initialization error in g_sim_encoder_ops structure
Signed-off-by: yangsen5 <yangsen5@xiaomi.com>
2024-05-15 22:03:18 +08:00
yangsen5
d6b7d782eb arch/sim_hostencoder: To avoid system calls being interrupted when use host api
Signed-off-by: yangsen5 <yangsen5@xiaomi.com>
2024-05-15 22:03:18 +08:00
shizhenghui
932cdf228b Add v4l2m2m sim encoder
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-05-15 22:03:18 +08:00
shizhenghui
ed1ad1be65 Add v4l2m2m & sim decoder
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-05-15 22:03:18 +08:00
YAMAMOTO Takashi
5df4925672 esp32s3_textheap.c: fix range checks
While there constants are commented as "First and last words of the
D/IRAM region", the _HIGH addresses are actually not in the corresponding
region.
2024-05-15 10:45:10 -03:00
Gao Feng
10c8c39426 xtensa/esp32s3: pending interrupt should be clear while disable GPIO IRQ 2024-05-15 10:36:04 -03:00
hujun5
6c1b900e82 arm64: optimise for arm64_switchcontext
We can save execution time by
       inline arm64_fullcontextrestore and arm64_switchcontext

test:
We can use qemu for testing.

compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-05-14 16:03:08 -03:00
Tiago Medicci Serrano
8a37d1ff1c espressif: Minor changes to keep consistency between sources
This commits replicates some changes on files that were originally
written for other Espressif SoCs and inspired new implementations.
Eventually, these new implementations were improved and this commit
replicates these changes on the original sources.
2024-05-14 22:10:45 +08:00
Tiago Medicci Serrano
c412dadcb9 esp32c3/wifi: Add support for the Wi-Fi in ESP32-C3
This commit introduces support for both station and softAP modes.
2024-05-14 22:10:45 +08:00
Tiago Medicci Serrano
7ed64e7234 esp32c3: Substitute / to $(DELIM)
Substitute `/` to `$(DELIM)` to make it compatible with other
implementations.
2024-05-14 22:10:45 +08:00
Tiago Medicci Serrano
2c4963dcd6 esp32c6/wifi: Add support for the Wi-Fi in ESP32-C6
This commit introduces support for both station and softAP modes.
2024-05-14 22:10:45 +08:00
Tiago Medicci Serrano
9e8c9ea47f esp: Update libc stubs to properly acquire/release locks.
Avoid using static mutex and recursive mutex as the resource to be
acquired/release. Instead, create a specific lock for each call if
it does not exist.
2024-05-14 22:10:45 +08:00
Tiago Medicci Serrano
47b0cae778 esp/hr_timer: Fix issue with timed-out timers 2024-05-14 22:10:45 +08:00
simbit18
d1789d84e8 fix nxstyle
fix Relative file path does not match actual file.
2024-05-13 22:24:36 +02:00
YAMAMOTO Takashi
3a4560ed40 esp32s3: make textheap return i-bus address consistently
Perform I-D translation for extram as well.

Also, use macros from soc.h.
2024-05-14 00:30:21 +08:00
YAMAMOTO Takashi
ab7805062d esp32s3/esp32s2: Fix D_I_BUS_OFFSET
It seems like a wrong copy-and-paste from esp32c3.
Actually, internal memory mapping varies among processors.

esp32s3: lightly tested with wamr aot
esp32s2: not tested (i have no hardware access)
2024-05-13 18:12:21 +08:00
Inochi Amaoto
4d2d9ecf39 arch/risc-v: fix idle stack assign order
The bc022f8cd8 introduces a static way to calculate idle stack
address for risc-v platform. However, it uses the reverse order
to access idle stack, which breaks boards with smp configuration.

Correct the idle stack order of g_cpux_idlestack.

Fixes: bc022f8cd8 ("arch/risc-v: unify idle stack calculation")
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-05-12 15:22:50 +09:00
Inochi Amaoto
bc022f8cd8 arch/risc-v: remove g_cpux_idlestack
As all the board allocate idle stack from _ebss. The idle stack
layout is fix and can be computed directly by using _ebss. There
is no need to use g_cpux_idlestack array anymore, remove it.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-05-11 17:57:59 +02:00
Inochi Amaoto
afb5a66847 arch/risc-v: unify idle stack calculation
As the stack layout is unified, it is possible to
use a unify formula to calculate the top of idle
stack.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-05-11 17:57:59 +02:00
simbit18
09bfaa7292 fix nxstyle
fix Relative file path does not match actual file.
2024-05-11 01:19:06 +08:00
Peter van der Perk
a8f81e4051 imxrt: lpuart singlewire transfer support 2024-05-10 20:00:24 +08:00
Tiago Medicci Serrano
bc4a020146 Revert "esp32s3: give ESP32S3_APP_FORMAT_LEGACY a prompt"
This reverts commit 2295fa818d.
2024-05-10 01:44:02 +08:00
hujun5
ace5dde1a9 arm/imx6: we use spin_lock_irqsave replace enter_critical_section to protect gpio init
,because enter_critical_section may be called before os initialized

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-05-09 13:45:02 +08:00
hujun5
5cee996588 up_putc: int up_putc, enter_critical_section may be called
before kernel has been iniitialized,we use spin_lock_irqsave to replace.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-05-09 13:45:02 +08:00
hujun5
e187dbd663 chip/s698pm_cpustart.c: Fix compile error
chip/s698pm_cpustart.c: In function 's698pm_cpu_boot':
Error: chip/s698pm_cpustart.c:74:17: error: unused variable 'tcb' [-Werror=unused-variable]
   struct tcb_s *tcb = this_task();
                 ^~~
cc1: all warnings being treated as errors
make[1]: *** [Makefile:99: s698pm_cpustart.o] Error 1
make[1]: Target 'libarch.a' not remade because of errors.
make: *** [tools/LibTargets.mk:164: arch/sparc/src/libarch.a] Error 2
make: Target 'all' not remade because of errors.
/github/workspace/sources/nuttx/tools/testbuild.sh: line 370: /github/workspace/sources/nuttx/../nuttx/nuttx.manifest: No such file or directory
  Normalize s698pm-dkit/smp

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-05-09 01:39:47 +08:00
Pressl, Štěpán
297b3b0209 arch/arm/src/samv7/sam_pwm.c: option to make channels synchronous
Make channels synchronous (i.e. share the same timebase) with the help
of SAMV7_PWMx_CHy_SYNC defines. All the channels share the same
timebase of channel 0, so this channel must be defined too.

Signed-off-by: Stepan Pressl <pressste@fel.cvut.cz>
2024-05-08 23:45:40 +08:00