Commit Graph

18463 Commits

Author SHA1 Message Date
Gustavo Henrique Nihei
25f2dc2077 risc-v/esp32c3: Enable the creation of encrypted Flash partitions
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-01 20:37:44 +08:00
Gustavo Henrique Nihei
9e5e60ba48 esp32s2/esp32c3: Build MCUboot bootloader with Flash Encryption support 2022-01-01 20:37:44 +08:00
Norman Rasmussen
185de258bf Fix preprocessing directives for uart flow control
commit 58bd873729 had a mix of
`#if defined(X)` and `#ifdef X`, but used `#if X` in its TCSETS ioctl
logic which causes compile warnings.
2021-12-31 18:51:17 +08:00
Dong Heng
c56c58020a risc-v/esp32c3: SPI flash MTD device uses all flash space 2021-12-31 11:40:23 +08:00
Gustavo Henrique Nihei
f130d8b91e xtensa/esp32s2: Remove unavailable support for ROM Basic Console
This feature is only available for ESP32 chips.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-31 00:56:08 +08:00
Gustavo Henrique Nihei
74c02fbadb risc-v/esp32c3: Remove unavailable support for ROM Basic Console
This feature is only available on ESP32 chips.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-31 00:56:08 +08:00
Huang Qi
33df35f003 arch/risc-v: Correct epc adjustment with C ISA
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-30 22:54:17 +09:00
chao.an
736add0fe8 arch/backtrace: correct the skip counter
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-30 16:57:40 +08:00
Gustavo Henrique Nihei
80da9abd6a xtensa/esp32: Move assertions after logging to improve debugging
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-30 12:35:41 +08:00
Gustavo Henrique Nihei
b6addaa4c7 xtensa/esp32: Enable the creation of encrypted Flash partitions
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-30 12:35:41 +08:00
Gustavo Henrique Nihei
340e0c8a8f xtensa/esp32: Build MCUboot bootloader with Flash Encryption support
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-30 12:35:41 +08:00
Jukka Laitinen
3beecbe905 risc-v/mpfs: Add MSSIO GPIO pinmap configuration
Add a pinmap header for mpfs to be able to configure MSSIO GPIOs
This also adds Kconfigs for some different chip/package types of the PolarFire SOC

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2021-12-30 11:49:00 +08:00
Huang Qi
2de22980e5 arch/risc-v: Refine syscall interface
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-30 11:47:42 +08:00
Norman Rasmussen
091322ba4a Add backtrace to risc-v common sources 2021-12-30 01:30:08 +08:00
Xiang Xiao
b92c90ee81 arch/arm: Fix rebase error in arm_backtrace_thumb.c
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-29 20:42:05 +08:00
Huang Qi
c15195b126 arch/risc-v: Refine riscv_testset.S
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-29 06:06:01 -06:00
Xiang Xiao
228442ee23 arch/renesas: Undefine macro B0 to avoid the confliction
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-29 08:11:08 -03:00
Huang Qi
901361be48 arch/risc-v: Move more files to common
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-29 01:19:30 -06:00
Huang Qi
22ae2e0121 arch/risc-v: Refine riscv_fpu.S
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-29 01:19:30 -06:00
ChenWen
6ce335fa84 xtensa/esp32: Fix some Wi-Fi issues
1. Fix the issue that Wi-Fi can't connect to some special routers occasionally.
    2. Update Wi-Fi driver code to fix issue of failure to send pkt.
    3. Replace software random with hardware random
2021-12-28 23:48:25 -06:00
chao.an
7ed0b97414 make/allsyms: skip the unnecessary link operation
For incremental compilation, skip the stage 1 dummy link
operation if nuttx elf has been generated

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-28 23:47:10 -06:00
Xiang Xiao
186ac17f1f arch: Select ARCH_HAVE_BACKTRACE in Kconfig for supported arch
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-29 13:34:02 +08:00
Xiang Xiao
dd942f0b04 sched/backtrace: Dump the complete stack regardless the depth
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-29 12:09:54 +08:00
Xiang Xiao
f302e8fd40 arch/sim: Implement up_backtrace
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-29 11:03:08 +08:00
Xiang Xiao
f061766801 video/fb: Fix typo error in include/nuttx/video/fb.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-28 17:21:18 -03:00
Huang Qi
e75321e61c arch/risc-v: Move riscv_blocktask.c to common
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-28 11:32:15 -06:00
Norman Rasmussen
934a79736a Use userspace chosen channel numbers when starting bl602 pwm
commit 2889315c20 added support for pwm
but didn't read the channel numbers provided by user-space. They should
be, otherwise it's not possible to start a sub-set of channels that are
not the first "n" channels.
2021-12-28 06:27:51 -06:00
chao.an
cf2dfa8985 arch/arm/assert: move the arm_assert to common code
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-28 05:09:30 -06:00
Huang Qi
d71cfc178a arch/risc-v: Remove unneeded kconfigs
CONFIG_RV32IM_HW_MULDIV can be safely removed since this behavior is
controlled by M extension.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-28 05:02:42 -06:00
chao.an
579738c8fa arch/arm: move the backtrace implement to common code
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-28 03:02:01 -06:00
Norman Rasmussen
1e2f067181 pwm: add option to break the loops when using multiple PWM channels
commit 7354ab187e added an option to break
the loops when using multiple PWM channels to arm pwm drivers. This adds
the same support to the risc-v pwm drivers.
2021-12-28 03:01:27 -06:00
Huang Qi
c2e8c92b25 arch/risc-v: Refine Toolchain.defs
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-28 00:30:10 -06:00
chao.an
a42aa8415d compile/flags: add FRAME_POINTER into Toolchain.defs
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-27 22:31:27 -06:00
chao.an
8eb999ff03 arch/arm: select ARM_THUMB by default for Cortex-M
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-27 22:30:53 -06:00
Petro Karashchenko
3ccb657dc2 nuttx: remove space befone newline in logs
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-27 21:01:19 -06:00
Huang Qi
0751bcd4ca arch/sim: Support vncserver as display device
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-24 11:59:43 -06:00
Alan C. Assis
01e4e249cc Add WiFi/BLE Coexistence support
Co-authored-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-12-23 20:42:23 -06:00
chao.an
6069433d2d arch/arm/cortex-a/r: dump all registers with alias
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-23 06:54:32 -06:00
Eero Nurkkala
3394dca826 risc-v/opensbi: Make.defs: use a wildcard for file listing
The source directory contents of the OpenSBI directory lib/sbi may be
listed with a one-line wildcard. This makes the Make.defs file look
simpler. The rest of the files need to be picked one at a time.

Co-authored-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-12-23 02:42:09 -06:00
Eero Nurkkala
b128ce334f mpfs: introduce OpenSBI
OpenSBI may be compiled as an external library. OpenSBI commit d249d65
(Dec. 11, 2021) needs to be reverted as it causes memcpy / memcmp to
end up in the wrong section. That issue has yet no known workaround.

OpenSBI may be lauched from the hart0 (e51). It will start the U-Boot
and eventually the Linux kernel on harts 1-4.

OpenSBI, once initialized properly, will trap and handle illegal
instructions (for example, CSR time) and unaligned address accesses
among other things.

Due to size size limitations for the mpfs eNVM area where the NuttX
is located, we actually set up the OpenSBI on its own section which
is in the bottom of the DDR memory. Special care must be taken so that
the kernel doesn't override the OpenSBI. For example, the Linux device
tree may reserve some space from the beginning:

  opensbi_reserved: opensbi@80000000 {
      reg = <0x80000000 0x200000>;
      label = "opensbi-reserved";
  };

The resulting nuttx.bin file is very large, but objcopy is used to
create the final binary images for the regions (eNVM and DDR) using
the nuttx elf file.

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-12-22 20:48:12 -06:00
Eero Nurkkala
491ae6cc53 mpfs: cache: assign ways to L2 zero device
Assign ways to L2 zerodevice. L2 zero device is used for
the scratchpad functionality. The area may be used for the
harts communicating to each other.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-12-22 20:48:12 -06:00
David Sidrane
74e692b3c1 stm32f7:sdmmc invalidate before DMA to avoid eviction overwrite
For FAT the same buffer is used for read and writes, there
  is a possibility a cache line is dirty. But the fs is
  not dirty and will not write the sector to disk. This can
  be seen  https://github.com/PX4/NuttX/pull/175

  When the system is busy that cache line can be evicted after the
  RX DMA has completed and overwrite the data in memory. The solution
  is to invalidate before the DMA to prevent an evection causing an
  overwite, and after the DMA it to insure coherency.
2021-12-22 20:44:04 -06:00
chao.an
fe2830ec94 xtensa: enhance the task dump
add irq stack information
add cpu loading

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-22 11:46:02 -03:00
chao.an
362fe2c6f8 arch/risc-v: enhance the task dump
add irq stack information
add cpu loading

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-22 11:46:02 -03:00
chao.an
a0b61bbf6f arm/cortex-a/r: enhance the task dump
add irq stack information
add cpu loading

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-22 11:46:02 -03:00
Abdelatif Guettouche
4f0dd95fe1 arch/Kconfig: Add HAVE_SYSCALL_HOOKS configs to Xtensa arch.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-12-22 06:26:36 -06:00
Xiang Xiao
b03886415f sim/netdev: Update IFF_RUNNING flag by netdev_carrier_on and netdev_carrier_off
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-22 07:15:00 -03:00
chao.an
2737701996 cortex-m/hardfault: add secure-fault handler
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-21 07:08:13 -06:00
ChenWen
6d165506d5 risc-v/esp32c3: Initialize rtc and peripheral parameters by default when chip starts 2021-12-21 10:03:58 -03:00
Gustavo Henrique Nihei
c471f0fe96 risc-v/esp32c3: Remove deprecated note about Flash Detect feature
Flash Detect option is already available on esptool.py installed via pip

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-21 07:02:40 -06:00