During PSRAM initialization and flash operations, the Cache needs to be disabled.
So all data and code for the aforementioned scope is required to be placed in Internal RAM.
After https://github.com/apache/nuttx/pull/11007/ was merged, the
path for some files changed, requiring the linker to be fixed to
make it run from the internal memory once again.
This commit sets the BLE's interrupt as a IRAM-enabled interrupt,
which enables it to run during a SPI flash operation. This enables
us to create a cache to off-load semaphores and message queues
operations and treat them when the SPI flash operation is finished.
By doing that, we avoid packet losses during a SPI flash operation.
This commit provides an interface to register ISRs that run from
IRAM and keeps track of the non-IRAM interrupts. It enables, for
instance, to avoid disabling all the interrupts during a SPI flash
operation: IRAM-enabled ISRs are, then, able to run during these
operations.
Whenever a SPI flash operation is going to take place, it's
necessary to disable both the instruction and data cache. In order
to avoid the other CPU (if SMP is enabled) to retrieve data from
the SPI flash, it needs to be paused until the current SPI flash
operation finishes. All the code that "pauses" the other CPU (in
fact, the CPU spins until `up_cpu_resume` is called) needs to run
from the instruction RAM.
1) Wi-Fi driver libs from Espressif ESP-IDF release/v5.0;
2) Station mode only;
3) WPA2-PSK and WPA3-SAE enabled;
Not yet supported (WIP):
- SoftAP mode;
- 802.11k, 802.11v and 802.11R;
- Power Save mode;
- BLE Coexistance;
