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18613 Commits

Author SHA1 Message Date
Gustavo Henrique Nihei
1c8e84b341 risc-v/esp32c3: Add Secure Boot support on top of MCUboot 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-12-21 07:02:40 -06:00
Gustavo Henrique Nihei
f542ab4564 xtensa/esp32s2: Add Secure Boot support on top of MCUboot 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-12-21 07:02:40 -06:00
Gustavo Henrique Nihei
d22a2aa7a0 xtensa/esp32: Refactor makefiles for compliance to Function Call Syntax 
According to Make documentation:
- "Commas and unmatched parentheses or braces cannot appear in the text
  of an argument as written";
- "Leading spaces cannot appear in the text of the first argument as
  written".

Although in the current state it was not resulting in parsing issues, it
is better to fix it.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-12-21 07:02:40 -06:00
Gustavo Henrique Nihei
6c3223289f xtensa/esp32: Add Secure Boot support on top of MCUboot 
This adds the capabitlity of building signed images on NuttX.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-12-21 07:02:40 -06:00
Juha Niskanen
54b652235c Update arch/Kconfig 
Co-authored-by: Gustavo Henrique Nihei <38959758+gustavonihei@users.noreply.github.com>
 2021-12-21 03:26:16 -06:00
Juha Niskanen
422ceec99b Fix typos in comments and Kconfig files 
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2021-12-21 03:26:16 -06:00
chao.an
287348475c sim/usrsock: increase the sim usrsock buffer size 
1. Increase the sim usrsock buffer size:
arch/sim/src/sim/up_usrsock.c

2. Fix build break
arch/sim/src/sim/up_usrsock_host.c

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-21 00:53:31 -06:00
Simon Filgis
6cc48ff6ff arch/arm/samv7: initial support for LIN bus communication 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-20 18:23:05 -03:00
Petro Karashchenko
3e76c3266e assert: unify stack and register dump across platforms 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-20 00:02:12 -03:00
Petro Karashchenko
67d8a82393 Kconfig: fix non-string default values uniformity 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-20 00:10:57 +01:00
David Sidrane
e269b5fa28 Revert "stm32h7 sdmmc: set SDMMC_CK pin to high speed (50 MHz) mode. When it was in slow speed mode (by default), the output SDMMC_CK clock rise and fall times were about 13 ns each, that were very slow and prevented some SDIO devices from working." 
This reverts commit 0aecfe8691.
 2021-12-19 01:40:35 -06:00
chao.an
c1c1882783 sim/usrsock: Reuse all addresses to avoid bind fail 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-18 13:15:46 -06:00
raiden00pl
87a8b1bed9 nrf52/Kconfig: NRF52_SDC_LE_CODED_PHY not available for nrf52832 2021-12-18 12:27:59 -06:00
raiden00pl
f3fdd5a019 arch/arm/src/nrf52/Kconfig: select IRQPRIO for SoftDevice 2021-12-18 09:13:36 -06:00
raiden00pl
a6c64795f4 arch/arm/src/nrf52/nrf52_sdc.c: raise error if BT device not selected 2021-12-18 09:13:36 -06:00
raiden00pl
cf2dae8d79 arch/arm/src/nrf52/nrf52_sdc.c: nxstyle fixes 2021-12-17 12:35:17 -06:00
raiden00pl
af143c96fc arch/arm/src/nrf52/nrf52_sdc.c: public device address and static device address support 2021-12-17 12:35:17 -06:00
raiden00pl
c7f6ac63b0 arch/arm/src/nrf52/nrf52_sdc.c: add option to register UART H4 device 2021-12-17 12:35:17 -06:00
raiden00pl
23ef3ea64c arch/arm/src/nrf52/nrf52_sdc.c: remove nedless new lines 2021-12-17 12:35:17 -06:00
raiden00pl
26951f5018 arch/arm/src/nrf52/nrf52_sdc.c: print HCI opcode as hex 2021-12-17 12:35:17 -06:00
raiden00pl
07c9204fd6 arch/arm/src/nrf52/nrf52_sdc.c: fix status byte offset 2021-12-17 12:35:17 -06:00
raiden00pl
ab66800e13 arch/arm/src/nrf52/Kconfig: fix typos 2021-12-17 12:35:17 -06:00
raiden00pl
ba6e8696b2 arch/arm/src/nrf52/hardware/nrf52_ficr.h: add device address types 2021-12-17 12:35:17 -06:00
Jiuzhu Dong
5a22d33475 up_putc: do up_putc when enable CONFIG_ARCH_LOWPUTC 
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-12-17 11:43:08 -06:00
raiden00pl
07d295b8db add 5-Clause Nordic License barrier for Nordic SoftDevice Controller 2021-12-17 11:22:39 -06:00
xiewenxiang
b1d051b651 riscv/esp32c3: Initialize the BLE Mac 2021-12-16 22:31:02 -03:00
Gerson Fernando Budke
2dd5578d50 arch/arm/src/samv7/Kconfig: Define mem sizes 
Current samv7 platform does not define SoC memories sizes. This define
both internal flash and sram memories sizes and update all defconfig
files.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
 2021-12-16 06:56:42 -03:00
Alexander Lunev
0aecfe8691 stm32h7 sdmmc: set SDMMC_CK pin to high speed (50 MHz) mode. 
When it was in slow speed mode (by default), the output SDMMC_CK clock rise and
fall times were about 13 ns each, that were very slow and
prevented some SDIO devices from working.
 2021-12-16 01:28:05 -06:00
chao.an
b11833cbba arch/assert: flush the syslog before stack dump 
flush the syslog before stack dump to avoid buffer overwrite

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-15 12:00:35 -06:00
chao.an
56ef1419dd arch/xtensa: set the current reg before print syslog 
ensure the semantics of the up_interrupt_context() works as expected

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-14 21:40:03 -06:00
chao.an
2fe06ac083 arch: xtensa: save current SP before overwrting 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-14 21:40:03 -06:00
chao.an
93b133fe66 arch/xtensa: correct the interrupt stack on irq handler 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-14 21:40:03 -06:00
Petro Karashchenko
51a2db6ffc Kconfig: improve uniformity 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-14 07:32:48 -06:00
Jiuzhu Dong
6b5a7a73ba sim: add CONFIG_SIM_STACKSIZE_ADJUSTMENT to reduce variability 
between sim and other different platform stack size setting

Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-12-13 21:15:30 -06:00
Petro Karashchenko
af614ac77d tls: restore C89 compatibility for TLS 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-13 21:14:53 -06:00
chao.an
c2fd66bfab arch/arm/risc-v/xtensa: add support of all symbols for debugging 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-13 08:31:13 -06:00
Abdelatif Guettouche
d31a0d8aca arch/xtensa/esp32: Show CPU activity on IDLE task and on interrupts. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-12-13 08:30:58 -06:00
Abdelatif Guettouche
6262f7e99a esp32_idle.c: Change private function's name to start with esp32_ 
instead of up_.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-12-13 08:30:58 -06:00
chao.an
89e2f00dad arch/assert: fix the stack dump overflow 
[ EMERG] kasan_report: kasan detected a read access error, address at 0x3c24fca8, size is 4
[ EMERG] up_assert: Assertion failed at file:kasan/kasan.c line: 104 task: init
[ EMERG] backtrace|10:  0x2c334666 0x2c35f0d6 0x2c359ef6 0x2c35f830 0x2c360ed4 0x2c3615c0 0x2c324e0c 0x2c30a168
[ EMERG] up_registerdump: R0: ffffffff R1: 00000004 R2: ffffffff R3: ffffffff
[ EMERG] up_registerdump: R4: 3c20d4f0 R5: 2c35acd5 R6: 00000000 FP: 3c24fae8
[ EMERG] up_registerdump: R8: 3c20d504 SB: ffffffff SL: 2c413e7c R11: 2c411eb8
[ EMERG] up_registerdump: IP: 00000002 SP: 3c24fae8 LR: 00000003 PC: 2c35f0d6
[ EMERG] up_registerdump: xPSR: 61010000 BASEPRI: 000000e0 CONTROL: 00000004

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-13 01:43:18 -06:00
chao.an
0b7b8d274f arm/cortex-m: enhance the crash dump 
1. add irq stack information to list
2. add cpu loading into list

before:

Idle Task: PID=0 PRI=0 Stack Used=512 of 3048
hpwork: PID=1 PRI=224 Stack Used=304 of 2016
lpwork: PID=2 PRI=100 Stack Used=304 of 2016
rptun: PID=4 PRI=224 Stack Used=856 of 2008

after:

[ EMERG] [ap] up_showtasks:    PID    PRI      USED     STACK   FILLED       CPU   COMMAND
[ EMERG] [ap] up_showtasks:   ----   ----       928      2048    45.3%      ----   irq
[ EMERG] [ap] up_dump_task:      0      0       512      3048    16.7%     99.4%   Idle Task
[ EMERG] [ap] up_dump_task:      1    224       304      2016    15.0%      0.0%   hpwork
[ EMERG] [ap] up_dump_task:      2    100       304      2016    15.0%      0.0%   lpwork
[ EMERG] [ap] up_dump_task:      4    224       856      2008    42.6%      0.0%   rptun

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-12 21:40:29 -06:00
lupyuen
2a87b37a69 riscv/bl602: Swap SPI MISO and MOSI 2021-12-12 20:40:49 -06:00
Huang Qi
8ce3337e85 arch/risc-v: Implement TLS support 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-12 10:19:00 -06:00
Matheus Castello
294694bb2f arch: arm: select LIBC_ARCH_ATOMIC when config ARCH_CHIP_RP2040 
Use the common atomic operations when needed.

Signed-off-by: Matheus Castello <matheus@castello.eng.br>
 2021-12-11 11:32:17 -06:00
Juha Niskanen
a35d205f3b arch/arm/src/stm32l4/stm32l4_pwm.c: fix printf format 
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2021-12-10 12:30:26 -06:00
Daniel Agar
efc949bceb arch/arm/src/stm32/Kconfig STM32_STM32F412 add SPI2 & SPI3 2021-12-09 21:30:41 -06:00
chao.an
3d75c25737 cortex-m/hardfault: enhance the dump information of mem/hard-fault 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-09 11:42:21 -06:00
chao.an
66e604b40e cortex-m/hardfault: add usage-fault handler 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-09 11:42:21 -06:00
chao.an
2f449245cc cortex-m/hardfault: add bus-fault handler 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-09 11:42:21 -06:00
chao.an
99fa58c871 arm/cortex-m23: armv8-m baseline do not support mem-fault 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-09 05:36:00 -06:00
chao.an
3e812dd88c cortex-m/fault: add CFSR(Configurable Fault Status Register) Definitions 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-09 04:30:06 -06:00
Xiang Xiao
6357523892 arch: Add _wchar_t typedef like other basic types 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-09 16:57:23 +09:00
chao.an
9b502dca05 arm/backtrace: disable the sanitize address check 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-09 01:05:46 -06:00
chao.an
7a61588b00 cortex-m/backtrace: remove the push process to simplify backtrace 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-09 01:05:46 -06:00
chao.an
437c81f8d0 cortex-m/assert: dump all registers with alias 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-09 00:16:04 -06:00
Michal Lenc
ae57492189 samv7: enable MCAN driver support for both rev A and rev B 
This commit enables the MCAN driver to function with both rev A and rev B
version of the chip. The version of the chip is selected automtically from
SAM_CHIPID_CIDR register so there is no need to predefined it in the
configuration.

The functonality was tested on rev B version of the chip. The rev A was
not tested since I do not have the functional board but the code remains
the same as in the previous NuttX version so it should not cause any
additional troubles.

The code is co-authored by Miloš Pokorný who wrote the initial transition
to rev B of the chip.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Co-authored-by: Miloš Pokorný <milos.pokorny@seznam.cz>
 2021-12-07 23:36:11 -06:00
Huang Qi
58e0781e2e arch/arm: Implement TLS support 
Signed-off-by: Huang Qi <no1wudi@qq.com>
 2021-12-07 23:31:41 -06:00
Masayuki Ishikawa
bec9058b4c arch: lc823450: Replace the critical section with spinlock in lc823450_serial.c 
Summary:
- This commit replaces the critical section with spinlock
- The logic is the same as cxd56_serial.c

Impact:
- None

Testing:
- Tested with lc823450-xgevk:bt

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-12-07 23:28:54 -06:00
Huang Qi
63ab2f4308 arch/risc-v: Introduce basic support for qemu rv32 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-07 23:28:33 -06:00
raiden00pl
54e3b148e9 arch/sim/src/sim/up_assert.c: fix implicit declaration warning 2021-12-07 07:51:44 -06:00
anjiahao
9d6c92f0fa arch:move debug.h form headfile to c file 
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2021-12-07 04:01:27 -08:00
fenghang
c39ef4420e 1.phyplus update files to accord with the requirement of chcekpatch.sh 
2.fix some files to fix compile warning

3.remove blueteeth header files, which are not used in nuttx core.

4.fix configs and add lost files

5.update defconfig, remove useless items

6.fix compile warning for nuttx phyplus

7.delete useless: ble, h4, zblue defconfig files form phyplus configure folder

8.fix file format check error on phyplus source code

9.fix phyplus kconfig param error

10.update configure file for nuttx
 2021-12-07 01:37:29 -06:00
fenghang
073c9880a3 phyplus first submit 2021-12-07 01:37:29 -06:00
chao.an
437a30d117 arch/tcbinfo: fix build break if task name disabled 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-06 00:47:58 -06:00
Dong Heng
698f1f76ff risc-v/esp32c3: Refactor SPI Flash to support umask interrupt when R/W/E SPI Flash 
This can fix BLE assert when erase SPI Flash.
 2021-12-06 13:13:11 +09:00
Xiang Xiao
a0990ee416 arch: Remove the duplicated up_tls_info implementation 
Define up_tls_info in arch/arch.h directly if the general one isn't suitable

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-05 20:59:53 -06:00
Xiang Xiao
19e5ee6ce0 arch: Remove FILE dump code from _up_dumponexit 
since the kernel build can't access the userspace memory
inside other process directly

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-06 11:23:58 +09:00
Abdelatif Guettouche
50d217a9e8 esp32_cpustart.c: Improve comments around the usage of the inter-cpu 
startup handshake.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-12-02 11:21:49 -06:00
Abdelatif Guettouche
b34951e3a0 esp32_cpustart.c: Remove the CONFIG_SMP condition on some part of code 
because the whole file is only built if CONFIG_SMP is enabled.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-12-02 11:21:49 -06:00
Xiang Xiao
b65c7c26cf arch: Dump task name through tcb_s::name instead of argv[0] 
since argv is defined in task_tcb_s not tcb_s

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-01 16:04:15 +01:00
Gerson Fernando Budke
c3307fce6b arch/arm/Kconfig: Add ARCH_HAVE_PROGMEM config 
The Atmel samv7 implements progmem functionality. However, there is
missing ARCH_HAVE_PROGMEM Kconfig symbol. This add missing symbol.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
 2021-11-29 21:31:08 -06:00
Petro Karashchenko
31809724e1 boards/same70-xplained: disable systick before loading MCUboot application 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-11-28 20:33:53 -06:00
Petro Karashchenko
fae27cc945 arch/samv7: fix unaligned address write for progmem interface 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-11-28 11:04:28 -06:00
Michal Lenc
ce53ea5da6 arch/arm/src/samv7: add DMA and TC trigger support to AFEC driver 
This commit adds DMA and TC support to SAMV7 AFEC driver. The AFEC (ADC)
can now be triggered by Timer/counter at chosen frewuency and samples can
be transfered via DMA with configurable number of samples. Timer/counter
trigger is now set as a default option with the possibility to change it
to software generated trigger.

DMA is inspired by SAMA5 driver and also uses ping pong buffers.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-11-27 06:17:45 -06:00
Michal Lenc
6f2e23ad0c arch/arm/src/samv7/sam_tc.c: fix compile warnings and errors 
Just a minor change fixing some compile warnings and errros, does not have
any impact on functionality.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-11-27 06:17:45 -06:00
Abdelatif Guettouche
251b8a3445 esp32xx_rtc: Include "clock/clock.h" to have a declaration of 
g_basetime.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-11-26 15:23:47 -03:00
Abdelatif Guettouche
af11cf6cd1 esp32xx_rtc.c: Fix a duplicated assignment. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-11-26 15:23:47 -03:00
Dong Heng
66023da10c risc-v/esp32c3: Refactor ADC calibration 
Use calibration parameters from efuse rather than self-calibration.
 2021-11-26 15:23:24 -03:00
Petro Karashchenko
0d9425676d arch/arm/src/samv7: add flash progmem erasestate ioctl support 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-11-26 14:55:34 -03:00
Petro Karashchenko
134b2e6ec9 arch/arm/include/samv7: fix typo in samv7 irq header files 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-11-26 14:55:34 -03:00
Petro Karashchenko
dd647d200e arch/samv7/sam_progmem: fix page size flash writing 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-11-26 08:47:08 -06:00
Xiang Xiao
e30a5f3790 arch/sim: Add new option to enable arch specific hostfs 
we have many different hostfs implementation now, so it's better
to select the implementation explicitly, just like what we have
done for arm(FS_HOSTFS vs. ARM_SEMIHOSTING_HOSTFS).

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-11-25 14:42:23 +01:00
zhuyanlin
1b3005accf arch:cache_invalidate: fix unalign cacheline invalidate 
Only invalidate may corrupt data in unalign start and end.
Use writeback and invalidate instead.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-11-24 22:48:13 -06:00
zhuyanlin
4db5016d83 arch:hostfs: add cache coherence config for semihosting option 
N/A

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-11-24 22:48:13 -06:00
David Sidrane
ad7e36d83f stm32f7:sdmmc defer invalidate until after DMA completion 
The FAT was not coherent. Resulting in a write failed
   with errno:28 No space left on device.

   It is unclear how the memory is acesses prior to the DMA
   completion. But this restructuring ensures the data
   is coherent.

   This issue was not detected on the stm32h7
 2021-11-24 20:38:23 -06:00
Jani Paalijarvi
4dfd3c9160 arch/riscv: Add ARCH_HAVE_SPI_CS_CONTROL for mpfs 
Make it possible to override SPI CS function in board logic

Co-authored-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-11-24 06:50:32 -06:00
Lee Lup Yuen
6e68d55f8a Fix GPIO output 2021-11-24 06:48:50 -06:00
chao.an
7cbb8da692 binfmt/elf: add bare metal coredump support 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-11-23 20:48:00 -06:00
chao.an
0f76ff42eb arch/sim: add arch elf define 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-11-23 20:34:56 +09:00
chao.an
4c76c356ef arch/arm: add more arch elf define 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-11-23 20:34:56 +09:00
Abdelatif Guettouche
65db787eff esp32_irq.c: Fix retrieving IRQ number and peripheral ID when it comes 
to GPIOs in SMP mode.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-11-22 11:41:10 -06:00
Xiang Xiao
a29ee19af4 driver/motor: Remove the unnecessary critical section operation 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-11-18 19:27:07 -06:00
Jani Paalijarvi
6dd4d5de15 risc-v/mpfs: Add support for Aries M100PFSMVP board 
- Add defconfig and board specific files
- Create mpfs/common for code which is shared between MPFS boards.
- Add support for GPIO driven EMMCSD mux.
- Move DDR Libero definitions from arch to boards.

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
 2021-11-18 10:59:44 -03:00
Xiang Xiao
a799835ec6 arch/arm: Remove EXPERIMENTAL from ARCH_TRUSTZONE_XXX 
since it work on the product device

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-11-17 08:59:14 -03:00
zhuyanlin
ffb543d061 xtensa: add setjmp.h include file 
N/A

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-11-17 02:23:45 -06:00
zhuyanlin
0e002af323 xtensa_backtrace: fix typ error 
N/A

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-11-17 01:47:26 -06:00
Andres Sanchez
064f6c8c55 add MTDIOCTL_PROGMEM_ERASESTATE support 
Signed-off-by: Andres Sanchez <tito97_sp@hotmail.com>

solve style check errors.
 2021-11-16 14:45:03 -03:00
Eero Nurkkala
6db480a7f9 mpfs: emmcsd: boost waitresponse perf 
When waiting for a response to a sent command, the command
complete bit (MPFS_EMMCSD_SRS12_CC) should always guarantee
the completion of that particular command. There's no need
to have some combinations skipping the check of the command
complete bit. Thus, remove the 'waitbits' parameter as it's
unnecessary.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-11-16 10:25:57 -06:00
Dong Heng
92eedd93a7 risc-v/esp32c3: Fix reset triggering crash nested when crash 2021-11-16 10:44:54 -03:00
Abdelatif Guettouche
5a41572fd0 esp32c3/esp32c3_usbserial.c: Initialize cpuint to ENOMEM, otherwise the 
first attempt to attaching an interrupt will trigger an assertion.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-11-15 12:11:45 -06:00
Alin Jerpelea
6deaba896d arch: Haltian Ltd: update licenses to Apache 
Gregory Nutt has submitted the SGA
Haltian Ltd has submitted the SGA
Uros Platise has submitted the ICLA

as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-11-15 06:49:32 -06:00
Xiang Xiao
2262ddfa6d arch: Remove fflush(stdout) from driver code 
it's wrong to call stdio function inside driver

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-11-15 00:04:12 +01:00
Abdelatif Guettouche
6cbcbd5481 arch/risc-v&xtensa/Kconfig: Don't select LIBC_ARCH_MEMCCMP. The Kconfig 
option doens't exist and we are not providing any external
implementation.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-11-13 11:54:42 -03:00
Abdelatif Guettouche
a01cb867ce esp32c3_rom.ld: Add some of the string.h functions to the linker 
script.

These functions are strongly declared and thus will be used instead of
any other implementation.  Furthermore, necessary Kconfig options are
selected to avoid building those function from NuttX's C library.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-11-13 11:54:42 -03:00
zhuyanlin
c6c534f27b xtensa:mpu:use WRITEBACK attribute for intsram & extsram 
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-11-13 05:59:10 -06:00
Dong Heng
fed7808d80 esp32 & esp32c3: Partition supports BIO cmd 2021-11-13 05:58:30 -06:00
anjiahao
edaa8a0ce9 fix sim_x11fb compile error 
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2021-11-13 05:58:01 -06:00
Dong Heng
f5c5d77744 risc-v/esp32c3: Add hardware brownout check and reset 2021-11-12 16:50:19 -03:00
Eero Nurkkala
876b39914b mpfs: uart: add a way to configure uart3 and uart4 
Currently configuring the uart3/4 as the serial console
doesn't work. Apply proper changes in mpfs_config.h that
enables the following configuration options:

 - CONFIG_UART3_SERIAL_CONSOLE
 - CONFIG_UART4_SERIAL_CONSOLE

Also, fix a typo in mpfs_lowputc.c that gives a compile
error if defined.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-11-11 06:02:27 -06:00
zhuyanlin
012bd1494c arch:debug: add struct for task aware debug. 
When enable DEBUG_TCBINFO config, a global struct will
provide, then debuggers can aware nuttx task infomation.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-11-10 14:31:10 -03:00
Juha Niskanen
201c67acbd stm32l4 dfumode: enable for STM32L4+ chips 2021-11-10 11:18:37 -06:00
Alan C. Assis
b8c33e585e esp32c3: Fix GPIO Output on pins 18 and 19 USB/JTAG 2021-11-09 20:54:34 -06:00
Abdelatif Guettouche
23039c92cf esp32c3/Make.defs: Alawys build esp32c3_serial.c 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-11-09 09:22:57 -03:00
Abdelatif Guettouche
ebd94961c7 arch/riscv/esp32c3: Add the USB-Serial Driver. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-11-09 09:22:57 -03:00
Abdelatif Guettouche
17cf3edf46 arch/risc-v/esp32c3: Add register definitions for the USB Serial/JTAG 
controller.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-11-09 09:22:57 -03:00
Dong Heng
a59aae6927 esp32/esp32c3: Fix MMU pages number calculation error 2021-11-07 21:59:54 -06:00
Michal Lenc
e0cef411e1 arch/arm/src/samv7: add support for AFEC (ADC) driver 
This commit adds microcontroller support for Analog Front End driver to
samv7 MCUs. Only software trigger via IOCTL is currently supported,
averaging can be set by configuration option CONFIG_SAMV7_AFECn_RES.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-11-07 21:04:56 -06:00
Yuichi Nakamura
3a0cd56623 rp2040: support I2C_RESET 2021-11-07 03:43:22 -08:00
Yuichi Nakamura
c109262a7f rp2040: add rp2040_gpio_get_function_pin() 2021-11-07 03:43:22 -08:00
raiden00pl
7b595ab73a arch/arm/stm32/stm32_qencoder: add support for Qenco index pin 2021-11-07 03:52:48 -06:00
zhuyanlin
5a4140f020 arch:xtensa: add setjmp xtensa function 
N/A

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-11-06 07:39:27 -05:00
zhuyanlin
580d17cc02 arch:xtensa: make xtensa_abi.h global include and usage 
N/A

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-11-06 07:39:27 -05:00
David Sidrane
4b96c28ed4 stm32h7:Support SPI SPI_DELAY_CONTROL 2021-11-06 05:14:05 -05:00
David Sidrane
040a04241e drivers/spi:Define SPI_~CS~_DELAY_CONTROL to support other delays 2021-11-06 05:14:05 -05:00
Eero Nurkkala
f8832f7d86 mpfs: emmcsd: fix uninitialized value 
cppcheck reports the following:

arch/risc-v/src/mpfs/mpfs_emmcsd.c:2375:22: error: Uninitialized variable: waitbits [uninitvar]
  while (!(status & (waitbits | MPFS_EMMCSD_SRS12_EINT))

The finding is positive and this patch initializes it to
zero properly.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-11-05 11:47:49 +01:00
David Sidrane
c077361a8a imxrt:usb Fix EP type allocation 2021-11-04 13:23:25 -05:00
David Sidrane
95f7f4b9e6 imxrt:usb DMA cache aligned Buffers for Endpoints 2021-11-04 13:23:25 -05:00
David Sidrane
bd2bc1e351 imxrt:usbdev Clean up cache maintainence 2021-11-04 13:23:25 -05:00
David Sidrane
c3d10ad0aa imxrt:usbdev formatting cleanup 2021-11-04 13:23:25 -05:00
David Sidrane
532635129c imxrt:usdhc add proper support for dcache (wb) 2021-11-04 13:23:25 -05:00
David Sidrane
5022244339 imxrt mpuinit:Set Data and Code Type to Normal 
Strongly-Ordered requires aligned access unless
  caching is enabled.

  Normal memory
  Accesses to normal memory region are idempotent...
  - unaligned accesses can be supported
 2021-11-04 13:23:25 -05:00
David Sidrane
34c3efcb91 imxrt mpuinit:Remove duplicate entry for ITCM (0x0) 2021-11-04 13:23:25 -05:00
David Sidrane
08d0434bad imxrt:mpu init handle dcache setting in MPU config 
With CONFIG_ARMV7M_DCACHE the cache maintenance operation
   are not present. Or if CONFIG_ARMV7M_DCACHE_WRITETHROUGH
   is on then buffering operations are no-ops.

   This change enables MPU_RASR_C and MPU_RASR_B if
   CONFIG_ARMV7M_DCACHE is only set.

   if CONFIG_ARMV7M_DCACHE_WRITETHROUGH is set then only
   MPU_RASR_C is enabled.

   N.B When caching is disalbed unaligned access may cause hard faults
   so add -mno-unaligned-access

   It is always safe to enable Buffering in FLASH to achive unaligned
   access leniency, as it is not written to.
 2021-11-04 13:23:25 -05:00
ChenWen
440787c0c1 risc-v/esp32c3: Fix Wi-Fi & BLE coexist issue 
1. Wi-Fi and BLE use common PHY functions.
  2. Fix Wi-Fi & BLE coexist adapter error.
  3. Update esp-wireless-drivers-3rdparty, provide coexist protection for connection.
 2021-11-04 11:02:05 -03:00
ChenWen
65d7f4bfb3 riscv/esp32c3: Support more country codes 2021-11-04 11:02:05 -03:00
ChenWen
4fc2f6e28c riscv/esp32c3: Support debug log configuration for Wi-Fi library 2021-11-04 11:02:05 -03:00
ChenWen
02968cc124 risc-v/esp32c3: Improve Wi-Fi connection success rate 2021-11-04 11:02:05 -03:00
ChenWen
222ec556d5 riscv/esp32c3: Fix some Wi-Fi issues 
1. Fix the issue that Wi-Fi can't connect to some special routers occasionally.
  2. Support Wi-Fi 12/13 channel active scanning by default.
  3. Update Wi-Fi driver code to fix issue of failure to send pkt.
  4. Replace software random with hardware random
  5. Fix Wi-Fi mode start error
 2021-11-04 11:02:05 -03:00
chenwen
33031a2813 riscv/esp32c3: Fix the issue of Wi-Fi automatic disconnection 2021-11-04 11:02:05 -03:00
chenwen
afbad5ca9d riscv/esp32c3: Clear station configuration when connection fails or disconnect 2021-11-04 11:02:05 -03:00
Eero Nurkkala
8e43f39141 mpfs: cache: provide L1/L2 cache enablers 
E51 may configure the L1 and L2 caches. Once configured,
no reconfiguration is possible after hardware reset is
issued.

L2 is 16-way set associative with write-back policy. The
size 2 MB, from which 1 MB is utilized with the values
provided here. That's a total of 8 ways. The rest of the
L2 is left out for the bootloader usage.

mpfs_enable_cache() first checks the bootloader usage
doesn't overlap with the cache itself, thus providing a
set of functional values.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-11-04 11:00:55 -03:00
Alexander Lunev
60de445ab3 stm32h7 sdmmc: do not enable power saving configuration bit (in SD 4-bit mode) because 
the SDIO clock is not enabled when the bus goes to the idle state, that, in turn, breaks
IRQ delivering mechanism over DAT[1]/IRQ SDIO line to the host.
 2021-11-03 22:50:14 -05:00
Xiang Xiao
3e967f784e sim: Split SIM_SANITIZE to SIM_ASAN and SIM_UBSAN 
align the naming style with MM_ASAN

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-11-02 21:02:43 +01:00
mage1
c82a676630 sim: fix sim runtime err under sanitize check mode. 
since gcc sanitize can not stub proper code in nuttx kernel code.
 2021-11-02 21:02:43 +01:00
Jani Paalijarvi
a16a9f80e2 mpfs: i2c: Add support for adaptive I2C bus frequency 
Select the closest possible frequency which is smaller
than or equal to requested in I2C msg
 2021-11-02 04:10:08 -05:00
ligd
2f4662c513 arch/arm: Remove -mcpu for fix warning 
warning: switch '-mcpu=cortex-m55' conflicts with '-march=armv8-m.main' switch

Signed-off-by: ligd <liguiding1@xiaomi.com>
 2021-11-01 21:28:10 -05:00
ligd
8417b4726b Revert "arch/armv8-m: use -mfpu=auto based on -mcpu=cortex-m55" 
This reverts commit d9a5b92c1a306a70df52d50a02a80dc8ef20bf0d.

Revert "arch/arm: Remove -march and -mtune"

This reverts commit b8e99cf12f3a287311a2d341f285c71a5da3e4d4.
 2021-11-01 21:28:10 -05:00
Abdelatif Guettouche
860370284e esp32c3_dma: Remove the DMA test included in the driver along with its 
defconfig.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-11-01 13:49:59 -05:00
Alexander Vasiljev
aeb1d3098d stm32h7/dmamux: correct bit fields 2021-11-01 14:40:33 -03:00
Abdelatif Guettouche
73f15ed544 esp32/Kconfig: Make ESP32_BT_RESERVE_DRAM default to 0 again if 
Bluetooth is not enabled.  When Bluetooth is enbaled then it defaults to
64KB.  This will not wast those 64KB of memory when Bluetooth is not enabled.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-11-01 10:01:38 -05:00
Alexander Lunev
33d236121f stm32h7 sdmmc: added missing sdio_set_sdio_card_isr() function to initialize SDIO in-band interrupt logic 2021-10-31 22:26:13 -05:00
Xiang Xiao
b58379b738 arch/arm: Add l suffix for INT32_C macro 
since int32_t typedef to signed long

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-10-31 12:56:41 -03:00
Michal Lenc
a64903acc7 samv7: adds support for QSPI driver in SPI Mode 
This commit adds new files that support functionality of QSPI driver in
SPI Master Mode. This functionality is included in new files sam_qspi_spi.x
to avoid too much mess in the source code. QSPI in SPI mode can be turn
on by config option SAMV7_QSPI_SPI_MODE.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-10-30 01:24:31 -05:00
yinshengkai
ee17ae5ba1 tool: add code coverage tool 2021-10-29 19:21:23 +02:00
raiden00pl
bb5e3fee44 arch/arm/src/stm32/stm32_foc.c: define missing FOC1_PWM_FZ_BIT for G4 2021-10-29 07:49:59 -05:00
raiden00pl
8e9e54cad3 arch/arm/src/stm32/hardware/stm32_dbgmcu.h: fix invalid STM32_DBGMCU_APB2_FZ offset for G4 2021-10-29 07:49:59 -05:00
Alexander Vasiljev
35e93644cf stm32h7: add low power timers 2021-10-27 10:37:05 -05:00
Jiuzhu Dong
1ed4118378 power/battery: add baterr, batinfo, batwarn for debug log 
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-10-26 13:59:42 -03:00
chao.an
b90d094138 arch/sim: add native socket support based on usrsock 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-10-26 08:01:50 -05:00
Gustavo Henrique Nihei
de0e4d4aac xtensa/esp32s2: Rename MTD-related configs to become more intuitive 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-25 21:45:20 -05:00
Gustavo Henrique Nihei
06bb85d8a5 risc-v/esp32c3: Rename MTD-related configs to become more intuitive 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-25 21:45:20 -05:00
Gustavo Henrique Nihei
fb00ab3242 xtensa/esp32: Rename MTD-related configs to become more intuitive 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-25 21:45:20 -05:00
Gustavo Henrique Nihei
eb889b0884 xtensa/esp32s2: Enable Partition Table allocation at custom offset 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-25 16:34:58 -03:00
Gustavo Henrique Nihei
eb7ffd014e risc-v/esp32c3: Enable Partition Table allocation at custom offset 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-25 16:34:58 -03:00
Gustavo Henrique Nihei
211f899b62 risc-v/esp32c3: Refactor and reorganize Partition Table related configs 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-25 16:34:58 -03:00
Gustavo Henrique Nihei
9d7b9821b3 xtensa/esp32: Enable Partition Table allocation at custom offset 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-25 16:34:58 -03:00
Gustavo Henrique Nihei
b555b3f89e xtensa/esp32: Refactor and reorganize Partition Table related configs 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-25 16:34:58 -03:00
Gustavo Henrique Nihei
793266d39e espressif: Fix spacing style in Kconfig files 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-25 08:01:44 -05:00
Gustavo Henrique Nihei
4ff754827c espressif: Fix prompt string of Wi-Fi FS mount point configs 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-25 08:01:44 -05:00
Gustavo Henrique Nihei
a1af605973 espressif: Fix references to Wi-Fi according to Wi-Fi Alliance 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-25 08:01:44 -05:00
Alan C. Assis
7e8003cba1 Move chip specific file compilation to CHIP_CSRCS 2021-10-23 04:03:12 -05:00
Alan C. Assis
03738622a1 esp32s2: Add RNG driver support and board profile example 2021-10-23 04:03:12 -05:00
David Sidrane
e1a0a1188e stm32h7:Support CONFIG_MPU_RESET and CONFIG_ARM_MPU_EARLY_RESET 2021-10-23 03:58:26 -05:00
David Sidrane
e66423229a stm32f7:Support CONFIG_MPU_RESET and CONFIG_ARM_MPU_EARLY_RESET 2021-10-23 03:58:26 -05:00
David Sidrane
fd2c1cb216 stm32:Support CONFIG_MPU_RESET and CONFIG_ARM_MPU_EARLY_RESET 2021-10-23 03:58:26 -05:00
David Sidrane
9d8f7126f6 armv7-m,armv7-r,armv8-m:MPU Add mpu_reset and ARM_MPU_EARLY_RESET 
When NuttX is booted from a foreign (non NuttX)
   bootloader. There as a possibility that the
   bootloader configured the MPU, in an
   incompatible way for the NuttX memory usage.

   The option to reset the MPU before it is initialized
   may not succeed if the bss and data initialization
   code violated the previous MPU configurations.

   Added herein are ARM_MPU_RESET and
   ARM_MPU_EARLY_RESET. The former can be used
   If the system is capable of booting and running
   NuttX MPU configuration code without an MPU
   violation. The latter is used if the system can
   not run the bss and data initialization code.

   These are options so that a NuttX may be configured to
   not clobber a bootloader MPU configuration in a system
   that is architected to share the MPU configuration task.
 2021-10-23 03:58:26 -05:00
zhuyanlin
cf1a04d0a2 xtensa:cache: add lock & unlock feature 
Since some xtensa cores cache support lock & unlock feature.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-10-22 13:31:32 -03:00
zhuyanlin
b4ea11f7b1 arch:cache: add lock feature for cache 
Some architectures support lock & unlock cache feature.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-10-22 13:31:32 -03:00
David Sidrane
90cfa6f313 imxrt:syslog is dependant on arm_lowputc 2021-10-22 10:07:20 -05:00
oreh-a
3c1ac89557 Fixed line length 2021-10-22 09:03:14 -05:00
Alexander Oryshchenko
ed392abb83 Added ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG option to stm32f0/g0/l0 chip configiuration 2021-10-22 09:03:14 -05:00
Eero Nurkkala
e57f3f7a3a mpfs: emmcsd: provide proper internal emmc settings 
So far the SD-card functionality has been tested with
the driver. Now, also the internal eMMC has been tested
working with this patch. This patch applies IOMUX and
clock settings that have been tested working with the
internal eMMC in the Polarfire Icicle kit.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-10-21 22:41:08 -05:00
Eero Nurkkala
c34b9620db mpfs: clockconfig: add clock initialiation sequence 
Add clock initialization sequence especially for systems
containing no bootloader.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-10-21 22:40:26 -05:00
Eero Nurkkala
bc72ccdf6a mpfs: Kconfig/Make: add DDR support flag 
This adds the proper flag for introducing the DDR
support. Also call the mpfs_ddr_init() at the
proper location.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-10-21 22:40:26 -05:00
Eero Nurkkala
3b330089d5 mpfs: ddr: add DDR training 
This adds DDR training. The training has a small chance of failing,
and then the training is restarted.

DDR training cannot be done meaningfully while the software is
in DDR. If the system is intended to run from eNVM, like a
bootloader, the linker script should be tuned to utilize the envm
region as follows:

  envm (rx)   : ORIGIN = 0x20220100, LENGTH = 128K - 256
  l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 1024k

256 bytes are reserved for the system; The fixed block may be
installed from the 'hart-software-services' -repository:
https://github.com/polarfire-soc/hart-software-services.git

For example, the 256-byte image: hss-envm-wrapper-bm1-dummySbic.bin
may be prepended on the nuttx bootloader image in the following
manner:

 cat hss-envm-wrapper-bm1-dummySbic.bin > nuttx_bootloader.bin
 cat nuttx.bin >> nuttx_bootloader.bin
 riscv64-unknown-elf-objcopy -I binary -O ihex --change-section-lma
  *+0x20220000 nuttx_bootloader.bin flashable_image.hex

This provides an image 'flashable_image.hex' that may be flashed on
the eNVM region via Microsemi Libero tool.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-10-21 22:40:26 -05:00
Jukka Laitinen
c5b11f42b6 mpfs_head.S: Support for booting on different harts and from eNVM 
- Fix the FPU enabling code
- If booting from eNVM, all harts start booting. With CONFIG_MPFS_BOOTLOADER,
  one can allow just one hart booting and rest are stuck in wfi.
- Check that mtvec is actually updated before continuing the boot
- Create 5 IRQ stacks, one for each hart

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-10-21 22:40:26 -05:00
Jukka Laitinen
37761c293d mpfs_head.S: Fixes for booting on different harts 
- Jump to mpfs_start with mhartid in a0 as the comment says
- Don't invalidate mmu tlb on e51 (it doesn't have mmu)
- Fix FPU initialization flags on e54 (it fires IRQ5 and crashes)

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-10-21 22:40:26 -05:00
Jukka Laitinen
e5843db282 mpfs: Add configuration flags to configure NuttX booting on single hart 
The bootloader hart also configures the needed clocks and peripherals.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-10-21 22:40:26 -05:00
Eero Nurkkala
d909b0f635 mpfs: hardware/memorymap: add more base addresses 
Add a number of missing base addresses.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-10-21 22:40:26 -05:00
chao.an
bd7cb1aae5 sim/bluetooth: remove the WIRELESS_BLUETOOTH depends if native host is in use 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-10-21 11:24:46 -05:00
Abdelatif Guettouche
018aa8eb8d esp32c3_serial.c: Remove the stub implementations of the early serial 
functions as they are only called when the configuration is enabled.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-20 10:22:10 -03:00
Xiang Xiao
1efc9fbac6 sim/rptun: Trigger the callback only the sequnece number change 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-10-20 10:21:54 -03:00
Abdelatif Guettouche
c83c1071cc esp32c3_bignum.c & esp32c3_sha.c: Fix some trivial nxstyle complaints. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-19 18:41:57 -03:00
Abdelatif Guettouche
e424241d09 arch/risc-v/esp32c3: Remove the bignum test from the driver. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-19 18:41:57 -03:00
Abdelatif Guettouche
91cb9dafaf arch/risc-v/esp32c3: Remove the RSA test from the driver. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-19 18:41:57 -03:00
Abdelatif Guettouche
652d77efd2 arch/risc-v/esp32c3: Remove the SHA test from the driver. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-19 18:41:57 -03:00
Abdelatif Guettouche
5d1c01aea7 arch/risc-v/esp32c3: Remove the AES test from the driver. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-19 18:41:57 -03:00
Abdelatif Guettouche
8288a04a0b arch/xtensa/esp32: Remove the AES test from the driver. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-19 18:41:57 -03:00
zhuyanlin
b5134565fa arch:xtens:mpu: modify acc and memtype to uint32_t 
The uint8_t and uint16_t will overflow in MPU_ENTRY_AR marco.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-10-19 00:24:31 -05:00
Xiang Xiao
91398e73eb arch/xtensa/Kconfig: add quotes in source to clean warnings from setconfig 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-10-19 00:33:51 +02:00
Michal Lenc
3e1ce5f770 arch/arm/src/imxrt/hardware: add header file for ADC_ETC module 
This commit adds header file imxrt_adc_etc.h for external ADC trigger
module. This contains only definitions of ADC_ETC registers and separate
bits, implementation of ADC_ETC driver is yet to be done.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-10-17 16:50:59 +02:00
Abdelatif Guettouche
7549de49b4 arch/*_cpupause:Allow a spin before taking the g_cpu_wait spinlock. 
If we repeatedly call up_cpu_pause and up_cpu_resume, there would be
cases where the next call to up_cpu_pause happens while the other CPU is
still responding to the previous resume request. In this case the
DEBUGASSERT will trigger. We should allow the first CPU to wait until the
other CPU has finished responding to the resume request.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-17 21:10:23 +09:00
Abdelatif Guettouche
7b43d11435 esp32_spiflash.c: Allocate only one variable to hold the cache state in 
single CPU mode.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 22:56:21 -07:00
Abdelatif Guettouche
f54a929001 esp32_spiflash.c: Keep the index of the other CPU between SPI Flash 
operations.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 22:56:21 -07:00
Abdelatif Guettouche
eeb68bda3d xtensa_testset.c: Simplify the test-set function and remove some old 
comments.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 22:56:21 -07:00
Abdelatif Guettouche
dfe1637864 esp32_spiflash.c: Pause the other CPU during flash operation. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 22:56:21 -07:00
Abdelatif Guettouche
f2c2323642 esp32_intercpu_interrupt.c: Force the functions to internal SRAM. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 22:56:21 -07:00
Abdelatif Guettouche
d2bc011719 arch/xtensa/xtensa_cpupause.c: Allow a spin before taking the g_cpu_wait 
spinlock.

If we repeatedly call up_cpu_pause and up_cpu_resume, there would be
cases where the next call to up_cpu_pause happens while the other CPU is
still responding to the previous resume request.  In this case the
DEBUGASSERT will trigger.  We should allow the first CPU to wait until the
other CPU has finished responding to the resume request.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 09:46:23 -07:00
Abdelatif Guettouche
591c1563b8 esp32_oneshot_lowerhalf.c: Use the same alignment as the rest of the 
code base.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
9e1d2ca95e esp32_rt_timer.c: Group static variables into a struct and fix naming 
standard

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
0dff3f2762 esp32_wifi_adapter.c: Use the specified spin lock when 
enabling/disabling interrupts.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
a50d673df7 esp32_wifi_adapter.c: Don't hold another spinlock when calling 
enter_critical_section, we already hold the global IRQ spinlock.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
11216257cf esp32_rt_timer.c: Don't nest calls to spin_lock_irqsave with a device 
specific spinlock, this will lead to deadlocks.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
e847c61801 esp32_wifi_adapter.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
32f7471f9e esp32_wlan.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
4ae1285124 esp32_emac.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
e64390d5e9 esp32_rt_timer.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
c61009c2cf esp32/esp32_spi_slave.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
2273684cb1 esp32/esp32_spi.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
0123243f9a esp32/esp32_i2c.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
0af9a49d9c esp32/esp32_oneshot_lowerhalf.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
698af43d78 esp32/esp32_freerun.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
04bd27400a xtensa/esp32_wdt_lowerhalf.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
19a096cdfe arch/xtensa/esp32_tim_lowerhalf.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Gustavo Henrique Nihei
ff705586bb xtensa/esp32s2: Provide SPI Flash parameters to MCUboot build 
Also unify bootloader config creation to reduce duplication.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-15 23:55:10 -07:00
Gustavo Henrique Nihei
4d5e0f8fe1 xtensa/esp32: Provide SPI Flash parameters to MCUboot build 
Also unify bootloader config creation to reduce duplication.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-15 23:55:10 -07:00
Gustavo Henrique Nihei
99ac065d0a risc-v/esp32c3: Provide SPI Flash parameters to MCUboot build 
Also unify bootloader config creation to reduce duplication.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-15 23:55:10 -07:00
Gustavo Henrique Nihei
cc78541966 risc-v/esp32c3: Add esp-nuttx-bootloader folder to gitignore list 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-15 23:55:10 -07:00
Gustavo Henrique Nihei
ae25ebce4c risc-v/esp32c3: Fix wrong arch in the path to chip folder 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-15 23:55:10 -07:00
Abdelatif Guettouche
a7d8d9dd98 esp32s2/tie.h: Run the file though detab. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-14 07:39:54 -03:00
Abdelatif Guettouche
6d246eb18f esp32s2/tie.h: The old tie.h file was from ESP32 which doesn't apply to 
ESP32-S2.  This commit gets the correct S2 tie.h file

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-14 07:39:54 -03:00
Abdelatif Guettouche
217fd97fd3 xtensa_coproc.S: Correctly save/restore coprocessor0 state. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-14 07:39:54 -03:00
Abdelatif Guettouche
7420f245bc xtensa_context.S: Save and restore SCOMPARE1 when necessary. 
SCOMPARE1 is used by some atomic instructions and need to be preserved
during a context switch.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-14 06:32:17 -03:00
Alin Jerpelea
b9986ca016 arch: arm: update licenses to Apache 
Gregory Nutt is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-10-11 10:13:07 +02:00
jsun
c58fddb915 Open ble controller adaptation code 
N/A

Signed-off-by: jsun <jsun@bouffalolab.com>
 2021-10-08 02:30:27 -07:00
Jari van Ewijk
e4752fbaee S32K1xx arch: Add (optional) support for SPI native/hardware chip select 2021-10-05 06:07:18 -07:00
Gustavo Henrique Nihei
47e804b167 risc-v/esp32c3: Make BLE adapter code compliant to nxstyle 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-05 08:45:40 -03:00
Alan C. Assis
867c6d0636 esp32: Add initial support to Bluetooth Low Energy 
Co-authored-by: saramonteiro <saramonteirosouza44@gmail.com>
Co-authored-by: Gustavo Henrique Nihei <gustavonihei@gmail.com>
 2021-10-04 15:10:37 -03:00
Abdelatif Guettouche
d22b4ec539 espxx_rng.c: Add "/" at the beginning of paths for consistency. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-30 13:50:25 -03:00
Abdelatif Guettouche
c811cefa2d esp32c3_rng.c: Remove unused functions. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-30 13:50:25 -03:00
Abdelatif Guettouche
5c6a30c00b esp32_rng.c: Remove the initialization guard. The init function is 
called only once during startup.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-30 13:50:25 -03:00
Abdelatif Guettouche
6a262c5203 esp32_rng.c: Remove unused functions. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-30 13:50:25 -03:00
liuhuan
ee6138e9ba power: Open CONFIG_PM compilation failed 
include debug.h

Signed-off-by: liuhuan <liuhuan16@xiaomi.com>
 2021-09-30 07:16:07 -07:00
Jari van Ewijk
cf6dcbc6fd S32K1XX arch: gpioread may also be used for output pins 2021-09-30 04:30:50 -07:00
Xiang Xiao
77bc1d1bdf power/battery: Move the enumurate to the common place 
so the userspace program can handle the different battery driver equally

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-09-30 14:58:42 +09:00
P.Brier
b9d1fcb232 Use ethernet MAC programmed in imxrt OCOTP MAC0/MAC1 (teemsy board has this) 2021-09-29 20:45:14 -07:00
Sara Souza
8a142f474e xtensa/esp32-s2/rttimer: Disable alarm before setting a new value and enabling it 2021-09-28 21:02:57 -03:00
Sara Souza
33f2d46bff risc-v/esp32-c3/rttimer: Disable alarm before setting a new value and enabling it 2021-09-28 21:02:57 -03:00
Alin Jerpelea
15a37c5a5a arch: Omni Hoverboards: update licenses to Apache 
Gregory Nutt has submitted the SGA
Omni Hoverboards has submitted the SGA
David Sidrane has submitted the ICLA
Mateusz Szafoni has submitted the ICLA
Sebastien Lorquet has submitted the ICLA
Paul Alexander Patience has submitted the ICLA

as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-09-28 04:37:38 -07:00
Gustavo Henrique Nihei
20341e6f17 risc-v/esp32c3: Enable support for "make bootloader" target 
This enables the provisioning of the bootloader binaries through the
build system.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-27 18:22:29 -07:00
Gustavo Henrique Nihei
3c63cb522c risc-v/esp32c3: Enable booting from MCUboot bootloader 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-27 18:22:29 -07:00