This commit adds support for 1 wire interface over serial driver. SAMv7
MCU does not have build in one wire support therefore external hardware
still has to be used (connection of RX/TX for example).
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
UART/USART peripheral can be used for more than just standard serial
driver. It can for example be used for 1 wire interface communication
(with external circuitry added). This changes the Kconfig for SAMv7 to
allow future implementation of these drivers. Now user can select
what kind of a driver he wants on UART/USART (serial or something else).
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Follow other risc-v based chips, and fix:
```
chip/rv32m1_irq.c: In function 'up_irqinitialize':
Error: chip/rv32m1_irq.c:98:3: error: array subscript -2048 is outside array bounds of 'uint8_t[2147483647]' {aka 'unsigned char[2147483647]'} [-Werror=array-bounds]
98 | riscv_stack_color(g_intstacktop - intstack_size, intstack_size);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from /github/workspace/sources/nuttx/arch/risc-v/src/common/riscv_internal.h:40,
from chip/rv32m1_irq.c:36:
/github/workspace/sources/nuttx/arch/risc-v/src/common/riscv_common_memorymap.h:72:16: note: at offset -2048 into object 'g_intstacktop' of size [0, 2147483647]
72 | EXTERN uint8_t g_intstacktop[]; /* Initial top of interrupt stack */
| ^~~~~~~~~~~~~
cc1: all warnings being treated as errors
```
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Fix:
```
riscv-none-elf-ld: sotest.o: ABI is incompatible with that of the selected emulation:
target emulation `elf64-littleriscv' does not match `elf32-littleriscv'
riscv-none-elf-ld: failed to merge target specific data of file sotest.o
```
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
There is a problem when vfork() calls execv() (or execl()) to start a new application:
When the parent thread calls vfork() it receives and gets the pid of the vforked task,
and not the pid of the desired execv'ed application.
see issue #3334
Signed-off-by: yangyalei <yangyalei@xiaomi.com>
rndis header length is 36, L2 header is 14, IPv6 header is 40, tcp header is 56 when sack option count is 4(default max_ofosegs is 4). so the iob bufsize should greater than we need.
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
The previous iob_trimhead added dev->iob->io_offset, so if the
input frame is not merged into the ofo segment, we need to reset
dev->iob->io_offset so that the subsequent tcp_send can properly
assemble packets.
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
When the upper layer calls goldfish_camera_data_uninit, priv->capture_cb=NULL, but when there is data transmission in goldfish_camera_thread, priv->capture_cb will be called, which will cause a crash.
Signed-off-by: yangsen5 <yangsen5@xiaomi.com>
bug:
user thread: hpwork:
timer_create() with SIGEV_THREAD
timer_settime()
irq -> work_queue() add nxsig_notification_worker to Q
timer_delete()
nxsig_cancel_notification()
call nxsig_notification_worker()
work_cancel()
timer_free()
nxsig_notification_worker() used after free
root cause:
work_cancel() can't cancel work completely, the worker may alreay be running.
resolve:
use work_cancel_sync() API to cancel the work completely
Signed-off-by: ligd <liguiding1@xiaomi.com>
In the 'wd_timer',the callback function executed by 'wd_expiration' could call wd_start,and g_wdtickbase might be updated.Subsequently, g_wdtickbase is incremented by the value of ticks, causing g_wdtickbase to be greater than the actual passage of time.
Signed-off-by: yangguangcai <yangguangcai@xiaomi.com>
Summary
Add ARM PCSI (Power State Coordination Interface) Support
for qemu. With the interface, Poweroff/PowerReset can be support
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary:
Adding virtual evaluate platform GoldFish. Which is based on
Android Goldfish Emulator, it's a ARM virt board but Android enhance
it with more featue
The patch set goldfish as a chip
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
1.Change priv to client or server
2.Allocate memory for name in regulator_rpmsg_get
3.Lock/unlock regulator_list in regulator_rpmsg_server_s
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
It uses the memory block as the serial communication medium, which can communicate between different processes or different CPUs
Using the following configuration, the cross-core communication rate of 200MHz cortex-M55 is about 461KB/s
RAM_UART_BUFSIZE=1024
RAM_UART_POLLING_INTERVAL=100
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
