The spawn proxy thread is a special existence in NuttX, usually some developers
spend a lot of time on stack overflow of spawn proxy thread:
https://github.com/apache/nuttx/issues/9046https://github.com/apache/nuttx/pull/9081
In order to avoid similar issues, this PR will remove spawn proxy thread to simplify
the process of task/posix_spawn().
1. Postpone the related processing of spawn file actions until after task_init()
2. Delete the temporary thread of spawn proxy and related global variables
Signed-off-by: chao an <anchao@xiaomi.com>
minidump will backtrace failure when use C code to save user context,
because the stack push operation in C code can disrupt the stack information.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Add private data for spi_bitbang low-level driver to add an instance
specific private data.
And add spi_destroy_bitbang() to clean up a driver instance.
1. stack_alloc_ptr should be freed in kernel mode
2. replace nxsched_release_tcb() to nxtask_uninit() to remove tcb from inactive list
Signed-off-by: chao an <anchao@xiaomi.com>
Timestamp location in can message has changed,
In the original logic timestamp is saved at the end of the data segment:
io_data
-------------------------------------------------
| CAN message | Time Stamp |
-------------------------------------------------
|<--------------- io_len ---------------->|
In the new structure timestamps will reuse NET_LL_GUARDSIZE to isolate CAN messages:
io_data io_offset
-------------------------------------------------
| Time Stamp | CAN message |
-------------------------------------------------
|<-------- io_len --------->|
This PR will:
1. Increase NET_LL_GUARDSIZE to 16 (sizeof(struct timeval)) if NET_CAN && NET_TIMESTAMP are enabled
2. Apply timestamp to adapt to the new structure
Signed-off-by: chao an <anchao@xiaomi.com>
When executing up_fbinitialize, the driver may turn on the vsync interrupt. If the vsync interrupt calls fb_pollnotify before executing fb->vtable->priv = fb it will cause null pointer access and crash.
Signed-off-by: pengyiqiang <pengyiqiang@xiaomi.com>
- Fix DMA addressing issues within litex_sendsetup/litex_recvsetup
- Extend with handling specific to eMMC commands during init & use.
- Cleanup of 4-bit BUS handling for SD and eMMC
- For eMMC, Send CMD0 during init as per JEDEC v4.41 for pre-idle
This commit adds deifiniton of get_timer_period() and adj_timer_period()
functions used by adjtime() interface.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This commit adds Linux like adjtime() interface that is used to correct
the system time clock if it varies from real value. The adjustment is
done by slight adjustment of clock period and therefore the adjustment
is without time jumps (both forward and backwards)
The implementation is enabled by CONFIG_CLOCK_ADJTIME and separated from
CONFIG_CLOCK_TIMEKEEPING functions. Options CONFIG_CLOCK_ADJTIME_SLEWLIMIT
and CONFIG_CLOCK_ADJTIME_PERIOD can be used to control the adjustment
speed.
Interfaces up_get_timer_period() and up_adj_timer_period() has to be
defined by architecture level support.
This is not a POSIX interface but derives from 4.3BSD, System V.
It is also supported for Linux compatibility.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
fix the problem that stat fails to use the relative path
An error will be reported if used in the following way:
stat("//./bin", &st);
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Store the old environment in a local context so another temporary address
environment can be selected. This can happen especially when a process
is being loaded (the new process's mappings are temporarily instantiated)
and and interrupt occurs.
When l2cc is already in disable state, performing a disable operation
again will flush incorrect cache data to memory
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Invalidate operations at DDI0246H_l2c310_r3p3_trm:
If there is a stale entry in the L2 cache, the system enables the invalidation of
the L1 cache. But before the controller invalidates the L2 cache, it allocates a
line from the L2 cache to an L1 cache.
The robust code sequence for invalidation with a non-exclusive cache arrangement is:
1. InvalLevel2 Address ; forces the address out past level 2
2. CACHE SYNC ; Ensures completion of the L2 inval
3. InvalLevel1 Address ; This is broadcast within the cluster
4. DSB ; Ensure completion of the inval as far as Level 2.
This sequence ensures that, if there is an allocation to L1 after the L1 invalidation, the data
picked up is the new data and not stale data from the L2
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
The current implementation requires the use of enter_critical_section, so the source code needs to be moved to kernel space
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Summary:
- This commit adds sabre-6quad:netnsh_ar8031 configuration
Impact:
- None
Testing:
- Tested with ping, telnet, iperf
- Note that iperf in TCP mode still has a performance issue.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
