Commit Graph

19706 Commits

Author SHA1 Message Date
Hidenori Matsubayashi
28180b49d1 arm64: add Cortex-A57 and Cortex-A72 configurations
This change adds the following:
- Rename the board configuration name from qemu-a53 to qemu-v8a.
- Add the configurations for Cortex-A57 and Cortex-A72.

Signed-off-by: Hidenori Matsubayashi <hidenori.matsubayashi@gmail.com>
2022-10-14 09:27:35 +08:00
Hidenori Matsubayashi
06cf41901f arch/arm64: cleanup defconfigs
Use CONFIG_ARCH_CHIP_QEMU instead of CONFIG_ARCH_CHIP_QEMU_A53. This is because these configurations depend on the hardware configuration of qemu (memory map, irq numbers, etc.).

Signed-off-by: Hidenori Matsubayashi <hidenori.matsubayashi@gmail.com>
2022-10-13 19:26:26 +08:00
Alan Carvalho de Assis
c297ecaa5d esp32s2: Add missing ESP32S2 SPIRAM config 2022-10-13 01:41:47 +08:00
zouboan
d3f84ba724 arch/sparc dismiss non-Unicode characters issue 2022-10-12 11:36:14 -03:00
zhangyuan21
7d34ebdd4e armv7-a: add l2 page mapping interface 2022-10-12 22:00:06 +08:00
zhangyuan21
466635a5e0 armv7-a: set normal memory shareable in smp mode 2022-10-12 19:54:09 +08:00
zhangyuan21
750007ded9 sched: use tick count for sched timer expiration 2022-10-12 11:55:46 +08:00
Zhe Weng
7225e44725 arch/sim: support multiple tapdev for sim
Support more than one TAP device for debugging (future) NAT and FORWARD, left WPCAP and VPNKit unchanged (force number to 1).
Although we can support at most 31 interfaces, limit to 8 like CONFIG_TUN_NINTERFACES.

Signed-off-by: wengzhe <wengzhe@xiaomi.com>
2022-10-12 01:57:21 +08:00
chao an
bcdd03cdf3 arm/backtrace: rename arm_backtrace_thumb.c to arm_backtrace_sp.c
1. rename arm_backtrace_thumb.c to arm_backtrace_sp.c
2. use EHABI stack unwinder instead of instruction unwind

Signed-off-by: chao an <anchao@xiaomi.com>
2022-10-12 01:55:48 +08:00
Brennan Ashton
4ce8cf7bdc bl602/dma: Fix possible call of null pointer to function 2022-10-11 14:34:52 +08:00
Xiang Xiao
1cd9fa25cd arm/tlsr82xx: Don't select ARCH_HAVE_BACKTRACE
since it's already selected by ARCH_ARM

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-10-11 00:01:35 +02:00
chao an
24129e4ba7 arm/backtrace: add support for EHABI(Exception Handling ABI) stack unwinder
Reference:
https://github.com/ARM-software/abi-aa/blob/main/ehabi32/ehabi32.rst
https://github.com/ARM-software/abi-aa/releases/download/2022Q1/ehabi32.pdf

Signed-off-by: chao an <anchao@xiaomi.com>
2022-10-11 03:11:37 +08:00
Jukka Laitinen
e793207bb6 arch/risc-v/src/mpfs: Add a config option for enabling L2 cache
Make a separate config flag for enabling L2 cache. This is on by
default when compiling a standalone/bootloader configuration, but
can also be disabled for special cases, such as memory testing

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-10-11 00:59:48 +08:00
liangchaozhong
cc426f8539 usrsock:add done flag in usrsock_iovec_do
set done to true if all data in iovec array is copied

Signed-off-by: liangchaozhong <liangchaozhong@xiaomi.com>
2022-10-11 00:57:49 +08:00
Andrés Sánchez Pascual
c28b05efd3 arch: stm32h7: Add support for dual bank flash
memory

Signed-off-by: Andrés Sánchez Pascual <tito97_sp@hotmail.com>
2022-10-10 01:07:45 +08:00
Brennan Ashton
8b7d2d3da4 bl602: Fix bug in lli functionality for dma. 2022-10-09 12:06:15 +02:00
Hidenori Matsubayashi
b0f9241ec1 arch/arm64: update to follow NuttX C Coding Standard
This change moves the static vars to the appropriate place to follow the coding standard. It also adds comments as sections and `static` where necessary.

Signed-off-by: Hidenori Matsubayashi <hidenori.matsubayashi@gmail.com>
2022-10-09 17:38:31 +08:00
Hidenori Matsubayashi
0b03a2316f arch/arm64/qemu/qemu_boot: fix wrong memory size
The default size in QEMU system is 128MB, and the size specified in chip.h is also 128MB. However, the region size for MMU was 512MB, so fixed it.

Signed-off-by: Hidenori Matsubayashi <hidenori.matsubayashi@gmail.com>
2022-10-09 17:18:26 +08:00
Masayuki Ishikawa
cb73e9a67d arch: qemu-rv: Refactor the entry point name for BUILD_KERNEL
Summary:
- This commit refactors the entry point name for BUILD_KERNEL
  to avoid misunderstanding the name

Impact:
- None

Testing:
- Tested with rv-virt:ksmp64

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-10-09 14:08:47 +08:00
Hidenori Matsubayashi
1297c23e7d arch/arm64/arm64_mmu: add mmu_nxrt_config
This change is a refactoring to match the userspace mmu_regions implementation.

Signed-off-by: Hidenori Matsubayashi <hidenori.matsubayashi@gmail.com>
2022-10-09 12:52:40 +09:00
Masayuki Ishikawa
4b6c9915fe arch: qemu-rv: Fix timer and IPI handling for BUILD_KERNEL+SMP
Summary:
- I noticed that the OS timer sometimes proceeds fast when
  a task is scheduled to run on CPUO via IPI.
- Actually, qemu-rv implementation shares supervisor software
  interrupt for both timer and IPI on CPU0.
- This commit fixes this issue.

Impact:
- qemu-rv only

Testing:
- Tested with qemu-6.2

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-10-08 17:19:51 +08:00
Masayuki Ishikawa
4e095d2e90 arch: risc-v: Add SMP support for BUILD_KERNEL
Summary:
- This commit adds SMP support for BUILD_KERNEL

Impact:
- RISC-V: BUILD_KERNEL + SMP only

Testing:
- Tested with rv-virt:ksmp64 (will be added later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-10-08 09:25:41 +08:00
Ville Juven
0d52b5be56 mpfs_mm_init: Mark the L2 kernel page table as a global mapping
Kernel mappings are global, i.e. they exist in every address environment
2022-10-07 17:26:21 +08:00
Ville Juven
373568f63a mpfs_mm_init.c: Ensure the L3 page table size is large enough
Run-time check for L3 page table size, to ensure it is large enough
to map all of the kernel memory.

NOTE: The check has to be run-time, as KFLASH_SIZE/KSRAM_SIZE are really
linker relocation symbols, and thus cannot be utilized compile-time.
2022-10-07 17:26:21 +08:00
Ville Juven
dbc9a5ffa2 riscv_mmu: Add some basic sanity checks for section boundaries
L3 table maps 2MB of memory, this brings an implicit requirement for
any L3 region to be aligned to 2MB. This commit adds build time sanity
checks to ensure this requirement is met.

For other SvXX architectures the boundary requirement (might be) is
different.
2022-10-07 17:26:21 +08:00
Masayuki Ishikawa
df6bf3e614 arch: risc-v: Introduce RISCV_IPI macro for SMP
Summary:
- This commit introduces RISCV_IPI macro for SMP
- Also, replace RISCV_IRQ_MSOFT with RISCV_IRQ_SOFT
- Remove duplicate irq_attach() from qemu_rv_irq.c

Impact:
- None

Testing:
- Tested with rv-virt:smp64 and maix-bit:smp on QEMU

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-10-07 14:49:29 +08:00
Masayuki Ishikawa
a7bca63b3b arch: qemu-rv: Fix build errors in chip.h for BUILD_KERNEL + SMP
Summary:
- This commit fixes build errors for BUILD_KERNEL + SMP

Impact:
- None

Testing:
- Tested with rv-virt:ksmp64 (will be added later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-10-05 17:19:13 +08:00
Masayuki Ishikawa
c4901d6f4b arch: risc-v: Introduce g_percpu_spin in riscv_percpu.c
Summary:
- This commit introduces g_percpu_spin to avoid deadlock
  in riscv_percpu.c instead of using the global spinlock.

Impact:
- None

Testing:
- Tested with rv-virt:knsh64 and rv-virt:ksmp64 (will be added later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-10-05 05:15:38 +02:00
Gustavo Henrique Nihei
73678c4839 xtensa/esp32: Allow allocation of user data in SPI RAM
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-10-04 21:32:42 +02:00
Xiang Xiao
f813fea555 Fix chip/cxd56_gnss.c:2858:7: error: label 'err' used but not defined
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-10-04 20:59:30 +02:00
Brennan Ashton
102c63be9e bl602: Add initial DMA support, including SPI over DMA. 2022-10-03 16:01:30 -03:00
Jukka Laitinen
03bce705d5 arch/risc-v/src/mpfs/mpfs_ethernet.c: Set PHY speed advert after PHY reset
This allows properly using 10/100Mbps also with 1G phy. Some gigabit PHYs
come out of reset with 1G advertisement enabled, causing other devices to
set up link with 1G. If, after this, the link is set to 10/100 on the mpfs,
the link won't work.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-10-03 19:35:30 +02:00
Masayuki Ishikawa
2fa872e304 arch: qemu-rv: Add M-timer handling for BUILD_KERNEL
Summary:
- In RISC-V, BUILD_KERNEL uses S-mode and to use M-mode timer
  we need to handle it by using OpenSBI or self-implementation.
- This commit adds M-timer self-implementation for BUILD_KERNEL.

Impact:
- qemu-rv only

Testing:
- Tested with rv-virt:knsh64 on qemu-6.2

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-10-03 23:26:11 +08:00
Masayuki Ishikawa
b3e300f8e6 arch: qemu-rv: Fix qemu_rv_start_s() for S-mode
Summary:
- I found inappropriate SET_CSR() usage in the function.
- This PR fixes this issue.

Impact:
- None

Testing:
- tested with rv-virt:knsh64

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-10-02 22:32:07 +08:00
Tiago Medicci Serrano
18c715ba92 xtensa/esp32: add initial support for I2S
Add initial support for the I2S peripheral on ESP32.
Add I2S character driver and generic I2S audio driver.
Include i2schar defconfig for ESP32-DevKitC board.
2022-09-30 17:23:17 -03:00
Xiang Xiao
e38248ee08 Return -EINVAL for the internal API
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-30 17:54:56 +02:00
Xiang Xiao
bdeaea3742 Remove the unnessary empty line after label
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-30 17:54:56 +02:00
Carlos Sanchez
6e490759d6 s32k1xx: Fix FlexIO timer register access macros 2022-09-30 23:38:59 +08:00
Carlos Sanchez
68db81ab4f s32k1xx: Allow building with debug features and no console. 2022-09-30 15:15:55 +02:00
Xiang Xiao
53dcddc9e3 arch/armv[7|8]-m: Implement up_invalidate_icache
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-30 08:07:45 +02:00
Gustavo Henrique Nihei
c0cd56a758 risc-v/esp32c3: Fix retrieval for linker-defined symbol
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-09-29 23:31:48 +02:00
chao an
6bc4baa4ca arch/makefile: preprocess link script to make configure more flexibly
Signed-off-by: chao an <anchao@xiaomi.com>
2022-09-29 17:06:47 +08:00
yinshengkai
5c9b094d65 tools: Replace mkallsyms.sh with mkallsyms.py
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2022-09-29 08:33:04 +08:00
Fotis Panagiotopoulos
bbf3f2866d Fixed non-UTF8 characters. 2022-09-28 09:38:55 +08:00
ligd
078a0486f5 armv7-a: SMP hande all cores start at same time
In SMP mode, if all cores start at same time, all from __start(),
then only primary need do initialize, so others core should wait
primary, use 'sev' let the non-primary continue to __cpuN_start().

Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-09-28 10:33:13 +09:00
wangbowen6
589647308c arm/tlsr82: move peripherals pin config to board.h
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2022-09-28 09:30:06 +08:00
Xiang Xiao
764540267e sched/clock: Rename g_system_timer to g_system_ticks
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-27 17:45:44 -03:00
Jukka Laitinen
24ea8ee3e9 arch/risc-v/src/mpfs/mpfs_ddr.c: Use DDR type selection macros to flag out code
The DDR type can be determined at compile time, remove code which is not used

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-09-28 02:09:02 +08:00
Jukka Laitinen
0ba3bc66be arch/risc-v/src/mpfs/Kconfig: Add configuration flags for DDR type selection
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-09-28 02:09:02 +08:00
Masayuki Ishikawa
0cd896b1d5 arch: risc-v: Fix license information to use the OpenSBI
Summary:
- I noticed that the OpenSBI library depends on the BSD license
- This commit fixes this issue

Impact:
- CONFIG_OPENSBI=y only

Testing:
- Build with icicle:opensbi (will be updated later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-09-27 18:29:09 +02:00