Commit Graph

22327 Commits

Author SHA1 Message Date
Filipe Cavalcanti
29ae9d1110 esp32s2: fix SPI flash and file system mounting
Copied spi flash files from risc-v
Removed old spiflash from make.defs
KConfig modifications for common spiflash
Added new spiflash entry to make.defs
S2 Board config update
Modifications working on S2. Need fix on ROM function
Board fixes
Deleted old spiflash files
Fixes for smartfs operation
Set new HAL version
Fixed wrong change on S3
2024-09-03 19:13:46 -03:00
Tiago Medicci Serrano
6df9de8788 esp32: fix initialization with PSRAM + SMP
Cache flush must be done prior to the APP cpu initalization. This,
however, must be true for the case where PSRAM is not available or
not selected. To do that, this commit flushs the cache during the
device initialization.
2024-09-02 10:24:26 -03:00
YAMAMOTO Takashi
c06a742a63 esp32: fix a crash with PSRAM + SMP
this function is called via esp_spiram_init_cache early in the boot.
2024-09-02 10:24:26 -03:00
guoshichao
4c01594d5b nuttx: remove the unnecessary -pipe build option
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-08-31 10:22:20 +08:00
Tiago Medicci Serrano
c72c66fff8 espressif: Fix deadlock in RT timer caused by critical section
This commit fixes a deadlock in `esp32s3-devkit:sta_softap`
defconfig: `spin_lock_irqsave` was being used to enter a critical
section that calls `nxsem_post`. In this case, it's recommended
to use `[enter|leave]_critical_section` to avoid deadlocks when a
context switch may happen, for instance.
2024-08-30 17:00:51 -03:00
YAMAMOTO Takashi
e8b1876f99 esp32: enable APP_CPU cache earlier
NuttX uses PSRAM, possibly using the APP_CPU cache MMU,
way before starting the APP_CPU in up_cpu_start().
Flushing the cache when launching the APP_CPU can cause
data corruptions on PSRAM.
Eg. mm_heap structures if the PSRAM is added to a heap.
2024-08-31 00:13:42 +08:00
chao an
cf4a92c81e armv8-r/gicv3: correct cpu index of irouter
interrupt routing cpu should be index not cpuset

Signed-off-by: chao an <anchao@lixiang.com>
2024-08-30 21:48:58 +08:00
YAMAMOTO Takashi
a722b74de7 esp32: cache_sram_mmu_set: update the correct register bits 2024-08-30 21:46:31 +08:00
Tiago Medicci Serrano
a916de0e14 espressif: Update HAL library reference to include debug assert
During the board bringup, the new HAL reference includes an assert
to check if the critical section flags is being stored as expected.
2024-08-30 21:41:47 +08:00
yangsong8
5a39e83c05 usbdev: extend the usb req len to size_t
Some USB controllers can receive or send multiple data packets then
generate one interrupt. This mechanism can reduce the number of data
copies. Extend req buf to accommodate this.

Signed-off-by: yangsong8 <yangsong8@xiaomi.com>
2024-08-30 01:32:02 +08:00
Ville Juven
23e0bf5953 imx9_usdhc.c: Fix build error when CONFIG_ARM64_DCACHE_DISABLE=y
priv->rxbuffer does not exist when CONFIG_ARM64_DCACHE_DISABLE=y so
references to it will create a build error -> flag / remove accesses
to it.
2024-08-30 01:13:26 +08:00
Ville Juven
a0a85e5c10 arch/arm64: Move ELF_64BIT selection to arch/Kconfig
Unify the elf file format for the whole arm64 architecture
2024-08-28 07:45:36 -04:00
Lup Yuen Lee
4c35bde3ba risc-v/bl808: Configure MMU to cache User Text, Data and Heap
This PR configures the BL808 MMU to cache the the User Text, Data and Heap. We enable the T-Head MMU Flags for Shareable, Bufferable and Cacheable, as explained in the previous PR: https://github.com/apache/nuttx/pull/13199

This PR fixes the Slow Memory Access for NuttX Apps on Ox64 BL808 SBC: https://github.com/apache/nuttx/issues/12696. With this fix, Ox64 NuttX CoreMark jumps from 19 to 1,104. (Close to Buildroot Linux CoreMark)

Modified Files:

`arch/risc-v/Kconfig`: Enabled `ARCH_MMU_EXT_THEAD` for BL808 SoC.
2024-08-28 13:47:41 +08:00
pangzhen1
dee4c63adb protected build: userspace threads will unexpectly work in privileged mode after syscall
In protected build mode, the syscall returns without setting correct value for the CONTROL register, which causes the userspace threads working in privileged mode after syscall.

Signed-off-by: pangzhen1 <pangzhen1@xiaomi.com>
2024-08-28 13:44:37 +08:00
Lup Yuen Lee
b14dc8f8ae risc-v/mmu: Configure T-Head MMU to cache User Text, Data and Heap
This PR configures the T-Head MMU to cache the the User Text, Data and Heap. We enable the MMU Flags for Shareable, Bufferable and Cacheable, as explained in this article: https://lupyuen.github.io/articles/plic3#appendix-mmu-caching-for-t-head-c906

This PR fixes the Slow Memory Access for NuttX Apps on BL808 and SG2000 SoCs: https://github.com/apache/nuttx/issues/12696. With this fix, SG2000 NuttX CoreMark jumps from 21 to 2,423. (Close to SG2000 Debian CoreMark)

We introduce a Kconfig Option: `ARCH_MMU_EXT_THEAD` ("System Type > Enable T-Head MMU extension support"). Enabling this Kconfig Option will configure the T-Head MMU to cache the User Text, Data and Heap.

This PR enables the MMU cache for only SG2000 SoC (Milk-V Duo S SBC). The next PR will apply the same settings to BL808 SoC (Pine64 Ox64 SBC).

Modified Files:

`arch/risc-v/Kconfig`: Added Kconfig Option `ARCH_MMU_EXT_THEAD` that will configure the T-Head MMU. Enabled `ARCH_MMU_EXT_THEAD` for SG2000 SoC.

`arch/risc-v/src/common/riscv_mmu.h`: Set the T-Head MMU Flags (Shareable, Bufferable and Cacheable) for User Text, Data and Heap, if `ARCH_MMU_EXT_THEAD` is enabled

`arch/risc-v/src/common/riscv_addrenv.c`: Extended the MMU Flags from 32 bits to 64 bits, to accommodate the T-Head MMU Flags

`arch/risc-v/src/common/riscv_exception.c`: Extended the MMU Flags from 32 bits to 64 bit, to accommodate the T-Head MMU Flags. This code is enabled only for MMU Paging (`CONFIG_PAGING`).
2024-08-27 19:54:58 -04:00
guoshichao
2d7c47ce16 greenhills: fix the build option warning
Warning: Unknown option "-fno-optimize-sibling-calls" ignored.  Did you mean "-mno-long-calls"?

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-08-28 01:22:03 +08:00
jinxiuxu
575c9b12ab drivers/audio: fix samp rate conversion issue
use ac_controls.hw to get the correct sample rate intead of ac_controls.b

Signed-off-by: jinxiuxu <jinxiuxu@xiaomi.com>
2024-08-27 22:00:39 +08:00
simbit18
1661a66843 [cmake]: added initial support for MSYS2
Currently concerns only arm.

tools/ci/testlist/msys2.dat:
At the moment I only added the board nucleo-l152re:nsh

.github/workflows/build.yml:
Enabled cmake for msys2
2024-08-27 21:36:12 +08:00
Ville Juven
12ba2eeb23 arm64_checkstack.c: Fix traversing of user stack when ARCH_ADDRENV=Y
Need to instantiate the correct address environment when reading from
user stack, otherwise the result is very likely a crash
2024-08-27 21:34:43 +08:00
Ville Juven
963c5e8e52 arm64/imx9: Force 64-bit ELF format
The format is always 64-bits
2024-08-27 07:39:26 -04:00
SPRESENSE
2cc9221c09 arch: cxd56xx: Add logic for i2c reset
Add ARCH_HAVE_I2CRESET configration to ARCH_CHIP_CXD56XX
and implement i2c reset function.
2024-08-27 12:29:46 +02:00
SPRESENSE
de8829f8cd arch: cxd56xx: Fix SCU sensor data format
Add offset setting for sensor data to be written to SCU math function.
Fix comments in function descriptions.
2024-08-27 12:28:50 +02:00
yangguangcai
352e3a6873 armv7-a timer:fix timer overflow.
Signed-off-by: yangguangcai <yangguangcai@xiaomi.com>
2024-08-26 17:50:47 -04:00
yanghuatao
33ddf1a297 toolchain/ghs: Fix green hills toolchain build Vela warnings
ccarm: Warning: Option "-fomit-frame-pointer" not supported in this product
ccarm: Warning: Unknown option "-Wno-cpp" ignored.  Did you mean "--nocpp"?
ccarm: Warning: Unknown option "-pipe" passed to linker
ccarm: Warning: Unknown option "-Wno-psabi" ignored.  Did you mean "-Wno-convert64"?
ccarm: Warning: Option "-fomit-frame-pointer" not supported in this product
ccarm: Warning: Unknown option "-Wno-cpp" ignored.  Did you mean "--nocpp"?
ccarm: Warning: Unknown option "-pipe" passed to linker
[asarm] (warning ) unknown option: -mimplicit-it=always
Warning: Unknown option "-pipe" passed to linker
[asarm] (warning ) unknown option: -mthumb
[asarm] (warning ) unknown option: -mimplicit-it=always
[asarm] (warning ) unknown option: -mthumb
[asarm] (warning ) unknown option: -mimplicit-it=always
[asarm] (warning ) unknown option: -mthumb
[asarm] (warning ) unknown option: -mimplicit-it=always
[asarm] (warning ) unknown option: -mthumb
[asarm] (warning ) unknown option: -mimplicit-it=always
[asarm] (warning ) unknown option: -mthumb
[asarm] (warning ) unknown option: -mimplicit-it=always

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2024-08-27 01:56:34 +08:00
guoshichao
3bb30231a9 greenhills: fix the file build path error
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-08-27 01:56:34 +08:00
guoshichao
e5f40db601 greenhills: fix the "etc/init.d/rc.sysinit" file preprocess error
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-08-27 01:56:34 +08:00
guoshichao
c2d26988fd greenhills: fix double-precision float operation running error
since not all Armv7-m platform support double-precision floating
operations, so we add an extra option that help those specific platform
could define the single-precision floating operations.
for example, qemu-mps platform(armv7-m) support double-precision
floating operations, so we do not need to open
CONFIG_ARM_FPU_SINGLE_HARDWARE build options;
but for fc7300 platform(armv7-m) only support single-precision floating
operations, so if we pass "-fhard" build option to "ghs" compiler, then
the following instruction will be generated:
vcvt.f64.s32    d9, s18
which will fail to execute on fc7300 platform.
with "-fsingle" build option, the "ghs" compiler will generate hardware
instruction for single-precision floating operation, and generate
software instruction for double-precision floating operation.

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-08-27 01:56:34 +08:00
guoshichao
90a6ced9c1 arch/arm/toolchain: add --entry_std LDFLAGS for different toolchain
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-08-27 01:56:34 +08:00
pangzhen1
d2ec034ada support inputting multiple ldscript files when linking the nuttx.bin
To support greenhill compilation, LDFLAGS removes the code that adds -T through addprefix to ARCHSCRIPT(greenhill requires a space between -T and ldscript files, but addprefix didn't do it). However,if we modified like this, when ARCHSCRIPT has more than one ldscript, the -T is only added to the first ldscript, but not to the following ldscripts, which results in a warning when linking.
To solve this problem, we can just add a space after $(SCRIPT_OPT) when using addprefix, instead of deleting addprefix.

Signed-off-by: pangzhen1 <pangzhen1@xiaomi.com>
2024-08-27 01:56:34 +08:00
guoshichao
67f0b5131b arch/arm/toolchain: add greenhills toolchain config
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-08-27 01:56:34 +08:00
guoshichao
dd8b630b0d nuttx: add GREENHILLS compiler config option
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-08-27 01:56:34 +08:00
Xiang Xiao
fcb3e84c24 can: Merge netpacket/can.h into nuttx/can.h
To align with the layout of Linux can header file.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-08-26 05:05:31 -04:00
Windrow14
cc8d453b5a arch/xtensa/src/esp32s3/esp32s3_sdmmc.c: wait for command done event also on error response
Wait for CMDDONE in esp32s3_waitresponse even an error response is received.
Otherwise, the CMDDONE event of this command will disrupt later command.

Signed-off-by: Yinzhe Wu <Yinzhe.Wu@sony.com>
Reviewed-by: Yuezhang Mo <Yuezhang.Mo@sony.com>
Reviewed-by: Jacky Cao <Jacky.Cao@sony.com>
Tested-by: Yinzhe Wu <Yinzhe.Wu@sony.com>
2024-08-26 13:44:57 +08:00
yinshengkai
84333881d7 mm: add mm_largest api to get the current largest available memory block
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-08-25 23:09:28 +08:00
yinshengkai
49d1b4198f mm: add memory pressure notification support
Add mm_heap_free interface to pass remaining memory to memory pressure

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-08-25 23:09:28 +08:00
yanghuatao
fac44ab8aa nuttx/mps2: Support NuttX running on qemu cortex-m7
Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2024-08-25 22:56:46 +08:00
Xiang Xiao
d3be25d90c arch/arm: Add the support of MPS2 AN386 and AN500
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-08-25 22:56:46 +08:00
hujun5
1d6a099180 irq: remove restore_critical_section in irq
Only in the non-critical region, nuttx can the respond to the irq and not hold the lock
When returning from the irq, there is no need to check whether the lock needs to be released
we also need keep restore_critical_section in svc call

test:
Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
   -machine virt,virtualization=on,gic-version=3 \
   -net none -chardev stdio,id=con,mux=on -serial chardev:con \
   -mon chardev=con,mode=readline -kernel ./nuttx

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-08-25 21:14:19 +08:00
Petro Karashchenko
d499ac9d58 nuttx: fix multiple 'FAR', 'CODE' and style issues
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-08-25 19:22:15 +08:00
Petro Karashchenko
7b18f9d19f nuttx: add missing 'FAR' and fix style issues
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-08-25 19:22:15 +08:00
Petro Karashchenko
a8ec8b8cd2 arch/x86_64: remove 'ul' sufix from shift value
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-08-25 19:22:15 +08:00
Petro Karashchenko
b7cbe16fed arch/x86_64: remove redundant init
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-08-25 19:22:15 +08:00
Petro Karashchenko
f40b09cbc9 style: remove redundant spaces
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-08-25 19:22:15 +08:00
Petro Karashchenko
d252b6229f nuttx: use sizeof instead of define or number in snprintf
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-08-25 19:22:15 +08:00
Kevin Zhou
bf57047429 xtensa/esp32s3: Separate address and command flag for QSPI DMA transfer 2024-08-24 11:31:35 +08:00
Yanfeng Liu
634ee5b1f6 board/maix-bit: add cmake support
This adds initial CMake support for `maix-bit` device.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-24 11:08:25 +08:00
Ville Juven
29f8648ecc arm64: Initial implementation of CONFIG_BUILD_KERNEL
This is the initial version for kernel mode build on the arm64 platform.
It works much in the same way as the risc-v implementation so any
highlights can be read from there.

Features that have been tested working:
- Creating address environments
- Loading init (nsh) from elf file
- Booting to nsh
- Starting other processes from nsh
- ostest runs to completion

Features that are not tested / do not work:
- SHM / shared memory support
- Kernel memory mapping (MM_KMAP)
- fork/vfork

An example qemu target is provided as a separate patch:
tools/configure.sh qemu-armv8a:knsh
2024-08-23 10:26:34 -03:00
Ville Juven
7f228b1554 arm64/barriers.h: Generalize barrier macros
Make it possible to define arguments for barriers
2024-08-23 10:26:34 -03:00
Ville Juven
52781221b3 arm64_sync_exc: Use temporaries x9/x10 instead of x0/x1
Why? Because this allows optimizing the user system call path in such
a way that the parameter registers don't have to be read from the saved
integer register context when the system call is executed.
2024-08-23 10:26:34 -03:00
wangchen
f0cdaca660 nuttx-names.in:add popen & pclose assign to glibc interface
Signed-off-by: wangchen <wangchen41@xiaomi.com>
2024-08-23 20:20:25 +08:00