Gregory Nutt
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6324df44e8
|
SAMA5 Timer/counter repair: Missing sem_post() caused a hang
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2014-08-09 18:34:52 -06:00 |
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Gregory Nutt
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d1d1d76189
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SAMA5: Use the one-shot and free-running timers to implement tickless OS support for SAMA5
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2014-08-09 17:14:51 -06:00 |
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Gregory Nutt
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569d5d7218
|
SAMA5 free-running timer: Add support for a free-running timer wrapper around the low-level timer/counter logic.
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2014-08-09 16:43:48 -06:00 |
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Gregory Nutt
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acb05460d0
|
SAMA5 oneshot: Some clean-up and correction to the initial implementation
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2014-08-09 16:42:04 -06:00 |
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Gregory Nutt
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d8aa6c01bd
|
SAMA5 timer/counter: Add support for a one-shot timer wrapper around the low-level timer/counter logic. This also involved several changes that rippled into the ADC driver (untested).
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2014-08-09 15:27:55 -06:00 |
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Gregory Nutt
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5803fb78b8
|
SAMA5 T/C: Can now handle non-constant BOARD_MCK_FREQUENCY. Also now supports methods to attach user interrupt handlers
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2014-08-09 10:30:45 -06:00 |
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Gregory Nutt
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da0de3284e
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Fix errors in documentation and comments related to the Tickless OS. From Vijay Kumar
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2014-08-09 06:41:38 -06:00 |
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Gregory Nutt
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e1769b22f1
|
Remove os_internal.h it has been replace by several new header files under sched/. There have been some sneak inclusion paths via os_internal.h, so expect a few compilation errors for some architectures
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2014-08-08 18:39:28 -06:00 |
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Gregory Nutt
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d798dd37a7
|
Replace os_internal.h with sched/sched.h in files that actually reference something in sched.h
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2014-08-08 17:53:55 -06:00 |
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Gregory Nutt
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23a334c066
|
Move task control files from sched/ to sched/task
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2014-08-08 16:44:08 -06:00 |
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Gregory Nutt
|
d4b56eb3cc
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Move clock functions from sched/ to sched/clock
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2014-08-08 14:43:02 -06:00 |
|
Gregory Nutt
|
85e8117062
|
Move interrupt dispatch logic from sched/ to sched/irq
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2014-08-08 14:31:15 -06:00 |
|
Gregory Nutt
|
c9661ad5a7
|
Change all time conversions. Yech. New timer units in microseconds breaks all existing logic that used milliseconds in the conversions. Something likely got broken doing this, probably because I confused a MSEC2TICK conversion with a TICK2MSEC conversion. Also, the tickless OS no appears fully functional and passes the OS test on the simulator with no errors
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2014-08-07 18:00:38 -06:00 |
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Gregory Nutt
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0aa7209765
|
Change CONFIG_MSEC_PER_TICK to CONFIG_USEC_PER_TICK. This gives more options for system timers in general, but more importantly, let's us realize higher resolution for the case of CONFIG_SCHED_TICKLESS=y -- of course, at the risk of some new interger overvflow problems
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2014-08-07 13:42:47 -06:00 |
|
Gregory Nutt
|
520a51a3e1
|
Implements the tickless OS
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2014-08-07 11:39:16 -06:00 |
|
Gregory Nutt
|
dc48bec019
|
Add support for a simulated interval timer support verification of the tickless OS.
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2014-08-06 18:29:29 -06:00 |
|
Gregory Nutt
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cc7cb0f031
|
Don't build in sched_processtimer.c if CONFIG_SCHED_TICKLESS is selected.
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2014-08-06 18:27:10 -06:00 |
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Gregory Nutt
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0452b1555b
|
if CONFIG_SCHED_TICKLESS is defined, then the global variable g_system_timer does not exist
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2014-08-06 18:26:16 -06:00 |
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Gregory Nutt
|
736d3c169a
|
Rename up_timerinit() to up_timer_initailize(); Add prototypes for candidate interfaces for the tickless OS; Don't build existing timer initialization logic if CONFIG_SCHED_TICKLESS is defined.
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2014-08-06 16:26:01 -06:00 |
|
Gregory Nutt
|
7b9c44101d
|
SAMA5D3 HSMCI: TX DMA is again disabled
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2014-08-05 07:07:39 -06:00 |
|
Gregory Nutt
|
159bcc255d
|
SAMA5 PCK: Add Main clock as an option for the PCK clock source
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2014-08-03 10:17:50 -06:00 |
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Gregory Nutt
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c75bf6d741
|
SAMA5 SSC: Verify that the requested bit width is supported. Correct some alignment tests that depend upon the data bit width.
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2014-08-02 14:26:49 -06:00 |
|
Gregory Nutt
|
83dab03576
|
SAMA5 WM8904: Fix errors in programmable clock output configuration
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2014-08-01 15:18:58 -06:00 |
|
Gregory Nutt
|
805a02965c
|
SAMA5 SSC: Start Delay is now configurable
|
2014-08-01 14:10:37 -06:00 |
|
Gregory Nutt
|
50bd2ba46c
|
SAMA5 SSC: Frame Synch Delay is now configurable
|
2014-08-01 12:25:31 -06:00 |
|
Gregory Nutt
|
0b4090df0d
|
SAMA5D SSC: Needs to account for data offset in audio buffer.
|
2014-07-31 19:14:24 -06:00 |
|
Gregory Nutt
|
c657139b30
|
SAMA5D3X-EK: Add support for the WM8904 audio CODEC
|
2014-07-31 11:14:57 -06:00 |
|
Gregory Nutt
|
24af676c05
|
SAMA5: Changes needed for a clean SAMA5D3 build after all of the recent SAMA5D4 changes.
|
2014-07-31 11:09:56 -06:00 |
|
Gregory Nutt
|
276cc44878
|
SAMA5 HSMCI: e-enable TX DMA and verify that DMA writes to the SD card are functional. They are so now TX DMA is re-enabled in the driver. This might affect the SAMA5D3 platforms where the TX DMA problem was found. The SAMA4D3 and 4 use the same HSMCI driver. Much has change since then and it is not surprising that DMA is now functional. However, the has not be re-verified on the SAMA5D3 which has a different DMA controller.
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2014-07-30 11:20:06 -06:00 |
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Gregory Nutt
|
4df0fbec04
|
SAMA5D HSMCI: Fix a problem on card insertion/removal callback handling. Interrupts were being disable so that the callbacks occurred with interrupts disabled. This resulted in loss of some interrupts and some not-so-good behaviors. The solution is to perform all callbacks on the work thread unconditionally (2014-7-29).
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2014-07-30 10:19:41 -06:00 |
|
Gregory Nutt
|
70be3bae16
|
SAMA5D HSMCI: Add method to do RX transfer without DMA. The 8-byte SCR transfer was failing silently with the DMA transfer, leaving the SD card in single bit mode
|
2014-07-29 21:13:28 -06:00 |
|
Gregory Nutt
|
2861636015
|
Cosmetic changes to comments
|
2014-07-29 07:17:01 -06:00 |
|
Gregory Nutt
|
53930d5531
|
SAMA5D-EK: Correct system timer frequency. Input clock is MCK/2, not MCK
|
2014-07-29 07:12:36 -06:00 |
|
Gregory Nutt
|
1b6eec572d
|
Cosmetic changes to comments
|
2014-07-29 07:11:16 -06:00 |
|
Gregory Nutt
|
8c2b458d75
|
Fixes to last SAMA5 PMIC checkin
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2014-07-28 17:09:37 -06:00 |
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Gregory Nutt
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d450993f2e
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LPC17xx: DC updates from Max. Also fixes some syntax errors that I introduced in the last commit.
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2014-07-28 07:23:49 -06:00 |
|
Gregory Nutt
|
100bba42be
|
ARM: Move L2 cache initialization to much later in the sequence
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2014-07-27 10:03:33 -06:00 |
|
Gregory Nutt
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c523abdc62
|
ARMv7-A L2 Cache currently depends on EXPERIMENTAL because it does not yet work properly
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2014-07-26 18:48:54 -06:00 |
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Gregory Nutt
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4446d6e98d
|
ARMv7 L2 Cache: Minor bugfixes/improvements
|
2014-07-26 18:48:26 -06:00 |
|
Gregory Nutt
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0519118de2
|
Enables cache early in boot-up sequence
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2014-07-26 18:48:00 -06:00 |
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Gregory Nutt
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d09ee81320
|
Change naming from cp_XYZ_cache() to arch_XYP_cache() so that all cache operations will pick up L2 support if it is enabled
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2014-07-26 18:47:33 -06:00 |
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Gregory Nutt
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0d83d198de
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New cache.h file. Renames cp15_XYZ_cache() to arch_XYZ_cache() and addes L2 cache support if L2 cache is enabled
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2014-07-26 18:46:52 -06:00 |
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Gregory Nutt
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ca3776a7ec
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Rename ARMv7-A cache.h to cp15_cache.h. Things will be broken on this commit until I get the new cache.h in place.
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2014-07-26 16:54:19 -06:00 |
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Gregory Nutt
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ec70cfe44c
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arch/arm/src/armv7-a/arm_l2cc_pl310.c, l2cc.h, l2cc_pl310.h, Kconfig: Add initiali support for the ARM L2CC-PL310 L2 cache.
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2014-07-26 16:50:08 -06:00 |
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Gregory Nutt
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be198337f7
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ARMv7-A: L2CC PL310 address filtering is an optional feature
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2014-07-25 19:46:09 -06:00 |
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Gregory Nutt
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ef5bfd72a6
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ARMv7-A: Add missing L2CC PL310 bit definitions
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2014-07-25 19:41:35 -06:00 |
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Gregory Nutt
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597c9839cc
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rch/arm/armv7-a/l2cc_pl310.h: Move arch/arm/sama5/chip/sam_l2cc.h to arch/arm/armv7-a/l2cc_pl310.h. Adjust the two corresponding Kconfig files as well.
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2014-07-25 17:25:17 -06:00 |
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Gregory Nutt
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47752a35c1
|
3rd time is a charm. Max is right, the initial priority setting should be NVIC_SYSH_PRIORITY_MIN
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2014-07-24 16:51:07 -06:00 |
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Gregory Nutt
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8718dad9c8
|
Oops, should have been NVIC_SYSH_PRIORITY_DEFAULT
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2014-07-24 16:42:15 -06:00 |
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Gregory Nutt
|
7f5b88dbcd
|
LPC17 Ethernet: Added option to use the kernel worker thread to do most of the workload with CONFIG_NET_WORKER_THREAD option in Kconfig. Eliminated a problem with PHY DP83848C : it doesn't need a specific initialization on mbed. Critical bufix: From time to time (after some hours) the Ethernet receiver would lose one receive interrupt and the IP stack never recover because there is no receive watchdog as the transmit watchdog. From Max
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2014-07-24 16:39:18 -06:00 |
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Gregory Nutt
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fdff663e57
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Added burstmode ADC conversion mode, with CONFIG_ADC_BURSTMODE option in Kconfig. From Max
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2014-07-24 16:23:31 -06:00 |
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Gregory Nutt
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ab572091c5
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Mostly cosmetic changes from Max
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2014-07-24 16:00:21 -06:00 |
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Gregory Nutt
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ad3626e61a
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Eliminate warnings. From Max
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2014-07-24 15:50:37 -06:00 |
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Gregory Nutt
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6dcb524d16
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Correct the initial value of the BASEPRI register. This was apparently never being initialized. From Max
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2014-07-24 15:37:13 -06:00 |
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Gregory Nutt
|
0fcc0adaa2
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Fix a recently introduced typo that was being masked by some bad conditional compilation
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2014-07-22 11:45:14 -06:00 |
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Gregory Nutt
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17abe05357
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Update ChangeLog
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2014-07-22 07:25:01 -06:00 |
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Gregory Nutt
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3bb6a877fd
|
STM32 OTGFS device: Various changes to try to reduce that amount of time in interrupts handles and with interrupts disbled. Needs verification on other platforms. From Petteri Aimonen
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2014-07-22 07:23:17 -06:00 |
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Gregory Nutt
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f76cac2773
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Fix typos in the STM32 DAC header file. From Petteri Aimonen
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2014-07-22 07:13:33 -06:00 |
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Gregory Nutt
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121c00036d
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SAMA5D4 XDMAC: Never sets a channel as secure. Will probably have to revisit this
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2014-07-21 17:46:35 -06:00 |
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Gregory Nutt
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df65c5e4df
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SAMA5D4: Fix some HSMCI issues when XDMAC0 is enabled
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2014-07-21 17:45:48 -06:00 |
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Gregory Nutt
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b9f1fbeb6c
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SAMA5 HSMCI: Correct multi-block DMA setup; Fixes related to DMA timeout. Still problems with HSMCI DMA via XDMAC
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2014-07-21 16:49:56 -06:00 |
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Gregory Nutt
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f508c07b97
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SAMA5 XDMAC: Missing some CUBC bits
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2014-07-21 16:47:16 -06:00 |
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Gregory Nutt
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43b214addd
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SAMA4D5 HSMCI: Set burst size to 1, sample DMA registers on timeout, and don't return from transfer until BOTH the HSMCI transfer and DMA complete
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2014-07-21 13:24:55 -06:00 |
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Gregory Nutt
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3b24da2d7c
|
XDMAC register sampling missed CIM register; Should not set SWREQ bit in DMA setup
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2014-07-21 13:23:36 -06:00 |
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Gregory Nutt
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e202c8e9b2
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Fix a commented out assertion
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2014-07-20 17:06:55 -06:00 |
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Gregory Nutt
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e8c030a833
|
Fix typos in comments
|
2014-07-20 13:09:47 -06:00 |
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Gregory Nutt
|
7fa1eec246
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SAMA5D4-EK: PIO Schmitt trigger logic backward
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2014-07-20 13:04:30 -06:00 |
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Gregory Nutt
|
f4bcb730d2
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WM8904 w/NxPlayer: Fix some compile errors and warnings with debug enabled
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2014-07-20 09:17:36 -06:00 |
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Gregory Nutt
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54d441b5c9
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SAMA5D ADC: Fix some typos in conditional compilation
|
2014-07-19 13:56:48 -06:00 |
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Gregory Nutt
|
6ece3d8378
|
SAMA5 SCK: The SAMA5D3 does things a little differently
|
2014-07-19 13:55:53 -06:00 |
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Gregory Nutt
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d8f85d1caa
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SAMA5 PCK: Add support for the slow clock as the PCK clock source
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2014-07-19 13:55:08 -06:00 |
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Gregory Nutt
|
c74531e014
|
SAMA5: Update slow clock logic. Things work a little differently on the SAMA5D3
|
2014-07-19 13:25:59 -06:00 |
|
Gregory Nutt
|
bad3ad58cb
|
SAMA5: Add slow clock support
|
2014-07-19 13:07:55 -06:00 |
|
Gregory Nutt
|
6d9f9e37bf
|
SAMA5D4-EK: Add WM8904 initialization logic
|
2014-07-19 11:58:53 -06:00 |
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Gregory Nutt
|
3a6ea3642f
|
SAMA5 LCDC: Back out the delay kludge. Increase the LCDC input clock from MCK to 2*MCK was sufficient for all timing instbility problems
|
2014-07-12 11:24:14 -06:00 |
|
Gregory Nutt
|
8d1feb7a54
|
SAMA5D4-EK LCDC: Change source clock to 2*Mck seems to solve stability issues
|
2014-07-12 09:45:05 -06:00 |
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Gregory Nutt
|
253110bbf1
|
SAMA5D4-EK LCDC: Adding a delay after enabling the LCD solves lots of start-up timing issues
|
2014-07-12 08:05:22 -06:00 |
|
Gregory Nutt
|
3384906cdd
|
Lpc17xx Ethernet: Comment out an assertion that is reported to first inappropriately. From Max
|
2014-07-11 12:25:11 -06:00 |
|
Gregory Nutt
|
95df6bd3de
|
SAMA5D4-EK LCD: Actual hardware with appears to be RGB888
|
2014-07-10 12:23:41 -06:00 |
|
Gregory Nutt
|
89024f3698
|
SAMA5D4-EK: LCDC works (with a few color problems)
|
2014-07-10 12:03:10 -06:00 |
|
Gregory Nutt
|
60e64ae93d
|
Don't have to set SDA high initially in I2C reset because that is done by the pin configuration
|
2014-07-09 17:17:32 -06:00 |
|
Gregory Nutt
|
981c1ebf55
|
SAMA5 PIO: Fix a typo in Schmitt trigger configuration; Configure pin as a a vanilla input first so that final pin configuration is more read-able (i.e., easier to debug)
|
2014-07-09 17:16:43 -06:00 |
|
Gregory Nutt
|
27be48a1ba
|
SAMA5 I2C Reset: More changes... still does not work right
|
2014-07-09 15:09:06 -06:00 |
|
Gregory Nutt
|
c2ca4be4f5
|
SAMA5 TWI: Some restructured needed by up_i2creset. Also timeout needs to vary with the size of the transfer and if debug is on or not
|
2014-07-09 13:39:10 -06:00 |
|
Gregory Nutt
|
84056291e8
|
Use sam_pio_forceclk() so that we can read the current state of an open-drain output in the TWI reset logic.
|
2014-07-09 11:31:21 -06:00 |
|
Gregory Nutt
|
a966e4f30b
|
Add a new interface sam_pio_forceclk() that can be used to force PIO clocking on. I am afraid I was too conservative with PIO clocking in the initial design; this is the price
|
2014-07-09 11:26:07 -06:00 |
|
Gregory Nutt
|
e9362128bd
|
SAMA5 TWI: Add support for up_i2creset
|
2014-07-09 09:51:28 -06:00 |
|
Gregory Nutt
|
a7ec464d48
|
SAMA5D4 LCDC: Adapt the SAMA5D3 LCDC driver to work with the SAMA5D4 which has no hardware cursor
|
2014-07-08 12:45:16 -06:00 |
|
Gregory Nutt
|
e76f10ceac
|
SAMA5D3/4 HEAP: Add a configuration option to reserve DRAM for a framebuffer when executing out of DRAM.
|
2014-07-08 12:43:38 -06:00 |
|
Gregory Nutt
|
befcb1c961
|
Fix some cloned errors in SAM GPIO interrupt setup
|
2014-07-07 15:54:37 -06:00 |
|
Gregory Nutt
|
ca43955541
|
SAMA5D3/4: Fix two issues associated with PIO interrupts
|
2014-07-07 14:16:29 -06:00 |
|
Gregory Nutt
|
95bbdb675b
|
SAMA5D3/4 I2C: Test for read or write operation was reversed. How could this have worked before?
|
2014-07-07 09:54:43 -06:00 |
|
Gregory Nutt
|
0d14befb88
|
SAM3/4: Fix compile of sam_aes.c if CONFIG_CRYPTO_AES is defined. rom Max Nekludov
|
2014-07-07 08:03:18 -06:00 |
|
Gregory Nutt
|
4afc23d16d
|
maXTouch: Fix test of I2C_TRANSFER return value
|
2014-07-06 08:51:38 -06:00 |
|
Gregory Nutt
|
c5fc24e110
|
NET: Standardize naming of all protocal header lengths
|
2014-07-05 13:04:48 -06:00 |
|
Gregory Nutt
|
60246e613b
|
NET: emoved all includes of uip.h; added includes of ip.h wherever needed. Tried to fix problems of the now missing sneak inclusions because uip.h was removed. There are probably a few of these that were missed.
|
2014-07-04 19:13:08 -06:00 |
|
Gregory Nutt
|
0bb153b8cb
|
Remove all inclusion of uip.h
|
2014-07-04 16:58:22 -06:00 |
|
Gregory Nutt
|
cce35ce975
|
NET: More renaming
|
2014-07-04 15:40:49 -06:00 |
|
Gregory Nutt
|
858587d633
|
AMA5 OHCI: Pointers to allocated port values were not being nullified after being deallocated. This caused some assertions when debug was enabled
|
2014-07-04 08:17:14 -06:00 |
|
Gregory Nutt
|
1657e6296b
|
Move crypto header files from include/crypto to include/nuttx/crypto
|
2014-07-03 18:35:08 -06:00 |
|