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2328 Commits

Author SHA1 Message Date
Gustavo Henrique Nihei
330eff36d7 sourcefiles: Fix relative path in file header 2021-03-09 23:18:28 +08:00
David Sidrane
abda656076 stm32:Ethernet Fix too big frames 2021-03-06 03:07:58 -08:00
Fotis Panagiotopoulos
f423403dfa stm32_wwdg debug log formatting 2021-03-03 19:02:04 -08:00
Nathan Hartman
3ac61053ce arch/stm32, arch/stm32f7: Fix nxstyle errors 
arch/arm/src/stm32/hardware/stm32_dma2d.h,
arch/arm/src/stm32/hardware/stm32_ltdc.h,
arch/arm/src/stm32/stm32_dma2d.c,
arch/arm/src/stm32/stm32_ltdc.c,
arch/arm/src/stm32f7/hardware/stm32_dma2d.h,
arch/arm/src/stm32f7/hardware/stm32_ltdc.h,
arch/arm/src/stm32f7/stm32_dma2d.c, and
arch/arm/src/stm32f7/stm32_ltdc.c:

    * Fix nxstyle "mixed case identifier" errors for the
      following identifiers:

      DMA2D_xGPFCCR_ALPHA         -> DMA2D_XGPFCCR_ALPHA
      DMA2D_xGPFCCR_AM            -> DMA2D_XGPFCCR_AM
      DMA2D_xGPFCCR_CCM           -> DMA2D_XGPFCCR_CCM
      DMA2D_xGPFCCR_CM            -> DMA2D_XGPFCCR_CM
      DMA2D_xGPFCCR_CS            -> DMA2D_XGPFCCR_CS
      DMA2D_xGPFCCR_START         -> DMA2D_XGPFCCR_START
      LTDC_LxBFCR_BF1             -> LTDC_LXBFCR_BF1
      LTDC_LxBFCR_BF2             -> LTDC_LXBFCR_BF2
      LTDC_LxCFBLR_CFBLL          -> LTDC_LXCFBLR_CFBLL
      LTDC_LxCFBLR_CFBP           -> LTDC_LXCFBLR_CFBP
      LTDC_LxCR_CLUTEN            -> LTDC_LXCR_CLUTEN
      LTDC_LxCR_COLKEN            -> LTDC_LXCR_COLKEN
      LTDC_LxCR_LEN               -> LTDC_LXCR_LEN
      LTDC_LxWHPCR_WHSPPOS        -> LTDC_LXWHPCR_WHSPPOS
      LTDC_LxWHPCR_WHSTPOS        -> LTDC_LXWHPCR_WHSTPOS
      LTDC_LxWVPCR_WVSPPOS        -> LTDC_LXWVPCR_WVSPPOS
      LTDC_LxWVPCR_WVSTPOS        -> LTDC_LXWVPCR_WVSTPOS
      STM32_LTDC_LxWHPCR_WHSTPOS  -> STM32_LTDC_LXWHPCR_WHSTPOS
      STM32_LTDC_LxWVPCR_WVSTPOS  -> STM32_LTDC_LXWVPCR_WVSTPOS
      STM32_LTDC_Lx_BYPP          -> STM32_LTDC_LX_BYPP
      DMA2D_xGCOLR_BLUE           -> DMA2D_XGCOLR_BLUE
      DMA2D_xGCOLR_BLUE_MASK      -> DMA2D_XGCOLR_BLUE_MASK
      DMA2D_xGCOLR_BLUE_SHIFT     -> DMA2D_XGCOLR_BLUE_SHIFT
      DMA2D_xGCOLR_GREEN          -> DMA2D_XGCOLR_GREEN
      DMA2D_xGCOLR_GREEN_MASK     -> DMA2D_XGCOLR_GREEN_MASK
      DMA2D_xGCOLR_GREEN_SHIFT    -> DMA2D_XGCOLR_GREEN_SHIFT
      DMA2D_xGCOLR_RED            -> DMA2D_XGCOLR_RED
      DMA2D_xGCOLR_RED_MASK       -> DMA2D_XGCOLR_RED_MASK
      DMA2D_xGCOLR_RED_SHIFT      -> DMA2D_XGCOLR_RED_SHIFT
      DMA2D_xGOR                  -> DMA2D_XGOR
      DMA2D_xGOR_MASK             -> DMA2D_XGOR_MASK
      DMA2D_xGOR_SHIFT            -> DMA2D_XGOR_SHIFT
      DMA2D_xGPFCCR_ALPHA_MASK    -> DMA2D_XGPFCCR_ALPHA_MASK
      DMA2D_xGPFCCR_ALPHA_SHIFT   -> DMA2D_XGPFCCR_ALPHA_SHIFT
      DMA2D_xGPFCCR_AM_MASK       -> DMA2D_XGPFCCR_AM_MASK
      DMA2D_xGPFCCR_AM_SHIFT      -> DMA2D_XGPFCCR_AM_SHIFT
      DMA2D_xGPFCCR_CM_MASK       -> DMA2D_XGPFCCR_CM_MASK
      DMA2D_xGPFCCR_CM_SHIFT      -> DMA2D_XGPFCCR_CM_SHIFT
      DMA2D_xGPFCCR_CS_MASK       -> DMA2D_XGPFCCR_CS_MASK
      DMA2D_xGPFCCR_CS_SHIFT      -> DMA2D_XGPFCCR_CS_SHIFT
      LTDC_LxBFCR_BF1_MASK        -> LTDC_LXBFCR_BF1_MASK
      LTDC_LxBFCR_BF1_SHIFT       -> LTDC_LXBFCR_BF1_SHIFT
      LTDC_LxBFCR_BF2_MASK        -> LTDC_LXBFCR_BF2_MASK
      LTDC_LxBFCR_BF2_SHIFT       -> LTDC_LXBFCR_BF2_SHIFT
      LTDC_LxCACR_CONSTA          -> LTDC_LXCACR_CONSTA
      LTDC_LxCACR_CONSTA          -> LTDC_LXCACR_CONSTA
      LTDC_LxCACR_CONSTA_MASK     -> LTDC_LXCACR_CONSTA_MASK
      LTDC_LxCACR_CONSTA_SHIFT    -> LTDC_LXCACR_CONSTA_SHIFT
      LTDC_LxCFBLNR_LN            -> LTDC_LXCFBLNR_LN
      LTDC_LxCFBLNR_LN            -> LTDC_LXCFBLNR_LN
      LTDC_LxCFBLNR_LN_MASK       -> LTDC_LXCFBLNR_LN_MASK
      LTDC_LxCFBLNR_LN_SHIFT      -> LTDC_LXCFBLNR_LN_SHIFT
      LTDC_LxCFBLR_CFBLL_MASK     -> LTDC_LXCFBLR_CFBLL_MASK
      LTDC_LxCFBLR_CFBLL_SHIFT    -> LTDC_LXCFBLR_CFBLL_SHIFT
      LTDC_LxCFBLR_CFBP_MASK      -> LTDC_LXCFBLR_CFBP_MASK
      LTDC_LxCFBLR_CFBP_SHIFT     -> LTDC_LXCFBLR_CFBP_SHIFT
      LTDC_LxCKCR_CKBLUE          -> LTDC_LXCKCR_CKBLUE
      LTDC_LxCKCR_CKBLUE          -> LTDC_LXCKCR_CKBLUE
      LTDC_LxCKCR_CKBLUE_MASK     -> LTDC_LXCKCR_CKBLUE_MASK
      LTDC_LxCKCR_CKBLUE_SHIFT    -> LTDC_LXCKCR_CKBLUE_SHIFT
      LTDC_LxCKCR_CKGREEN         -> LTDC_LXCKCR_CKGREEN
      LTDC_LxCKCR_CKGREEN         -> LTDC_LXCKCR_CKGREEN
      LTDC_LxCKCR_CKGREEN_MASK    -> LTDC_LXCKCR_CKGREEN_MASK
      LTDC_LxCKCR_CKGREEN_SHIFT   -> LTDC_LXCKCR_CKGREEN_SHIFT
      LTDC_LxCKCR_CKRED           -> LTDC_LXCKCR_CKRED
      LTDC_LxCKCR_CKRED           -> LTDC_LXCKCR_CKRED
      LTDC_LxCKCR_CKRED_MASK      -> LTDC_LXCKCR_CKRED_MASK
      LTDC_LxCKCR_CKRED_SHIFT     -> LTDC_LXCKCR_CKRED_SHIFT
      LTDC_LxCLUTWR_BLUE          -> LTDC_LXCLUTWR_BLUE
      LTDC_LxCLUTWR_BLUE          -> LTDC_LXCLUTWR_BLUE
      LTDC_LxCLUTWR_BLUE_MASK     -> LTDC_LXCLUTWR_BLUE_MASK
      LTDC_LxCLUTWR_BLUE_SHIFT    -> LTDC_LXCLUTWR_BLUE_SHIFT
      LTDC_LxCLUTWR_CLUTADD       -> LTDC_LXCLUTWR_CLUTADD
      LTDC_LxCLUTWR_CLUTADD       -> LTDC_LXCLUTWR_CLUTADD
      LTDC_LxCLUTWR_CLUTADD_MASK  -> LTDC_LXCLUTWR_CLUTADD_MASK
      LTDC_LxCLUTWR_CLUTADD_SHIFT -> LTDC_LXCLUTWR_CLUTADD_SHIFT
      LTDC_LxCLUTWR_GREEN         -> LTDC_LXCLUTWR_GREEN
      LTDC_LxCLUTWR_GREEN         -> LTDC_LXCLUTWR_GREEN
      LTDC_LxCLUTWR_GREEN_MASK    -> LTDC_LXCLUTWR_GREEN_MASK
      LTDC_LxCLUTWR_GREEN_SHIFT   -> LTDC_LXCLUTWR_GREEN_SHIFT
      LTDC_LxCLUTWR_RED           -> LTDC_LXCLUTWR_RED
      LTDC_LxCLUTWR_RED           -> LTDC_LXCLUTWR_RED
      LTDC_LxCLUTWR_RED_MASK      -> LTDC_LXCLUTWR_RED_MASK
      LTDC_LxCLUTWR_RED_SHIFT     -> LTDC_LXCLUTWR_RED_SHIFT
      LTDC_LxDCCR_DCALPHA         -> LTDC_LXDCCR_DCALPHA
      LTDC_LxDCCR_DCALPHA         -> LTDC_LXDCCR_DCALPHA
      LTDC_LxDCCR_DCALPHA_MASK    -> LTDC_LXDCCR_DCALPHA_MASK
      LTDC_LxDCCR_DCALPHA_SHIFT   -> LTDC_LXDCCR_DCALPHA_SHIFT
      LTDC_LxDCCR_DCBLUE          -> LTDC_LXDCCR_DCBLUE
      LTDC_LxDCCR_DCBLUE          -> LTDC_LXDCCR_DCBLUE
      LTDC_LxDCCR_DCBLUE_MASK     -> LTDC_LXDCCR_DCBLUE_MASK
      LTDC_LxDCCR_DCBLUE_SHIFT    -> LTDC_LXDCCR_DCBLUE_SHIFT
      LTDC_LxDCCR_DCGREEN         -> LTDC_LXDCCR_DCGREEN
      LTDC_LxDCCR_DCGREEN         -> LTDC_LXDCCR_DCGREEN
      LTDC_LxDCCR_DCGREEN_MASK    -> LTDC_LXDCCR_DCGREEN_MASK
      LTDC_LxDCCR_DCGREEN_SHIFT   -> LTDC_LXDCCR_DCGREEN_SHIFT
      LTDC_LxDCCR_DCRED           -> LTDC_LXDCCR_DCRED
      LTDC_LxDCCR_DCRED           -> LTDC_LXDCCR_DCRED
      LTDC_LxDCCR_DCRED_MASK      -> LTDC_LXDCCR_DCRED_MASK
      LTDC_LxDCCR_DCRED_SHIFT     -> LTDC_LXDCCR_DCRED_SHIFT
      LTDC_LxPFCR_PF              -> LTDC_LXPFCR_PF
      LTDC_LxPFCR_PF              -> LTDC_LXPFCR_PF
      LTDC_LxPFCR_PF_MASK         -> LTDC_LXPFCR_PF_MASK
      LTDC_LxPFCR_PF_SHIFT        -> LTDC_LXPFCR_PF_SHIFT
      LTDC_LxWHPCR_WHSPPOS_MASK   -> LTDC_LXWHPCR_WHSPPOS_MASK
      LTDC_LxWHPCR_WHSPPOS_SHIFT  -> LTDC_LXWHPCR_WHSPPOS_SHIFT
      LTDC_LxWHPCR_WHSTPOS_MASK   -> LTDC_LXWHPCR_WHSTPOS_MASK
      LTDC_LxWHPCR_WHSTPOS_SHIFT  -> LTDC_LXWHPCR_WHSTPOS_SHIFT
      LTDC_LxWVPCR_WVSPPOS_MASK   -> LTDC_LXWVPCR_WVSPPOS_MASK
      LTDC_LxWVPCR_WVSPPOS_SHIFT  -> LTDC_LXWVPCR_WVSPPOS_SHIFT
      LTDC_LxWVPCR_WVSTPOS_MASK   -> LTDC_LXWVPCR_WVSTPOS_MASK
      LTDC_LxWVPCR_WVSTPOS_SHIFT  -> LTDC_LXWVPCR_WVSTPOS_SHIFT

    * Fix all other nxstyle errors in the affected files.
 2021-03-03 18:49:20 -08:00
Xiang Xiao
9473434587 Ensure the kernel component don't call userspace API 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-03-01 09:23:09 +09:00
Masayuki Ishikawa
d87f350831 arch, boards, drivers, include, sched, wireless: Change spinlock APIs. 
Summary:
- This commit changes spinlock APIs (spin_lock_irqsave/spin_unlock_irqrestore)
- In the previous implementation, the global spinlock (i.e. g_irq_spin) was used.
- This commit allows to use caller specific spinlock but also supports to use
  g_irq_spin for backword compatibility (In this case, NULL must be specified)

Impact:
- None

Testing:
- Tested with the following configurations
- spresnse:wifi, spresense:wifi_smp
- esp32-devkitc:smp (QEMU), sabre6-quad:smp (QEMU)
- maxi-bit:smp (QEMU), sim:smp
- stm32f4discovery:wifi

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-02-07 21:28:56 -08:00
Alan C. Assis
b0d611d3dc Replace ARM_LWL_CONSOLE with generic LWL_CONSOLE 2021-01-31 06:14:50 -08:00
David Sidrane
a2f82542ef stm32f412:Replaced Kludged pinmap with one for SoC. 
The stm32f412 was not a clean port. This is one step to fix
   it. The shortcuts taken has caused more wasted hours finding
   bad pin mappings then doing the job correctlry to begin with.

   stm32:Kconfig Add CAN2 on STM32F412
 2021-01-21 06:56:33 -08:00
David Sidrane
657088318a stm32412: Fixes pinmap CAN1 2021-01-13 11:01:44 -06:00
Nathan Hartman
7592fc17d3 arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_otghs.h:

    * Fix nxstyle issues.
 2021-01-01 18:17:03 +01:00
Nathan Hartman
588227ed7b arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_otgfs.h:

    * Fix nxstyle issues.
 2020-12-31 20:32:13 +01:00
Xiang Xiao
c647faa117 Fix nxstyle warning 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-12-31 09:37:29 +01:00
Xiang Xiao
0defe43282 OS internal function should indicate the error by return negative value 
instead to change errno value by calling set_errno

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-12-31 09:37:29 +01:00
Nathan Hartman
81224cc596 arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_spi.h:

    * Fix nxstyle issues.
 2020-12-30 10:20:15 -06:00
Nathan Hartman
763aae8155 arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_rtc.h:

    * Fix nxstyle issues.
 2020-12-29 08:36:31 -06:00
Nathan Hartman
080b2dfceb arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_exti.h:
arch/arm/src/stm32/stm32_flash.c:
arch/arm/src/stm32/stm32_fsmc.c:
arch/arm/src/stm32/stm32_fsmc.h:
arch/arm/src/stm32/stm32_hciuart.h:
arch/arm/src/stm32/stm32_mpuinit.h:
arch/arm/src/stm32/stm32_rtc.c:

    * Fix nxstyle issues.
 2020-12-24 23:21:16 +01:00
Nathan Hartman
dad32ccd47 arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_dma.h:

    * Fix nxstyle issues.
 2020-12-23 20:35:42 -06:00
Fotis Panagiotopoulos
e26daf9357 STM32 FLASH latency is calculated based on Vin. 2020-12-23 08:13:45 -08:00
Nathan Hartman
78f308ff2c arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_dac.h:

    * Fix nxstyle issues.
 2020-12-21 20:20:17 +01:00
Nathan Hartman
4cefc5ce7a stm32g4: Fix incorrect FLASH wait states 
When the architectural support for STM32G4 family was added, the
reference manual (RM0440) was at revision 2. Since then, it has
undergone several revisions. One significant change is in the
table of FLASH wait states: section 3.3.3 table 9. The outcome
of this change is that fewer FLASH wait states are needed for
most CPU clock (HCLK) frequencies. Notably, if running the CPU
clock at the maximum 170 MHz, only 4 FLASH wait states are
needed, rather than the previously programmed 8 wait states.
This gives a noticeable performance boost.

arch/arm/src/stm32/stm32g4xxxx_rcc.c:

    * FLASH_ACR_LATENCY_SETTING: Reimplement compile-time logic
      that selects the required wait state setting to use the new
      updated table.

    * Update all comments to indicate that RM0440 Rev 5 is used.

    * Update section numbers mentioned in comments in cases where
      they have changed due to added sections in the manual.
 2020-12-21 18:43:49 +01:00
Nathan Hartman
4facd82ae0 arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_ltdc.h:
arch/arm/src/stm32/stm32_pmsleep.c:
arch/arm/src/stm32/stm32_pmstandby.c:

    * Fix nxstyle issues.
 2020-12-19 00:16:47 -06:00
chao.an
4a559807a5 arch/netdev: try tcp timer in every txavail call 
In the current implementation, the first transmission of the new
connection handshake is depends entirely by tcp_timer(), which will
caused 0.5s - 1s delay each time in connect().

This patch is mainly to improve the performance of TCP handshake.

Original:

nsh> tcp_client
[    1.536100] TCP connect start.
[    2.000200] TCP connect end. DIFF: tick: 4641, 464ms.
[    3.000300] TCP connect start.
[    4.000400] TCP connect end. DIFF: tick: 10001, 1000ms.
[    5.000500] TCP connect start.
[    6.000600] TCP connect end. DIFF: tick: 10001, 1000ms.
[    7.000700] TCP connect start.
[    8.000800] TCP connect end. DIFF: tick: 10001, 1000ms.

Optimized:

nsh> tcp_client
[    3.263600] TCP connect start.
[    3.263700] TCP connect end. DIFF: tick: 1, 0ms.
[    4.263800] TCP connect start.
[    4.263800] TCP connect end. DIFF: tick: 0, 0ms.
[    5.263900] TCP connect start.
[    5.263900] TCP connect end. DIFF: tick: 0, 0ms.
[    6.264000] TCP connect start.
[    6.264000] TCP connect end. DIFF: tick: 0, 0ms.
[    7.264100] TCP connect start.
[    7.264100] TCP connect end. DIFF: tick: 0, 0ms.

Signed-off-by: chao.an <anchao@xiaomi.com>
 2020-12-18 14:16:11 +09:00
Nathan Hartman
b960bee78b arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_tim.c:

    * Fix nxstyle errors.
 2020-12-15 19:10:30 +01:00
Nathan Hartman
3adadbe5d7 arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_usbhost.h:

    * Fix nxstyle errors.
 2020-12-15 06:47:20 +01:00
Nathan Hartman
705c64e5ff arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_wwdg.c:

    * Fix nxstyle errors.
 2020-12-13 22:54:03 +01:00
Nathan Hartman
2fda2451e3 arch/stm32: Add register definitions for STM32G4 ADC 
arch/arm/src/stm32/hardware/stm32_adc_v2g4.h:

    * New file.

arch/arm/src/stm32/hardware/stm32_adc.h:

    * Distinguish between the normal STM32 ADC IPv2 core and the
      modified IPv2 core used in the G4 family, and include either
      stm32_adc_v2.h or stm32_adc_v2g4.h as needed.
 2020-12-12 13:58:51 +01:00
Nathan Hartman
3864912dc8 arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32l15xxx_rtcc.c:

    * Fix nxstyle errors.
 2020-12-11 15:04:13 -03:00
Nathan Hartman
648ec7bee4 arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32l15xxx_rcc.c:

    * Fix nxstyle errors.
 2020-12-10 18:30:24 +01:00
raiden00pl
0c05f2ea38 stm32: add stm32g43x support and nucleo-g431rb board 2020-12-09 09:43:25 -03:00
Nathan Hartman
c257c458ad arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_rng.c:

    * Fix nxstyle errors.
 2020-12-09 09:21:42 +01:00
Nathan Hartman
c162069cd5 arch/stm32: Fix nxstyle errors (and one typo) 
arch/arm/src/stm32/stm32_dma2d.h
arch/arm/src/stm32/stm32_fmc.h
arch/arm/src/stm32/stm32_freerun.h
arch/arm/src/stm32/stm32_pm.h

    * Fix nxstyle errors.

arch/arm/src/stm32/hardware/stm32g4xxxx_dmamux.h

    * Fix typo in comment.
 2020-12-07 22:22:02 +01:00
raiden00pl
979a5b7fd4 stm32: convert all STM32G47X specific code to generic STM32G4 series code. 
This is an initial step towards supporting other STM32G4 chips.
 2020-12-06 13:37:02 -05:00
YAMAMOTO Takashi
330aa43f72 arch/arm/src/stm32/stm32_adc.c: Don't assume debug macro expansion 2020-12-06 09:03:09 -06:00
YAMAMOTO Takashi
ac905598ca arch/arm/src/stm32/stm32_freerun.c: Fix syslog formats 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
c28c9387a1 arch/arm/src/stm32/stm32_freerun.c: Appease nxstyle 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
99000d306d arch/arm/src/stm32/stm32_iwdg.c: Fix syslog formats 2020-12-05 08:13:32 -06:00
raiden00pl
a95512e05d nxstyle fixes 2020-12-05 07:46:06 -06:00
raiden00pl
9407d06d92 stm32/hardware: remove redundand ifdefs to keep headers consistent 2020-12-05 07:46:06 -06:00
Nathan Hartman
607ff94793 arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_eth.h:

    * Fix nxstyle errors.
 2020-12-04 23:15:01 +01:00
Nathan Hartman
e4c725481c arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_alarm.h,
arch/arm/src/stm32/stm32_can.h,
arch/arm/src/stm32/stm32_capture.h:

    * Fix nxstyle errors.
 2020-12-03 20:20:47 +01:00
Fotis Panagiotopoulos
09b6aca971 nxstyle fixes. 2020-12-02 11:27:15 -08:00
Fotis Panagiotopoulos
f538839720 FLASH waiting cycles are configured based on HCLK. 2020-12-02 11:27:15 -08:00
Nathan Hartman
32b49e6db8 arch/stm32: Fix a wrong bitfield definition 
arch/arm/src/stm32/hardware/stm32_adc_v2.h:

    * ADC_CFGR1_JAWD1EN: Change from (1 << 22) to (1 << 24)
      and update comment.
 2020-12-02 11:20:57 -06:00
Nathan Hartman
350a8b31a8 arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/hardware/stm32_adc.h:

    * Fix nxstyle errors.

arch/arm/src/stm32/hardware/stm32_adc_v2.h:

    * Fix nxstyle errors.
 2020-12-02 00:00:25 -06:00
Nathan Hartman
86e41979b4 arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_tim_lowerhalf.c:

    * Fix nxstyle errors.
 2020-12-01 21:01:34 +01:00
Nathan Hartman
b002698865 arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_uid.c:

    * Fix nxstyle errors.
 2020-12-01 21:01:34 +01:00
Nathan Hartman
cff63d1b1e arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_userspace.h:

    * Fix nxstyle errors.
 2020-12-01 21:01:34 +01:00
raiden00pl
756cb41a6c stm32/stm32h7: fix the configuration of PWM outputs when subsequent channels are not enabled (eg. CH1 and CH2 disabled, CH3 enabled) 
Resolves issue #2446
 2020-11-30 22:27:35 -06:00
YAMAMOTO Takashi
4d7d1665af arch/arm/src/stm32/stm32_i2s.c: Fix syslog formats 2020-11-30 05:28:17 -06:00
YAMAMOTO Takashi
fab675d442 arch/arm/src/stm32/stm32_can.c: Fix a syslog format 2020-11-30 05:28:17 -06:00