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13120 Commits

Author SHA1 Message Date
David Sidrane
38df949adc Merged in david_s5/nuttx/upstream_kinetis (pull request #221) 
Kinetis:Add LPUART

Approved-by: Gregory Nutt
 2017-02-25 17:23:04 +00:00
Gregory Nutt
d77d322a61 QEncoder: Add mechanism to assure that architecture-specific IOCTL commands do not overlap. 2017-02-25 11:15:59 -06:00
David Sidrane
df01e343a7 Kinetis:Add LPUART serail device driver 2017-02-25 07:06:04 -10:00
David Sidrane
0cbc03255c Kinetis:Add LPUART and Clock configuartaion to freedom-k66f board 
Pin out LPUART0 for testing
   Define BOARD_SOPT2_PLLFLLSEL ti select MCGPLLCLK
   Define BOARD_SIM_CLKDIV3_FREQ etal to provide BOARD_LPUART0_FREQ
 2017-02-25 07:05:34 -10:00
David Sidrane
b553d34a68 Kinetis:Added configurable 1|2 stop bits 
HAVE_SERIAL_CONSOLE -> HAVE_UART_CONSOLE to bew consistent with
  HAVE_LPUART_CONSOLE naming
 2017-02-25 07:02:56 -10:00
David Sidrane
dd218ffa8c Kinetis:Extend clockconfig to support SOPT2_PLLFLLSEL and SIM_CLKDIV3 
A board.h file can now specify the:
   1) BOARD_SOPT2_PLLFLLSEL to select the output of the SIM_SOPT2 MUX
     from:
       MCGFLLCLK
       MCGPLLCLK
       USB1PFD
       IRC48MHZ

    2) If it defines BOARD_SIM_CLKDIV3_FREQ then it must define
    BOARD_SIM_CLKDIV3_PLLFLLFRAC and BOARD_SIM_CLKDIV3_PLLFLLDIV
    which wil be used to cpnfigure SIM_CLKDIV3 [PLLFLLFRAC, PLLFLLDIV]
 2017-02-25 07:02:56 -10:00
David Sidrane
86c9f97f78 Kinetis: Add LPUART as lowlevel console 2017-02-25 07:02:56 -10:00
David Sidrane
29ab603a66 Kinetis:Add LPUART for use with K66 
Add LPUART made UART5 an uption as the K66 does not have UART5
 2017-02-25 07:02:56 -10:00
David Sidrane
61b10c5e58 Kinetis:Add LPUART to K66 chip 
Add KINETIS_NLPUART setting it to 1 and adjust KINETIS_NUART
  to removed UART5 as the K66 dioes not have UART5
 2017-02-25 07:02:56 -10:00
David Sidrane
f6fe9beeb3 Kinetis:Add LPUART to config 2017-02-25 07:02:56 -10:00
David Sidrane
b280aef9c0 Kinetis:Add LPUART register definitions 2017-02-25 07:02:38 -10:00
David Sidrane
9061a3fb64 Kinetis: UART add UART_BDH_SBNS definition 2017-02-25 07:02:38 -10:00
Gregory Nutt
de0e2ec261 STM32: Remove one residual use of the obsoleted STM32_TIM27_FREQUENCY definition which does not work for all STM32 family members. 2017-02-25 10:04:28 -06:00
Gregory Nutt
4c6b635298 Fix error in previous commit. 2017-02-25 09:39:33 -06:00
Gregory Nutt
c694ca0ebc Enable clocking to the timer on QE setup; disable clock on QE teardown. 2017-02-25 09:26:11 -06:00
Alan Carvalho de Assis
37298504e6 Fix QEncoder driver, based on STM32L4 driver 2017-02-24 16:10:28 -06:00
Gregory Nutt
8ee2e8d8b0 Most Ethernet drviers: Check if the poll timer is running before restarting it at the end of each TX. 2017-02-24 15:58:17 -06:00
Marc Rechte
579360e77d Merge branch 'master' of https://bitbucket.org/mrechte/nuttx-twrk64 2017-02-24 08:02:08 +01:00
Marc Rechte
c734a6283c kinetis_enet.c add #define for number of loops for auto negotiation to complete 2017-02-24 08:00:11 +01:00
David Sidrane
a43554decd Kinetis:SIM add paramiterized SIM_CLKDIVx_xxFRAC|DIV macros 
The makes for cleaner board definitions like:

   Divider output clock = Divider input clock * ((PLLFLLFRAC+1)/(PLLFLLDIV+1))
       SIM_CLKDIV3_FREQ = BOARD_SOPT2_FREQ × [ (PLLFLLFRAC+1) / (PLLFLLDIV+1)]
                 90 Mhz = 180 Mhz X [(0 + 1) / (1 + 1)]
    #define BOARD_SIM_CLKDIV3_PLLFLLFRAC  1
    #define BOARD_SIM_CLKDIV3_PLLFLLDIV   2
    #define BOARD_SIM_CLKDIV3_FREQ        (BOARD_SOPT2_FREQ * (BOARD_SIM_CLKDIV3_PLLFLLFRAC / BOARD_SIM_CLKDIV3_PLLFLLDIV))
 2017-02-23 19:27:55 -10:00
David Sidrane
e1278c0cb9 Kinetis:Fix typo in comment 2017-02-23 19:25:53 -10:00
Gregory Nutt
207b4a3c68 Update README.txt 2017-02-23 11:02:06 -06:00
Gregory Nutt
d83422a00d Update README.txt 2017-02-23 10:57:21 -06:00
David Sidrane
41e3d9f174 Kinetis:Refactor you use SIM_SOPT2_PLLFLLSEL, added warning 
The warning has been added because: SIM_SOPT2_PLLFLLSEL
  is a clock selection that may feed many clock subsystem:
   USB, TPM, SDHCSRC, LPUARTSRC. Therefore, there needs to
  be a global board level setting to select  the source for
  SIM_SOPT2_PLLFLLSEL and then  derive all the  sub selections
  and proper fractions/divisors for each modules clock.
 2017-02-22 10:42:52 -10:00
David Sidrane
12c24f2644 Kinetis:kinetis_clockconfig uses the correct ACKISO 
ACKISO is located in the PMC_REGSC on the majority
   of the Kinetis SoCs. With the exception of the
   MK40DXxxxZVLQ10 where ACKISO is located in LLWU_CS
 2017-02-22 10:42:52 -10:00
David Sidrane
1324b8c00a Kinetis:Resolves issues where Freescale moved ACKISO 
ACKISO is located in the PMC_REGSC on the majority
  of the Kinetis SoCs. With the exception of the
  MK40DXxxxZVLQ10 where ACKISO is located in LLWU_CS
 2017-02-22 10:42:52 -10:00
David Sidrane
a4b985f865 Kinetis:PMC defines are based on PMC feature configuration 2017-02-22 10:42:52 -10:00
David Sidrane
1ba6eadcec Kinetis:Include the PMC features 2017-02-22 10:42:52 -10:00
David Sidrane
8525c266a1 Created a kinetis PMC versioning scheme pulled in by Kinetis chip.h 
The motvations is to version the IP blocks of the Kinetis
     K series family of parts.

     This added versioning and configuration features for the
     Kinetis PMC IP block.

     It is envisioned that in the long term as a chip is added.
     The author of the new chip definitions will either find
     the exact configuration in an existing chip define and
     add the new chip to it Or add the PMC fature configuration
     #defines to the chip ifdef list in
     arch/arm/include/kinetis/kinetis_pmc.h  In either case the
     author should mark it as "Verified to Document Number:"
     taken from the reference manual.

     The version KINETIS_PMC_VERSION_UKN has been applied to
     most all the SoCs in the kinetis arch prior to this commit.

     The exceptions are the CONFIG_ARCH_CHIP_MK60FN1M0VLQ12,
     CONFIG_ARCH_CHIP_MK20DXxxxVLH7 All K64 and K66 have ben
     Verified PMC configurations.
 2017-02-22 10:42:52 -10:00
David Sidrane
381ffa3083 Kinetis:SIM defines are based on SIM feature configuration 2017-02-22 10:42:52 -10:00
David Sidrane
5b550a37eb Kinetis:Include the SIM features 2017-02-22 10:42:52 -10:00
David Sidrane
d74f16ecb9 Kinetis:Created a kinetis SIM versioning scheme pulled in by Kinetis chip.h 
The motvations is to version the IP blocks of the Kinetis
   K series family of parts.

   This added versioning and configuration features for the
   Kinetis SIM IP block.

   It is envisioned that in the long term as a chip is added.
   The author of the new chip definitions will either find
   the exact configuration in an existing chip define and
   add the new chip to it Or add the SIM feature configuration
   #defines to the chip ifdef list in
   arch/arm/include/kinetis/kinetis_sim.h  In either case the
   author should mark it as "Verified to Document Number:"
   taken from the reference manual.

   The version KINETIS_SIM_VERSION_UKN has been applied to
   most all the SoCs in the kinetis arch prior to this commit.

   The exceptions are the CONFIG_ARCH_CHIP_MK60FN1M0VLQ12,
   All K64 and K66 which not have Verified SIM configurations.
 2017-02-22 10:42:52 -10:00
David Sidrane
14bdf3af22 Kinetis:Fixed Typo in kinetis_mcg header 2017-02-22 10:42:52 -10:00
Gregory Nutt
bb059432ea Move local variables to top of function for compliance with coding standard. 2017-02-20 17:54:04 -06:00
Jussi Kivilinna
4dfb8268f3 stm32f7: stm32_allocateheap: allow use DTCM memory for heap 
STM32F7 has up to 128KiB of DTCM memory that is currently left unused.

This patch adds DTCM to main heap if CONFIG_STM32F7_DTCMEXCLUDE is not enabled.
 2017-02-20 08:42:51 -06:00
Gregory Nutt
4b4f0dc4df STM32L4 COMP: Remove some unused definitions 2017-02-20 08:41:43 -06:00
Gregory Nutt
0fc226dd53 Changes from review of last PR 2017-02-19 14:58:37 -06:00
Marc Rechté
1838171d43 Add twr-k64f120m config and fix some ENET related problems 2017-02-19 21:20:56 +01:00
Gregory Nutt
4033953878 STM32L4 COMP: Port from Motorola MDK. 2017-02-19 11:33:35 -06:00
Gregory Nutt
e61ded4a14 STM32L4: Add Comparator register definition file. 2017-02-19 10:09:17 -06:00
Gregory Nutt
d900e1fac0 STM32L4: Bring LPTIM driver in from the Motorola MDK. 2017-02-18 11:06:20 -06:00
Gregory Nutt
6bafdb1cdc Remove some dangling whitespace at the end of some lines. 2017-02-18 10:20:08 -06:00
Gregory Nutt
085616d651 STM32L4: Bring power management logic from Motrola MDK into NuttX 2017-02-18 10:18:42 -06:00
Gregory Nutt
6fe94b5724 Trivial cosmetic, alignement changes. 2017-02-17 17:50:56 -06:00
Gregory Nutt
e4e7528b1a Port STM32L4 SAI driver from MDK. 2017-02-17 15:13:36 -06:00
Gregory Nutt
377fadc816 STM32L4: Add SAI register definition header file. 2017-02-17 13:52:22 -06:00
Jussi Kivilinna
dd1aa2357b Allow board to configure HSE clock in bypass-mode. This is needed to enable HSE with Nucleo-F746ZG board. 2017-02-17 07:15:22 -06:00
Masayuki Ishikawa
add2fbfa85 LM3S Ethernet: Fix interrupt work in the last big commit. 2017-02-17 17:40:58 +09:00
Gregory Nutt
a49b349614 C library: Add swab() 2017-02-16 14:42:27 -06:00
Gregory Nutt
3b351615be Kinetis K66: Change necessary for correct build. 2017-02-16 11:33:36 -06:00
Spahlinger, Michael
42e8b12ec3 Fix for SAMv7 SPI: DLYBS value wass calculated, but never written to any registers. This led to incorrect timings on the bus. 2017-02-16 07:42:37 -06:00
Gregory Nutt
c3bfccf293 Kinetis PWM: Purely cosmetic changes from review. 2017-02-15 17:54:55 -06:00
David Sidrane
c83af148b1 Kinetis:Add FTM3 to PWM 2017-02-15 13:42:36 -10:00
David Sidrane
a95a6c43d3 Kinetis Support RMII clock source select 
This defined the RMII clock source select bits and allows
  the selection to be made via Kconfig
 2017-02-15 13:42:36 -10:00
Gregory Nutt
1474300276 LPC43: Rename HAVE_CONSOLE to HAVE_SERIAL_CONSOLE. We can, of course, always have a some console other than a serial console. 2017-02-15 07:23:18 -06:00
Alan Carvalho de Assis
058f06cc94 Fix typos introduced in previous commit 2017-02-15 07:16:15 -06:00
Gregory Nutt
077adf863e Merge branch 'master' of bitbucket.org:nuttx/nuttx 2017-02-14 19:31:58 -06:00
Alan Carvalho de Assis
1b996f1c7c Add usbnsh config to Bambino 200E board 2017-02-14 19:31:39 -06:00
Gregory Nutt
4043dd4aa0 LPC43 serial: Correct conditional logi that selects /dev/ttySN. Problem noted by Alan Carvalho de Assis. 2017-02-14 19:12:11 -06:00
David Sidrane
3423a4ecc2 Kinetis: Add comment the Freedom-K66F uses KSZ8081 PHY 2017-02-14 09:15:23 -10:00
David Sidrane
35fc713931 Kinetis K64 and K66 share mpu files 2017-02-14 09:15:23 -10:00
Gregory Nutt
b4695c5ee9 hostfs: Add support for fstat(). 2017-02-14 09:54:08 -06:00
David Sidrane
84b206bf7e Kinetis K66 FMC 
Added K66 FMC register definition
 2017-02-13 14:35:52 -10:00
David Sidrane
7d80db5919 Kinetis K66 Pin Mux 2017-02-13 14:35:51 -10:00
David Sidrane
e28781ebeb Include K66 memory map 2017-02-13 14:35:51 -10:00
David Sidrane
6597e46ce7 Define Alternate addresses for IP blocks in both AIPS0 & AIPS1 
Added ALT version of RNGA, FTM2, DAC0 as a facility to later
   define secondary access via AIPS1 to these peripherals
 2017-02-13 14:35:51 -10:00
David Sidrane
bd7d7edcf8 Kinetis: Updated comment in clockconfig 2017-02-13 13:24:47 -10:00
David Sidrane
3840c802d1 Kinetis SPI and I2C are 0 based 
The K whole family line has max 4 or each. But the supported
  parts have the maximums listed below:

    K46 and K66    3 SPI SPI0-SPI2
    K46 and K66    4 I2C I2C0-I2C3
 2017-02-13 13:24:47 -10:00
David Sidrane
ddd1f8c507 Kinetis SDHC - Enable clock after selected 2017-02-13 13:24:47 -10:00
Gregory Nutt
40f8e8b41f Fix some backward DEBUGASSERT tests in ROMFS and FAT. 2017-02-13 14:06:39 -06:00
Manohara HK
b154531838 I found an issue inside the cp15_coherent_dcache function in file, arch/arm/src/armv7-r/cp15_coherent_dcache.S. 
The "mcr CP15_BPIALLIS(r0)" instruction is used for invalidating entire branch predictor.  But the problem is, since this is the generic code and can be called on any armv7-r architecture based CPU's.  It is a problem, if this instruction is called in uni processor configuration. Because, BPIALLIS (c7, 0, c1, 6) instruction is only added as part of the "Multiprocessing Extensions" (As per ARM® Architecture Reference Manual /ARMv7-A and ARMv7-R edition)

So in my opinion, this instruction should be under SMP configuration. In non-SMP configuration this instruction could become undefined.
 2017-02-13 06:33:15 -06:00
David Sidrane
a907bbc5d3 Typo up_exit.c edited online with Bitbucket 2017-02-09 20:38:15 +00:00
Gregory Nutt
3329a534f7 Remove spurious blank line. 2017-02-09 13:06:42 -06:00
Gregory Nutt
c55d8f15a1 Merged in david_s5/nuttx/upstream_bkp_fix (pull request #206) 
STM32 & STM32F7 Fixes the bkp reference counter issue

Approved-by: Gregory Nutt
 2017-02-09 19:03:04 +00:00
David Sidrane
550d259a28 STM32F7: Fixes the bkp reference counter issue 2017-02-09 08:39:51 -10:00
David Sidrane
169b3982a2 STM32: Fixes the bkp reference counter issue 2017-02-09 08:39:51 -10:00
Gregory Nutt
a292da29d0 Costmetic changes from review of last PR. 2017-02-09 08:39:31 -10:00
David Sidrane
7262a788c4 Better granualarity and erro checking of the board's MCG settings 
Allow for complete MCG_C2 definition from the boart.h file
  Moved #ifdef out of code by setting default values for
  Allow for individule bit setting in MCG_C2 for
    BOARD_EXTCLOCK_MCG_C2
    BOARD_MCG_C2_FCFTRIM
    BOARD_MCG_C2_LOCRE0
  Added range and sanity checking
 2017-02-09 08:39:31 -10:00
David Sidrane
0e687121e5 arch/arm/include/kinetis/kinetis_mcg.h 2017-02-09 08:39:31 -10:00
David Sidrane
b2deadd569 Support the Indexed name LOCK->LOCK0 2017-02-09 08:39:30 -10:00
David Sidrane
eee029eec1 MCG defines are based on the MCG feature configuration 
We define the bits as a common set of names. This means that
  an index may be added to a name i.e. LOCK is LOCK0 as that is
  the superset name.
 2017-02-09 08:39:30 -10:00
David Sidrane
ab7b72f2e8 Kinetis chip Adding K66 and inlcuding MCG versioning 
This includes arch/arm/include/kinetis/kinetis_mcg.h
  to bring in the MCG versioning and defines the KINETIS_K66
  family for the added SoCs:

   --------------- ------- --- ------- ------- ------ ------ ------ -----
   PART NUMBER     CPU     PIN PACKAGE  TOTAL  PROGRAM EEPROM SRAM  GPIO
                   FREQ    CNT          FLASH  FLASH
   --------------- ------- --- ------- ------- ------ ------ ------ -----
   MK66FN2M0VMD18  180 MHz 144 MAPBGA   2   MB    —    — KB  260 KB 100
   MK66FX1M0VMD18  180 MHz 144 MAPBGA  1.25 MB  1 MB   4 KB  256 KB 100
   MK66FN2M0VLQ18  180 MHz 144 LQFP     2   MB    —    — KB  260 KB 100
   MK66FX1M0VLQ18  180 MHz 144 LQFP    1.25 MB  1 MB   4 KB  256 KB 100
 2017-02-09 08:39:30 -10:00
David Sidrane
9bbd98580b Created a kinetis MCG versioning scheme pulled in by Kinetis chip.h 
The motvations is to version the IP blocks of the Kinetis
   K series family of parts.

   This added versioning and configuration features for the
   Kinetis MCG IP block.

   It is envisioned that in the long term as a chip is added.
   The author of the new chip definitions will either find
   the exact configuration in an existing  chip define and
   add the new chip to it Or add the MCG feature configuration
   #defines to the chip ifdef list in
   arch/arm/include/kinetis/kinetis_mcg.h  In either case the
   author should mark it as "Verified to Document Number:"
   taken from the reference manual.

   The version KINETIS_MCG_VERSION_UKN has been applied to
   most all the SoCs in the kinetis arch prior to this commit.

   The exceptions are the CONFIG_ARCH_CHIP_MK60FN1M0VLQ12,
   All K64 and K66 which not have Verified MCG configurations.
 2017-02-09 08:39:30 -10:00
David Sidrane
6199d1801e Add K66 memory map 2017-02-09 08:39:30 -10:00
David Sidrane
db65734820 Add Kinetis K66 to Kinetis Kconfig 2017-02-09 08:39:30 -10:00
David Sidrane
bdd99f5aa1 Removed ws at EOL 2017-02-09 08:39:30 -10:00
Marc Rechté
d501ffc563 Kinetis SDHC driver fixes. 2017-02-09 11:28:30 -06:00
Gregory Nutt
1d290c2b37 setvbuf: Add support for disabling I/O buffering. Initially cut; untested. 2017-02-09 09:24:44 -06:00
Gregory Nutt
e6558df4ad SIM: Add readlink and setvbuf to nuttx-names.dat 2017-02-09 08:31:00 -06:00
Alan Carvalho de Assis
afa1066b4d LPC43: Fix missing #endif 2017-02-08 11:52:15 -06:00
Gregory Nutt
e803e2c3f4 Costmetic changes from review of last PR. 2017-02-07 17:16:56 -06:00
David Sidrane
a4ea49aaa2 Better granualarity and erro checking of the board's MCG settings 
Allow for complete MCG_C2 definition from the boart.h file
  Moved #ifdef out of code by setting default values for
  Allow for individule bit setting in MCG_C2 for
    BOARD_EXTCLOCK_MCG_C2
    BOARD_MCG_C2_FCFTRIM
    BOARD_MCG_C2_LOCRE0
  Added range and sanity checking
 2017-02-07 12:38:28 -10:00
David Sidrane
ff056cf9bd arch/arm/include/kinetis/kinetis_mcg.h 2017-02-07 12:38:28 -10:00
David Sidrane
87f759172a Support the Indexed name LOCK->LOCK0 2017-02-07 12:38:28 -10:00
David Sidrane
6022c62229 MCG defines are based on the MCG feature configuration 
We define the bits as a common set of names. This means that
  an index may be added to a name i.e. LOCK is LOCK0 as that is
  the superset name.
 2017-02-07 12:38:28 -10:00
David Sidrane
2216ed52a9 Kinetis chip Adding K66 and inlcuding MCG versioning 
This includes arch/arm/include/kinetis/kinetis_mcg.h
  to bring in the MCG versioning and defines the KINETIS_K66
  family for the added SoCs:

   --------------- ------- --- ------- ------- ------ ------ ------ -----
   PART NUMBER     CPU     PIN PACKAGE  TOTAL  PROGRAM EEPROM SRAM  GPIO
                   FREQ    CNT          FLASH  FLASH
   --------------- ------- --- ------- ------- ------ ------ ------ -----
   MK66FN2M0VMD18  180 MHz 144 MAPBGA   2   MB    —    — KB  260 KB 100
   MK66FX1M0VMD18  180 MHz 144 MAPBGA  1.25 MB  1 MB   4 KB  256 KB 100
   MK66FN2M0VLQ18  180 MHz 144 LQFP     2   MB    —    — KB  260 KB 100
   MK66FX1M0VLQ18  180 MHz 144 LQFP    1.25 MB  1 MB   4 KB  256 KB 100
 2017-02-07 12:38:28 -10:00
David Sidrane
ec567371b6 Created a kinetis MCG versioning scheme pulled in by Kinetis chip.h 
The motvations is to version the IP blocks of the Kinetis
   K series family of parts.

   This added versioning and configuration features for the
   Kinetis MCG IP block.

   It is envisioned that in the long term as a chip is added.
   The author of the new chip definitions will either find
   the exact configuration in an existing  chip define and
   add the new chip to it Or add the MCG feature configuration
   #defines to the chip ifdef list in
   arch/arm/include/kinetis/kinetis_mcg.h  In either case the
   author should mark it as "Verified to Document Number:"
   taken from the reference manual.

   The version KINETIS_MCG_VERSION_UKN has been applied to
   most all the SoCs in the kinetis arch prior to this commit.

   The exceptions are the CONFIG_ARCH_CHIP_MK60FN1M0VLQ12,
   All K64 and K66 which not have Verified MCG configurations.
 2017-02-07 12:38:28 -10:00
David Sidrane
5bfd2fedc6 Add K66 memory map 2017-02-07 12:38:28 -10:00
David Sidrane
97ae289f99 Add Kinetis K66 to Kinetis Kconfig 2017-02-07 12:38:28 -10:00
David Sidrane
eb955c9f15 Removed ws at EOL 2017-02-07 12:38:28 -10:00
Gregory Nutt
62a1f6f110 up_timer_initialize() is named incorrectly. The prefix should be the architecture name, not up_ since it is private to the architecture. up_timerisr() is similarly misnamed and should also be private since it is used only with the xyz_timerisr.c files. Also updat TODO list. 2017-02-07 10:35:04 -06:00
Gregory Nutt
9395704192 Kinetis, not Kinetics. 2017-02-07 08:20:52 -06:00
Gregory Nutt
54ce3817a5 SDIO interface: Handle all possible DMA combinations in all SDIO drivers. 2017-02-07 07:15:29 -06:00
Marc Rechté
b459fd1529 Updates to Kinetis SDHC driver 2017-02-06 07:43:05 -06:00
Gregory Nutt
b39d962021 Soft links: Update Documentation, rename file, add system calls 2017-02-02 17:11:08 -06:00
Gregory Nutt
1c66c06315 STM32F7 SDMMC: Make sure that all SDMMC configuration variables begin with STM32F7_; Eliminate CONFIG_SDMMC1/2_DMA altogether. Does not appear to be used. 2017-01-31 14:27:50 -06:00
Gregory Nutt
b7d29086e0 STM32F7 SDMMC: Add support for single bit operation on SDMMC2 2017-01-31 12:22:06 -06:00
David Sidrane
9066b4c093 stm32_sdio.c edited online with Bitbucket 2017-01-31 18:01:40 +00:00
Gregory Nutt
3dbdb3bb31 CONFIG_SDIO_DMA: Was been defined in several low-level architecute Kconfig files, but used at the highest levels in the code. Both are bad and both are fixed with this commit 2017-01-31 11:52:00 -06:00
Gregory Nutt
2a4791f4ee Removed dmasupported() method from the SDIO interface. That is now a bit in the cpapability set. 2017-01-31 09:51:15 -06:00
Gregory Nutt
9ac00a355f Add capabilities() method to SDIO interface. Remove CONFIG_SDIO_WIDTH_D1_ONLY. That should not be a global propertie, but rather a capability/limitation of single slot when there may be multiple slots. 2017-01-31 09:16:01 -06:00
Gregory Nutt
db77807ad2 Back out use on inline functions to access 16-bit registers. The inline functions were a work-around for misbehaving compiler years and years ago. The mon standard macro-ized version should work just fine. 2017-01-27 11:53:04 -06:00
Alan Carvalho de Assis
25bf212ab4 LPC43 pinset definitions: Add more 1 bit to pinset to reach SFSCLK0-SFSCLK3 2017-01-26 13:31:29 -06:00
Alan Carvalho de Assis
cf2beeb1cf LPC43: Remove PINCONFIG_DIGITAL 2017-01-26 13:26:55 -06:00
Gregory Nutt
3b9bcd57ba Remove uninterpretable comment. 2017-01-26 07:20:35 -06:00
Gregory Nutt
ff61d8f69d Add missing sched_note_*() calls to sam4cm SMP functions. 2017-01-24 14:33:57 -06:00
Gregory Nutt
f40a0311f5 Merged in david_s5/nuttx/upstream_2_greg_f3_bkp (pull request #200) 
Add missing STM32_BKP_BASE
 2017-01-23 23:42:33 +00:00
David Sidrane
02825f3db0 Add missing STM32_BKP_BASE 2017-01-23 13:38:57 -10:00
Gregory Nutt
492bde8cdb Merged in david_s5/nuttx/upstream_2_greg_f7_config (pull request #199) 
Added missing ARCH_HAVE_RESET for F7
 2017-01-23 23:08:50 +00:00
David Sidrane
ab18e483bd Added missing ARCH_HAVE_RESET for F7 2017-01-23 13:01:55 -10:00
Gregory Nutt
b656e371d3 ELF: Move sim and x86 ARM versions of ELF relocation logic to libc/machine 2017-01-21 15:40:51 -06:00
Gregory Nutt
4a8c6a6d2d ELF: Move ARMv6-M, ARMv7-M, and legacy ARM versions of ELF relocation logic to libc/machine 2017-01-21 15:24:25 -06:00
Gregory Nutt
edd9186540 ELF: Move ARMv7-A and ARMv7-R versions of ELF relocation logic to libc/machine 2017-01-21 14:40:26 -06:00
Gregory Nutt
be5ba90d4f Move optimized ARM memcpy functions from arch/arm/src/ to libc/machine/. This is necessary for the PROTECTED and KERNEL build modes. Otherwise, memcpy() will be built in to kernel space and not accessible to applications. 2017-01-20 10:53:46 -06:00
Gregory Nutt
3c4684ef5f Eliminate CONFIG_ARCH_OPTIMIZED_FUNCTIONS. Move options to select architectur-specific C library options from libc/Kconfig to libc/machine/Kconfig and rename. 2017-01-20 09:30:07 -06:00
Gregory Nutt
9cc37d8ee1 Math library optimatizations for FPU only apply to ARMv8 which is not yet supported. 2017-01-20 08:24:59 -06:00
Gregory Nutt
cbeade4069 Remove comment blocks from empty file sections. 2017-01-19 11:59:41 -06:00
Gregory Nutt
0c0c98691e STM32 and STM32L4 Oneshot: EBUSY is more appropriate error then ENOMEM 2017-01-18 16:20:15 -06:00
Wolfgang Reißnegger
a22dc9b1a8 SAM3/4: Add support for ATSAM4S4C. 2017-01-18 11:56:51 -08:00
Gregory Nutt
b05f928143 STM32L4: Port fix for multiple oneshot timers from STM32. Also fixes a few issues with original STM32 implementation. 2017-01-18 10:45:22 -06:00
Gregory Nutt
0069761d6f STM32 Oneshot: Fix logic so that it can support multiple oneshot timers. 2017-01-18 08:48:26 -06:00
Neil Hancock
2ece27f435 Kinetis: Add support for K64/K66 RTC lower half driver 2017-01-17 15:34:44 -06:00
Gregory Nutt
0db31d0cd1 SMP: Fix a typo introduced in c5b00ccfc4 2017-01-16 08:48:05 -06:00
Gregory Nutt
a2083fbc92 Update some comments 2017-01-15 12:35:03 -06:00
Gregory Nutt
2837eff0cd SMP: Most cosmetic clean-up from review of previous commit. 2017-01-14 09:22:13 -06:00
Gregory Nutt
c5b00ccfc4 SMP Signals: Fix some SMP signal delivery logic. Was not handling some critical sections correctly and was missing logic to signal tasks running on other CPUs. 2017-01-14 08:28:37 -06:00
Gregory Nutt
3ed091376c In all implementations of _exit(), use enter_critical_section() vs. disabling local interrupts. 2017-01-13 11:08:24 -06:00
Maciej Skrzypek
902c41462d Kinetis: New K60 has no Flex memory 2017-01-13 08:20:48 -06:00
Maciej Skrzypek
0c430e1d0f Kinetis MCG: Wrong FRDIV set in MCG_C1 2017-01-13 08:19:05 -06:00
Maciej Skrzypek
b6b30bcc7d Kinetis: Need to set HAVE_UART_DEVICE when UART4 is selected 2017-01-13 08:16:31 -06:00
Maciej Skrzypek
98bdd12521 Kinetis Serial: Fixed compile error when UART5 is selected 2017-01-13 08:14:41 -06:00
Maciej Skrzypek
4becebe59f Kinetis: Fixed wrong MCG VDIV calculation on new NXP K60 2017-01-13 08:13:21 -06:00
Maciej Skrzypek
bc1826da63 Kinetis: Added CHIP_MK60FN1M0VLQ12 chip 2017-01-13 08:10:03 -06:00
Gregory Nutt
4ede950039 Fix some typos in comments. 2017-01-12 18:02:23 -06:00
Gregory Nutt
895f01dd80 Merged in david_s5/nuttx/upstream_revert_265af481209d60033f7cd4c4216048b1ce3eb435 (pull request #194) 
Revert "STM32 serial: Make input hardware flow-control work with RX DMA.  From Jussi Kivilinna"
 2017-01-12 17:58:20 -06:00
Gregory Nutt
bd696b8c40 Merged in david_s5/nuttx/upstream_to_greg_HSI_ON_re (pull request #193) 
HSI should not be turned off
 2017-01-12 17:47:16 -06:00
David Sidrane
20e723715c HSI should not be turned off 2017-01-12 13:44:03 -10:00
Gregory Nutt
d5cdab0e51 Revert "HSI should not be turned off" 
This reverts commit 4e051c05fb.

This change broke the STM32 seril driver.
 2017-01-12 16:27:04 -06:00
Gregory Nutt
3191549116 Merged in david_s5/nuttx/upstream_to_greg_HSI_ON (pull request #191) 
HSI should not be turned off
 2017-01-11 17:14:14 -06:00
Gregory Nutt
62fe2bf11a Merged in david_s5/nuttx/upstream_to_greg_HSI_not_req_on_F4 (pull request #192) 
STM32F4 does not have the requierment that the HSI be on for FLASH erase/write operations
 2017-01-11 17:13:36 -06:00
David Sidrane
0dbf44e3ad STM32F4 does not have the requierment that the HSI be on for FLASH erace/write operations 2017-01-11 12:47:24 -10:00
David Sidrane
4e051c05fb HSI should not be turned off 2017-01-11 12:18:12 -10:00
Aleksandr Vyhovanec
bf528f2071 packed_struct replaced by begin_packed_struct and end_packed_struct 2017-01-09 14:17:49 +03:00
Gregory Nutt
1f33654f2d Update some comments 2017-01-06 17:15:01 -06:00
Gregory Nutt
905a1ce10f SAMV7 Ethernet: Fix a compiler error introduced with commit 7467329a98 2017-01-06 16:49:18 -06:00
Gregory Nutt
13d00344c9 Add configuration to prevent selection of Windows native toolchains when using Ubuntu under Windows 10 2017-01-02 07:16:47 -06:00
Gregory Nutt
3a0413c048 Back out most of 34be3e7c3c and update README again. Windows native tools cannot be used with Ubuntu under Windows 10 now. For Cygwin, that support depends on the 'cygpath -w' tool to convert POSIX paths to Windows paths. There is no corresponding tool for Ubuntu under Windows 10. 2017-01-01 16:29:03 -06:00
Gregory Nutt
34be3e7c3c Add configuration support for builds with Ubuntu under Windows 10 2017-01-01 15:34:23 -06:00
Gregory Nutt
b9e2bd4f37 Merge branch 'master' of bitbucket.org:nuttx/nuttx 2016-12-31 12:25:20 -06:00
Gregory Nutt
17cbec16dc STM32 SDIO: Remove warning about unused variable in STM32 F4 builds. 2016-12-31 12:24:02 -06:00
Aleksandr Vyhovanec
a0814ece13 Fix typos 2016-12-30 09:49:31 +03:00
Masayuki Ishikawa
3a0ae405b2 i.MX6: Fix clearing GPT status register 2016-12-28 10:19:18 -06:00
Gregory Nutt
c9b15ebb6a Xtensa ESP32: Remove call to sched_lock()/unock() from inter-cpu interrupt logic. Results in recursive call to sched_mergepending(). 2016-12-25 09:26:20 -06:00
Gregory Nutt
b87fc91466 Revert "Xtensa SMP: Avoid a nasty situation in SMP by assuring that up_release_pending() is not re-entered." 
This reverts commit 733a57b4df.
 2016-12-25 07:12:46 -06:00
Gregory Nutt
49fae0ac6b Revert "All CMP platforms: Apply same fix verified on other platforms found on Xtensa." 
This reverts commit fb146abee0.
 2016-12-25 07:08:44 -06:00
Gregory Nutt
ea7b673174 Merged in david_s5/nuttx/upstream_sdio_1bit_dma (pull request #188) 
Allow dma in 1 bit mode in STM32F4xxx
 2016-12-24 20:21:03 -06:00
Gregory Nutt
12148f0e33 Merged in paulpatience/nuttx/stm32 (pull request #180) 
STM32: Forgot to update chip.h for STM32F303x[BC]'s 4 ADCs
 2016-12-24 20:20:39 -06:00
Gregory Nutt
efb86382c3 SMP: Back out deferred IRQ locking. This was accidentally merged into master and it looks like it is going to be more work than I thought to get it working again. Changes will go to the irqlock branch. 2016-12-24 19:53:37 -06:00
David Sidrane
df9ae3c13f Revert "STM32 serial: Make input hardware flow-control work with RX DMA. From Jussi Kivilinna" 
This reverts commit 265af48120.

Conflicts:
	arch/arm/src/stm32/stm32_serial.c
 2016-12-23 14:12:57 -10:00
Gregory Nutt
1b790a61cd Xtensa ESP32: Add stack checking logic. 2016-12-23 15:51:33 -06:00
Gregory Nutt
b262c6be91 Merge remote-tracking branch 'origin/master' into irqlock 2016-12-23 13:09:11 -06:00
Gregory Nutt
f3d755c16f Some trivial, cosmetic changes for irqlock branch 2016-12-23 13:04:33 -06:00
Gregory Nutt
c7f5435637 Implement deferred IRQ locking. The rest of the support for Xtensa. Untested. 2016-12-23 11:56:45 -06:00
Frank Benkert
29cf2eb342 AMV7: CAN: Make delete_filter functions more robust 2016-12-23 11:45:21 -06:00
Gregory Nutt
cb1cc66d81 Implement deferred IRQ locking. Adds partial support for Xtensa. More is needed. 2016-12-23 11:39:44 -06:00
Gregory Nutt
9f7ba21f8a Implement deferred IRQ locking. Adds support for simulator. 2016-12-23 11:28:43 -06:00
Gregory Nutt
729ee7c099 ARMv7-A: Small improvement to some register handling in context restoration. 2016-12-23 11:13:18 -06:00
Gregory Nutt
d9ef0e86fb Fix a couple of errors in the last commit 2016-12-23 10:45:13 -06:00
Gregory Nutt
c00a1870d7 Implement deferred IRQ locking. Adds support for ARMv7-A. 2016-12-23 10:17:36 -06:00
Gregory Nutt
e6fff09ef8 Implement deferred IRQ locking. So far only form ARMv7-M. 2016-12-23 07:55:41 -06:00
David Sidrane
76ceb37553 Allow dma in 1 bit mode in STM32F4xxx 2016-12-22 09:19:37 -10:00
Gregory Nutt
5f9caad078 Xtensa ESP32: Correct copyright info; update some comments 2016-12-22 12:34:55 -06:00
Gregory Nutt
714e6f80ca Xtensa ESP32: Corrects a problem with dispatching to signal handlers: Cannot vector directly to the signal handling function as in other ABIs under the Xtensa Window ABI. In that case, we need to go through a tiny hook when performs the correct window call (call4) otherwise registers will be scrambled in the signal handler 2016-12-22 11:19:38 -06:00
Gregory Nutt
d9a64b9ca9 Xtensa ESP32: Some fixes from integration of ostest configuration. Almost works: There are some assertions in xtensa_sigdeliver() 2016-12-22 09:34:39 -06:00
Gregory Nutt
fb146abee0 All CMP platforms: Apply same fix verified on other platforms found on Xtensa. 2016-12-21 14:04:09 -06:00
Gregory Nutt
733a57b4df Xtensa SMP: Avoid a nasty situation in SMP by assuring that up_release_pending() is not re-entered. 2016-12-21 13:34:01 -06:00
Gregory Nutt
588d2b506f Xtensa ESP32: Oddly, an rsync barrier when writing to co-processor register corrects problem. 2016-12-21 08:04:48 -06:00
Gregory Nutt
1b7162a0db Eliminate a warning 2016-12-21 08:04:48 -06:00
Gregory Nutt
81697f2285 Xtensa ESP32: Fix APP CPU startup... Can't use semaphores on the IDLE thread. 2016-12-20 11:26:37 -06:00
Gregory Nutt
6d5a718b98 Xtensa ESP32: A few fixes for APP CPU start-up 2016-12-20 10:38:27 -06:00
Gregory Nutt
4e9a0ffea5 Xtensa ESP32: Update APP CPU startup logic to match current Expressif example code. 2016-12-20 09:00:04 -06:00
Gregory Nutt
3b681586c0 Xtensa ESP32: Missing prologue/epilogue macros on C callable function 2016-12-20 08:31:36 -06:00
Gregory Nutt
5666bf30a7 Review of last PR 2016-12-20 07:08:46 -06:00
Young
07b70fcc20 Improve the PWM logs 2016-12-20 17:05:51 +08:00
Young
9d355e12d5 Support indefinite number of pulses generation in PULSECOUNT mode 2016-12-20 14:08:31 +08:00
Young
e35406f7d6 Support PWM_PULSECOUNT feature for TI tiva 2016-12-20 13:20:04 +08:00
Gregory Nutt
e5182acbe3 Xtensa ESP32: Make sure that SMP configuratin still builds without errors. 2016-12-19 14:12:19 -06:00
Gregory Nutt
e61549d8b9 Xtensa ESP32: Clean-up and fixes from last commits 2016-12-19 13:57:37 -06:00
Gregory Nutt
097f09cb02 Xtensa ESP32: Corrects timer initialization and timer input frequency. 2016-12-19 11:50:28 -06:00
Gregory Nutt
a9a39800a4 Xtensa ESP32: Fixes some double faults and user errors, but I do not fully understand why. 2016-12-19 11:14:08 -06:00
Gregory Nutt
886ce88b4f Xtensa ESP32: Automatically mount /proc at start-up. 2016-12-19 09:43:16 -06:00
Gregory Nutt
2b0b698d72 ESP32 Serial: Add logic to prevent infinite loops in interrupt handler. 2016-12-18 16:04:25 -06:00
Gregory Nutt
71bb79a6c7 ESP32 Serial: Fix some register bit definitions. 2016-12-18 15:11:34 -06:00
Gregory Nutt
4bd530d026 Xtensa ESP32: Last change should be conditioned on the window ABI. 2016-12-18 13:17:31 -06:00
Gregory Nutt
665c1647b5 Xtensa ESP32: Need to spill registers to memory as the last dying action before switching to a new thread. 2016-12-18 12:54:47 -06:00
Gregory Nutt
586f0aab50 Fix context save logic when called in window ABI configuration. Add an IDLE stack. Don't depend on the mystery stack received from the bootloader. 2016-12-18 10:08:08 -06:00
Gregory Nutt
93e6d16f75 Xtensa ESP32: wsr, not rsr. 2016-12-17 11:23:10 -06:00
Gregory Nutt
a88c50d366 Xtensa ESP32: Need to clone some logic for syncrhonous context switch. Window spill logic in the conmon restores logic is inappropriate in this context 2016-12-17 11:00:12 -06:00
Gregory Nutt
6b80e5f15f Xtensa ESP32: Fix clobbered a9 in co-processor context save/restore 2016-12-17 11:00:12 -06:00
Gregory Nutt
8de1127899 Xtensa ESP32: Using wrong register to disable interrupts. 2016-12-17 11:00:12 -06:00
David Sidrane
ec85425041 STM32: Fix some STM32F7 copy paste errors 2016-12-17 08:31:12 -06:00
Gregory Nutt
38ebe6c13f Xtensa ESP32: Change that should have been included in a previous commit was not. 2016-12-17 08:11:32 -06:00
Gregory Nutt
05e798488b One register getting clobber on context save 2016-12-17 08:10:10 -06:00
Gregory Nutt
adbacfc42c Xtensa ESP32: Fix a duplicate in Kconfig files. Level 1 should return via RFE. 2016-12-17 07:07:33 -06:00
Gregory Nutt
6599feb310 Xtensa ESP32: Fixes a few issue with restoring registers on interrupt return, but there is still a problem 2016-12-16 17:56:22 -06:00
Gregory Nutt
cdd8dc72a5 Xtensa ESP32: Basically a redesign of the interrupt dispatch logic. 2016-12-16 15:36:52 -06:00
Gregory Nutt
d4ad5f04d3 Xtensa ESP32: Minor rearchitecting of how CPU interrupts are enabled. MOre to come. 2016-12-16 14:13:09 -06:00
Gregory Nutt
cd3d414ba2 Xtensa: Fix some missing SMP logic 2016-12-16 13:37:28 -06:00
Gregory Nutt
34a994b0f6 Correct a logic problem the prevented dumping the IDLE thread's stack on an assertion 2016-12-16 13:21:01 -06:00
Gregory Nutt
6337fadd8c Missing escape character on CR of CR-LF expansion. 2016-12-16 10:49:42 -06:00
Gregory Nutt
935e49f5bb Update some comments 2016-12-16 09:38:08 -06:00
Gregory Nutt
f1a5b91cd8 Use r6, not r2 when passing paramters with call4 2016-12-16 09:21:44 -06:00
Gregory Nutt
41cf32a20e Fix windowspill register handling + Use r6, not r2 when passing paramters with call4 2016-12-16 09:20:36 -06:00
Gregory Nutt
aa5a8b0ca2 Xtensa: Make sure that all C callable assembly functions includes ENTRY prologue and RET epilogue. 2016-12-15 14:02:19 -06:00
Gregory Nutt
c56268b416 Fix missing CALL0 ABI condition. 2016-12-15 11:06:41 -06:00
Gregory Nutt
ea9e6c48e4 Cosmetic update to comments. 2016-12-15 10:43:34 -06:00
Gregory Nutt
10b9a10d2f Xtensa ESP32: Fix several build-related issues associated with vector section 2016-12-15 10:08:26 -06:00
Gregory Nutt
4795d58e03 Back out most of 46dbbe837e. The order is correct -- or, rather, the order is the same as the order that response data is provided. Change the order will break all other drivers. 2016-12-15 07:16:24 -06:00
Gregory Nutt
b5e979d58f ESP32: Fix a couple of bugs associated with handling of CPU interrupts. 2016-12-14 13:31:44 -06:00
Gregory Nutt
4052ec2d90 Add missing ENTRY() and RET() macros in C callable assembly language. At one time I though the that the ESP32 support the CALL0 ABI. I was mistaken so there may be a few more like this. 2016-12-14 12:14:51 -06:00
Gregory Nutt
730ca4ce41 Fix missing semicolons in DEBUGASSERT statements 2016-12-14 09:06:09 -06:00
Angus Gratton
dd5e47a418 ESP32 core v2: Two changes (1) flushes the UART TX buffer in the esp32 serial shutdown routine. The ROM bootloader does not flush the FIFO before handing over to user code, so some of this output is not currently seen when the UART is reconfigured in early stages of startup. And changes the openocd config file's default flash voltage from 1.8V to 3.3V. This is not necessary right now, but may save some hard-to-debug moments down the track (3.3V-only flash running at 1.8V often half-works and does weird things...) 2016-12-14 08:15:03 -06:00
Gregory Nutt
f063e4c5ac Remove Calypso architecture support and support for Calypso SERCOMM driver. 2016-12-13 18:35:52 -06:00
Gregory Nutt
c83da3c48f Remove minnsh configurations and support logic: up_getc() and lowinstream. 
This was an interesting exercise to see just how small you could get NuttX, but otherwise it was not useful:  (1) the NSH code violated the OS interface layer by callup up_getc and up_putc directly, and (2) while waiting for character input, NSH would call up_getc() which would hog all of the CPU.  NOt a reasonably solution other than as a proof of concept.
 2016-12-13 18:01:23 -06:00
Gregory Nutt
26560cb9e1 i.MX6: Remove non-cached, inter-cpu memory region. Not a useful concept. 2016-12-13 16:59:50 -06:00
Frank Benkert
a36ed28790 SAMV7: MCAN: Prevent Interrupt-Flooding of ACKE when not connected to CAN-BUS. An Acknowledge-Error will occur every time no other CAN Node acknowledges the message sent. This will also occur if the device is not connected to the can-bus. The CAN-Standard declares, that the Chip has to retry a given message as long as it is not sent successfully (or it is not cancelled by the application). Every time the chip tries to resend the message an Acknowledge-Error-Interrupt is generated. At high baud rates this can lead in extremely high CPU load just for handling the interrupts (and possibly the error handling in the application). To prevent this Interrupt-Flooding we disable the ACKE once it is seen as long we didn't transfer at least one message successfully. 2016-12-13 11:22:54 -06:00
Gregory Nutt
edeee90c66 i.MX6 interrupt handling: Additional logic needed to handle nested interrupts when an interrupt stack is used 2016-12-13 10:04:38 -06:00
Gregory Nutt
113d8bdcca Fix some SMP-related compilation errors 2016-12-09 17:10:59 -06:00
Gregory Nutt
70de0ee39f Merge remote-tracking branch 'origin/master' into cancelpt 2016-12-09 14:42:48 -06:00
Gregory Nutt
8b81cf5c7e Merged in david_s5/nuttx-3/david_s5/typo-in-stm32f76xx77xx_pinmaph-edited-on-1481298811328 (pull request #182) 
Typo in stm32f76xx77xx_pinmap.h edited online with Bitbucket
 2016-12-09 10:54:39 -06:00
Alan Carvalho de Assis
35023e4c6d LPC43xx SD card: Correct pin configuration options needed for SD card pins. 2016-12-09 10:54:17 -06:00
David Sidrane
64ae731c99 stm32_allocateheap.c edited online with Bitbucket 2016-12-09 16:35:35 +00:00
Gregory Nutt
018db84567 Flesh out more cancellation point logic. 2016-12-09 10:31:40 -06:00
David Sidrane
e7597d1754 Typo in stm32f76xx77xx_pinmap.h edited online with Bitbucket 2016-12-09 15:53:58 +00:00
David Sidrane
df9c5b33a0 Added STM32F469 RAM size and deliberated STM32F446 size 2016-12-09 05:02:31 -10:00
Paul A. Patience
30bbeb6c1f STM32: Forgot to update chip.h for STM32F303x[BC]'s 4 ADCs 2016-12-08 16:31:39 -05:00
David Sidrane
dd309ad9e8 I was wrong - the original commit was correct. Assume a write op on the last word: address of 0xxxxxfe and count of 2. It is a valid operation and address+count is == STM32_FLASH_SIZE - so that is OK 2016-12-08 21:14:31 +00:00
David Sidrane
c77bda47d7 BUGFIX:STM32F427 was rebooting. Over reached family. 2016-12-08 20:31:56 +00:00
Gregory Nutt
ab43681f15 Update TODO and some comments. 2016-12-08 10:24:40 -06:00
Pierre-noel Bouteville
017773eda3 EFM32: Fix a compilation error 2016-12-07 09:13:13 -06:00
Gregory Nutt
a7b688e87b sched notes: Add additional note to see if/when CPU is started in SMP mode. 2016-12-07 09:08:20 -06:00
Gregory Nutt
dc79e35d65 For Cortex-A9, should also set ACTLR.FW in SMP mode to enble TLB and cache broadcasts. Does not fix SMP cache problem. 2016-12-07 09:06:41 -06:00
Gregory Nutt
b9be0279b1 Coding standard requires a blank line after every comment. 2016-12-07 06:52:15 -06:00
Gregory Nutt
cae56b825b Merged in david_s5/nuttx/upstream_to_greg_SDIO_fix (pull request #177) 
Allow a config to override the SDIO clock edge setting
 2016-12-07 12:48:11 +00:00
David Sidrane
cbf863b1ca STM32F7: Allow the config to override the clock edge setting 2016-12-06 13:43:57 -10:00
David Sidrane
7cc0a06f44 STM32: Allow the config to override the clock edge setting 2016-12-06 13:30:07 -10:00
Gregory Nutt
e190e1ee5b stm32fxxxxx_otgfs.h edited online with Bitbucket 2016-12-06 15:58:05 +00:00
Gregory Nutt
8e447453e1 Add a missing bit field definitions that was lost when stm32_otgfs.h was deleted. 2016-12-06 09:22:03 -06:00
Gregory Nutt
d6437407b1 Fix broken build. Previous commit removed a file that was being used. 2016-12-06 09:03:00 -06:00
Gregory Nutt
b6a21edb42 Merged in david_s5/nuttx/upstream_to_greg (pull request #176) 
Upstream to greg
 2016-12-06 12:22:42 +00:00
David Sidrane
885b718552 Expanded otgfs support to stm32F469 and stm32f446 
Added missing bits definitions
   Used stm32F469 and stm32f446 bit definitions
   Removed unsed header file
 2016-12-05 18:07:57 -10:00
David Sidrane
50f36f8967 Added support for stmf469 SAI and I2S PLL configuration and STM446 fixes 2016-12-05 14:21:46 -10:00
David Sidrane
8b31eda4d8 Added Timers 2-5 and control of SAI and I2S PLLs 2016-12-05 14:19:56 -10:00
Gregory Nutt
9ed0387379 Olimex-LPC1766-STK: Enable procfs in NSH configuration. Automount /proc on startup. 2016-12-05 08:52:40 -06:00
Gregory Nutt
6cff0a7012 SAMA5 PWM: Minor improvement to a loop 2016-12-04 15:48:13 -06:00
Gregory Nutt
39c4ecbcd0 SAMA5 PWM: Costmetic 2016-12-04 15:39:53 -06:00
Gregory Nutt
ff76ebfd31 SAMA5 does not build when executing from SDRAM before board frequencies are not constant. Rather, the bootloader configures the clocking and we must derive the clocking from the MCK left by the bootloader. This means lots more computations. This is untested on initial commit because I don't have a good PWM test setup right now. 2016-12-04 15:25:43 -06:00
Masayuki Ishikawa
d92a7886a4 SAM3/4: Add SMP support for the dual-core SAM4CM 2016-12-04 07:23:31 -06:00
Masayuki Ishikawa
84900298b7 ARMv7-M SMP: Applied the latest changes for ARMv7A-SMP 2016-12-04 06:49:49 -06:00
Gregory Nutt
9c65b0321d Eliminate some warnings 2016-12-04 06:24:24 -06:00
Gregory Nutt
920a9592d1 Fix a naming collision introduced in last big commit 2016-12-03 18:19:08 -06:00
Gregory Nutt
7467329a98 Eliminate CONFIG_NO_NOINTS. Lots of files changed -> lots of testing needed. 2016-12-03 16:28:19 -06:00
Gregory Nutt
ad3897531f C5471 Ethernet now supports CONFIG_NET_NOINTS 2016-12-03 12:17:55 -06:00
Gregory Nutt
43459fe75e DM09x0 Ethernet now supports CONFIG_NET_NOINTS 2016-12-03 11:42:15 -06:00
Gregory Nutt
41e35c88bf eZ80 Ethernet now supports CONFIG_NET_NOINTS 2016-12-03 10:43:35 -06:00
Gregory Nutt
eba1e076ec PIC32MX/Z Ethernet: Now supports CONFIG_NET_NOINT 2016-12-03 09:50:14 -06:00
Gregory Nutt
bfa1da14e2 LM3S Ethernet now supports CONFIG_NET_NOINTS 2016-12-03 08:32:49 -06:00
Gregory Nutt
1851e9e837 SAMA5D3: Add support for CONFIG_NET_NOINTS to EMACA and GMAC driver. 2016-12-02 16:36:27 -06:00
Gregory Nutt
b95e1f656b i.MX6: Add an untested SPI driver taken directly from the i.MX1 port. 2016-12-02 13:51:07 -06:00
Gregory Nutt
c0cbea2550 Remove RGMP and RGMP drivers. 2016-12-02 09:49:33 -06:00
Alan Carvalho de Assis
cd119ad544 GPDMA driver for the LPC43xx. The GPDMA block is basically the same as the LPC17xx. Only the clock configuration is different and LPC43xx has four different DMA request sources, where LPC17xx has only two. 2016-12-01 18:01:04 -06:00
Sebastien Lorquet
db24f237d7 STM32L4: Correct USART1/2 definitions. Use default mbed UART4 settings 2016-12-01 09:00:59 -06:00
Alan Carvalho de Assis
8b3a6d1eca LPC43 SD/MMC: Correct some git definitions on SMMC control register in lpc43_sdmmc.h 2016-11-30 14:50:32 -06:00
Janne Rosberg
a03d26e88d stm32_otghshost: if STM32F446 increase number of channels to 16 2016-11-30 12:17:12 -06:00
Gregory Nutt
44668c00a0 LPC17 Ethernet: Tiny, trivial, cosmetic spacing change 2016-11-30 12:16:21 -06:00
Gregory Nutt
b29b77532f Update some comments 2016-11-29 18:17:37 -06:00
Gregory Nutt
934aded293 arch/: Adapt all Ethernet drivers to work as though CONFIG_NET_MULTIBUFFER were set. Remove all references to CONFIG_NET_MULTIBUFFER 2016-11-29 16:06:48 -06:00
Gregory Nutt
f06d521c10 Minor extensions to some comments 2016-11-29 10:01:38 -06:00
Ramtin Amin
137586f50a Misoc LM32: Add logic to flush/invalidate caches 2016-11-29 09:09:28 -06:00
Gregory Nutt
79bb895073 i.MX6: Don't output the alphabet if CONFIG_DEBUG_FEATURES is not set. 2016-11-29 08:34:22 -06:00
Gregory Nutt
a8b69c3efe Back out a debug change that was included in commit 2016-11-29 07:51:49 -06:00
Marc Rechté
3f91bd6056 STM32 DAC: Fix shift value whenever there are is a DAC2 and, hence, up to three interfaces. 2016-11-29 07:03:54 -06:00
Gregory Nutt
1f9e3ae5f1 Misoc LM32: Make naming consistent, lm32_sigdeliver vs. up_sigdeliver. 2016-11-28 11:18:07 -06:00
Ramtin Amin
b568bfa813 Misoc LM3: Add Misoc Ethernet driver. Integrate network support into configs/misoc/hello. Remove configs/misoc/include/generated directory. I suppose the the intent now is that this is a symbolic link? DANGER! This means that you cannot compile this code with first generating these files a providing a symbolic link to this location! 2016-11-28 11:08:29 -06:00
Gregory Nutt
d65be718c2 sched_note: Extend OS instrumentation to include some SMP events. 2016-11-27 17:14:57 -06:00
Gregory Nutt
cbf98ae0a0 ARMv7 GIC: SGIs are non-maskable but go through the same path as other, maskable interrupts. Added logic to serialize SGI processing when necessary. 2016-11-27 13:18:34 -06:00
Gregory Nutt
21e42d18c1 ARMv7-A/i.MX6 SMP: Move SMP coherernt cache setup to earlier in initialization of CPUn, n>0 2016-11-27 11:28:24 -06:00
Gregory Nutt
cd54c71dc1 ARMv7-A/i.MX6: Modify handling of the SMP cache coherency configuration so that it is identical to the steps from the TRM. Makes no differenct, however. 2016-11-27 10:21:46 -06:00
Gregory Nutt
278d8330d6 arm_scu.c edited online with Bitbucket. Fux some typos. 2016-11-27 02:59:42 +00:00
Gregory Nutt
3f6eadc238 ARMv7-A: Fix some SCU SMP logic 2016-11-26 18:41:48 -06:00
Gregory Nutt
546e352830 i.MX6: Add some controls to enable SMP cache coherency in SMP mode 2016-11-26 17:46:20 -06:00
Gregory Nutt
3353d9280f i.MX6: Disable non-cached region support. Add SCU register definitions. 2016-11-26 17:03:57 -06:00
Gregory Nutt
8dc79bb7ef Update comments and README file 2016-11-26 16:02:37 -06:00
Gregory Nutt
b2ba12e02a SMP: Basic function 2016-11-26 14:23:23 -06:00
Gregory Nutt
785ed5faf2 SMP: A few more compile/link issues. Still problems. 2016-11-26 13:20:11 -06:00
Gregory Nutt
6ff6da083f Fix a few compile related issues from the last commit 2016-11-26 12:23:09 -06:00
Gregory Nutt
aae306e942 i.MX6 SMP: Inter-CPU data no saved in a non-cacheable region. 2016-11-26 12:04:02 -06:00
Gregory Nutt
dda0ac8b21 Update comments 2016-11-26 11:06:24 -06:00
Gregory Nutt
9376296e99 Merge remote-tracking branch 'origin/master' into imx6-smp 2016-11-26 11:02:55 -06:00
Gregory Nutt
8bacb1e426 Update comments 2016-11-26 11:02:21 -06:00
Gregory Nutt
bdf570ea08 Fix typos in comments 2016-11-26 10:42:25 -06:00
Gregory Nutt
2fba04f752 i.MX6 SMP: Beginning of non-cacheable region (incomplete) 2016-11-26 10:37:06 -06:00
Gregory Nutt
61b45a8544 i.MX6: Add some comments 2016-11-26 09:27:29 -06:00
Gregory Nutt
e3fe320e08 SMP: Add support for linking spinlocks into a special, non-cached memory region. 2016-11-26 08:47:03 -06:00
Maciej Wójcik
0d0b1b64e2 Fix for F1 RTC Clock, tested on F103 2016-11-25 06:17:18 +01:00
Gregory Nutt
b08fb33c28 SMP: Fix typos in some conditional compilation 2016-11-24 17:59:45 -06:00
Gregory Nutt
7f636f2280 SMP: Add spin_trylock(). Use this in conditions where other CPUs need to stopped but we cannot call enter_critical_section. 2016-11-24 13:33:43 -06:00
Ramtin Amin
7568aaf213 Misoc LM32: Add signal handling logic 2016-11-24 12:58:23 -06:00
Gregory Nutt
f77dcdf323 ARMv7-A SMP: Add a little logic to signal handling. 2016-11-24 11:45:05 -06:00
Gregory Nutt
c03d126da6 arm_cpupause.c edited online with Bitbucke. What was I thinking... Back out previous change. 2016-11-24 04:45:07 +00:00
Gregory Nutt
19e7f2210e arm_cpupause.c edited online with Bitbucket. Fix a typo in a comment. 2016-11-24 04:24:40 +00:00
Gregory Nutt
4b0bbf41ca SMP: Fix backward condition in test. 2016-11-23 22:24:14 -06:00
Alan Carvalho de Assis
7dbc25b02b LPC43xx: Add timer driver; configs/bambino-200e: Add support for timer driver 2016-11-23 13:33:51 -06:00
Ramtin Amin
b8754afb14 Misoc LM32: Make system timer configurable via CONFIG_USEC_PER_TICK. 2016-11-23 07:00:57 -06:00
Gregory Nutt
f90525a5d1 SMP: Update some comments; trivial improvement by inlining static function. 2016-11-22 16:48:57 -06:00
Gregory Nutt
d95b8f64f5 sam4s-xplained-pro: Remove obsolete timer initialization logic 2016-11-22 12:25:57 -06:00
Gregory Nutt
12f830ffd5 SAM3/4: Name of method is now setcallback, not sethandler 2016-11-22 12:06:07 -06:00
Gregory Nutt
054072d054 Misoc: Add commits and warnings about missing caculation of the timer reload value 2016-11-22 12:15:34 -06:00
Ramtin Amin
d1e84fb788 Misoc: Add timer driver 2016-11-22 12:10:11 -06:00
Gregory Nutt
bac7153609 SMP: Add logic to avoid a deadlock condition when CPU1 is hung waiting for g_cpu_irqlock and CPU0 is waitin for g_cpu_paused 2016-11-22 11:34:16 -06:00
Sebastien Lorquet
ec586ab350 implementation of dumpgpio for stm32l4, was required for pwm debug. 2016-11-22 07:57:21 -06:00
Gregory Nutt
130bfa3f6b Remove a assertion condition that appears to rarely cause false-alarm assertions. Teported by Petteri Aimonen 2016-11-21 14:43:56 -06:00
Gregory Nutt
f53e48199f Simplify and document some macros 2016-11-21 13:12:43 -06:00
Gregory Nutt
558784d06f Spinlocks: Added capability to provide architecture-specific memory barriers. This was for i.MX6 but does not help with the SMP problems. It is still a good feature. 2016-11-21 11:55:59 -06:00
Gregory Nutt
0804286ad3 arch/: Add option to use low-priority work queue to all Ethernet drivers in arch that support CONFIG_NET_NOINTS. 2016-11-19 09:20:01 -06:00
Gregory Nutt
0db99b8c89 Trivial fix from review of last PR 2016-11-19 06:52:51 -06:00
Gregory Nutt
8705ce816a Merged in gnagflow/nuttx (pull request #173) 
Master
 2016-11-19 12:49:56 +00:00
Wolfgang Reißnegger
b23c1f8817 Typo fix in sam_udp.c 2016-11-18 17:23:22 -08:00
Wolfgang Reißnegger
d135246a7d SAM3/4: Remove 'stalled' flag in UDP driver. 
The flag is not necessary. The state of the endpoint can be determined
using 'epstate' instead.
 2016-11-18 17:23:21 -08:00
Wolfgang Reißnegger
9e349f4335 SAM3/4: Remove unused 'halted' flag in UDP driver. 2016-11-18 17:23:21 -08:00
Wolfgang Reißnegger
c7ef82c546 SAM3/4: Add delay between setting and clearing the endpoint RESET bit in sam_ep_resume(). 
We need to add a delay between setting and clearing the endpoint reset
bit in SAM_UDP_RSTEP. Without the delay the USB controller will (may?)
not reset the endpoint.

If the endpoint is not being reset, the Data Toggle (DTGLE) bit will
not to be cleared which will cause the next transaction to fail if
DTGLE is 1. If that happens the host will time-out and reset the bus.

Adding this delay may also fix the USBMSC_STALL_RACEWAR in
usbmsc_scsi.c, however this has not been verified yet.
 2016-11-18 17:23:21 -08:00
Paul A. Patience
8d9804d57b STM32: STM32F303xB and STM32F303xC chips have 4 ADCs 2016-11-18 19:28:09 -05:00
Gregory Nutt
f92afbfbf3 apps/examples/timer: Restore the timer example, but adapt the interface to use the new signal logic from Sebastien, Lorquet. Totally untested and probably does not work! 2016-11-17 15:19:17 -06:00
Gregory Nutt
19c1c9d78b All timer lower half drivers. Port Sebastien's changes to all all other implementations of the timer lower half. Very many just and untested. Expect some problems. 2016-11-17 15:03:31 -06:00
Sebastien Lorquet
197cec58d2 timer driver: Use signal to notify of timer expiration. Add generic argument so that there can be additional usage. 2016-11-17 14:38:21 -06:00
Gregory Nutt
18ad40b98c ARMv7-M: Fix double allocation of MPU region in mmu.h 2016-11-17 13:37:24 -06:00
Gregory Nutt
bb19f1b499 spinlocks should be volatile. 2016-11-17 10:04:22 -06:00
Gregory Nutt
6a875bcb61 Xtensa: Add EXPERIMENTAL hooks to support lazy co-processor state restore in the future. 2016-11-16 06:48:13 -06:00
Gregory Nutt
c84db68103 Xtensa ESP32: Fix some compilation errors that snuck with some of the last changes 2016-11-14 13:29:08 -06:00
Kolb, Stefan
bf096873a1 SAMV7 USBDEVHS: A problem occurred if the USB cable is unplugged while a large amount of data is send over an IN endpoint using DMA. If the USB cable is plugged in again after a few seconds it is not possible to send data over this IN endpoint again, all other endpoints work as expected. 
The problem occurs because if the USB cable is unplugged while an DMA transfer is in flight the transfer is canceled but the register SAM_USBHS_DEVDMACTRL is left in an undefined state.  The problem was fixed the problem by resetting the register SAM_USBHS_DEVDMACTRL to a known state. Additionally all pending interrupts are cleared.
 2016-11-14 10:32:49 -06:00