Summary:
- I noticed that ps shows incorrect stack usage when running
getprime in the background.
- With CONFIG_ARCH_ADDRENV=y, a user task including pthread
allocates its stack in the user space that needs to be
accessed with a correct address environment.
- This commit fixes this issue.
Impact:
- CONFIG_ARCH_ADDRENV=y only
Testing:
- Tested with sabre-6quad:knsh on qemu-6.2
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
ld: arch/libarch.a(cxd56_allocateheap.c.obj): in function `up_allocate_heap':
arch/arm/src/cxd56xx/cxd56_allocateheap.c:113: multiple definition of `up_allocate_heap'; arch/libarch.a(arm_allocateheap.c.obj):
arch/arm/src/common/arm_allocateheap.c:110: first defined here
Signed-off-by: chao.an <anchao@xiaomi.com>
arch/arm/src/common/arm_hostfs.c: In function 'host_read':
arch/arm/src/common/arm_hostfs.c:156:24:
warning: passing argument 1 of 'up_invalidate_dcache' makes integer from pointer without a cast [-Wint-conversion]
156 | up_invalidate_dcache(buf, buf + count);
| ^~~
| |
| void *
In file included from arch/arm/src/common/arm_hostfs.c:26:
include/nuttx/cache.h:261:37: note: expected 'uintptr_t' {aka 'unsigned int'} but argument is of type 'void *'
261 | void up_invalidate_dcache(uintptr_t start, uintptr_t end);
| ~~~~~~~~~~^~~~~
Signed-off-by: chao.an <anchao@xiaomi.com>
This commit adds RX DMA support to serial driver. The DMA is currently
supported only for USART peripherals, not for UART. It uses two circular
buffers which size can be setup by SAMV7_SERIAL_RXDMA_BUFFER option.
The idle bus interrupt is enabled to ensures data are read even if the
buffer is not yet full. The timeout can be setup by
SAMV7_SERIAL_DMA_TIMEOUT option.
This adds support only for RX transfers.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This commit adds functions sam_dmarxsetup_circular() and
sam_dmarxstart_circular() that create API for operating with two or more
circular buffers. This can be used for DMA operation with serial driver
or ADC where ping pong buffers are required to successfully transfer the
data at high speed.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This commit enhances SAMV7 serial driver with RS-485 mode available to
USART peripherals. The hardware automatically sets RTS pin high when
data are transfered and low then no transfer occurs. Only USART peripherals
support this mode, UART peripherals do not.
This mode can be enabled by configuration option SAMV7_USARTx_RS485MODE.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
1. Fix error recovery mechanism during transmission error
handling (enable transmission at the end).
2. Fix compilation / operation with CONFIG_SAMV7_EMAC_PREALLOCATE=y
3. Enable fully configured address space for transmission queues
to allow sending packets with length more than 976 bytes. With
partially configured address space the AHB error is generated
during transmission of long packets.
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
forget to update in this patch:
commit b02db04e00
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
Date: Sun Jun 5 17:10:19 2022 +0800
arch/assert: Keep the thread dump column order same as ps
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
* arch/arm/src/tiva/common/tiva_lowputc.c
(tiva_lowsetup):
For each UART, if Kconfig enables RTS/CTS (e.g.,
CONFIG_UART0_IFLOWCONTROL and/or CONFIG_UART0_OFLOWCONTROL),
configure the corresponding GPIO(s).
* arch/arm/src/tiva/common/tiva_serial.c:
(struct up_dev_s):
If CONFIG_SERIAL_IFLOWCONTROL, add a bool field 'iflow'. If
CONFIG_SERIAL_OFLOWCONTROL, add a bool field 'oflow'. This is
inspired by the implementation for kinetis.
(g_uart0priv, g_uart1priv, g_uart2priv, g_uart3priv, g_uart4priv,
g_uart5priv, g_uart6priv, g_uart7priv):
If Kconfig enables RTS/CTS for a UART (e.g.,
CONFIG_UART0_IFLOWCONTROL thru CONFIG_UART7_OFLOWCONTROL), set
the corresponding iflow and/or oflow flag(s).
(up_setup):
Check the above-mentioned iflow and oflow flags and set or unset
the RTSEN and/or CTSEN bits in the UART's CTL register to enable
the feature.
The "p" format specifier already prepends the pointer address with "0x"
when printing.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
SAMA5D2 and SAMA5D4 does not support external reset.
Some SAMA5 board's Kconfig contain item SAMA5_SYSTEMRESET, but it is better in arch/arm/src/Kconfig.
