Add an interface that validate if EasyDMA transfer is possible.
EasyDMA cannot access flash memory which can cause hard to detect silent bugs.
This feature is enabled if CONFIG_DEBUG_FEATURES=y and CONFIG_DEBUG_ASSERTIONS=y.
External function to query vbus status. Reading from the block requires
the clock, but if no devices are open -> vbus detect does not work.
This creates a chicken / egg problem, if vbus detect is used to start
the usb device.
bmp388 works poorly as the system fires STOPs even in
a beginning of a transaction. Don't let unrelated STOPs
to distort the data flow.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This adds 2 more FPGA I2Cs. Also rework the indexing
so that it matches the earlier work without major changes.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This fixes the following issue:
- After sending the address, the driver writes an extra zero
Without this patch, the extra write causes an extra ACK that would
terminate the sequence prematurely. This is observed as data read
corruption.
With this fix, the condition is detected precisely. That being the
case, the sequence is continued with a repeated start, after which
the read continues normally.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This incorporates an fpga i2c driver into the existing i2c driver.
This fpga i2c works almost 100% as the MSS i2c, but the difference
is that the fpga driver terminates all transactions with a stop
sent -interrupt. That needs to be handled.
Fpga clock source is also different, act accordingly.
SEC2TICK(10) is an overkill to any app, use just one second instead.
modifyreg32s are simplified as well, no need to clear and set
as set is enough.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
I2C status register reset value (0xf8) was not handled properly causing unnecessary bus resets.
Added critical section to mpfs_i2c_reset() and removed unnecessary interrupt disabling elsewhere.
Confirmation of the IN request must be done immediately after all data has been transferred,
otherwise sending data when more than one request has been added to the queue will
not work properly.
- Update TrustedFirmare-M instructions to latest version of STM32CubeL5
- Increase idle thread stack size to not overflow during system init
- Select ARCH_HAVE_TRUSTZONE for STM32L5
- Set CONFIG_ARCH_TRUSTZONE_NONSECURE for stm32l562e-dk:nsh, since NuttX
is running in the Non-secure world.
See https://github.com/apache/nuttx/issues/9316
Signed-off-by: Michael Jung <michael.jung@secore.ly>
Whenever a SPI flash operation is going to take place, it's
necessary to disable both the instruction and data cache. In order
to avoid the other CPU (if SMP is enabled) to retrieve data from
the SPI flash, it needs to be paused until the current SPI flash
operation finishes. All the code that "pauses" the other CPU (in
fact, the CPU spins until `up_cpu_resume` is called) needs to run
from the instruction RAM.
SAMv7 QSPI peripheral does not copy-in/out directly into/from
user provided buffer, but use a dedicated memory that is interfaces
using byte copy. The QSPI command buffer can point to memory with
any alignment
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Add a new field to record the global on the basis of mm_backtrace.
When using alloc, the field is incremented by 1,
so that the memory usage can be dumped within the range
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
armv8r and armv8a have different process affinity,
and sgi affinity needs to be able to adapt all of them.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Summary
For ARM64, it need to set IRQ type(EDGE or LEVEL). it's specific
for ARM64 PPI or SPI.
The change add arm64_gic_irq_trigger to set IRQ type
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary
add up_affinity_irq/up_trigger_irq/up_prioritize_irq for gicv3
these interface is necessary for some drivers
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary:
GICR_PWRR is a IMPLEMENTATION-DEFINED register for gc700/gc600, which
is following gic v3 and v4.
Please check GICR_PWRR define at TRM of GIC600/GIC700 for more detail
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
