Squashed commit of the following:
sched: Rename all use of system_t to clock_t.
syscall: Rename all use of system_t to clock_t.
net: Rename all use of system_t to clock_t.
libs: Rename all use of system_t to clock_t.
fs: Rename all use of system_t to clock_t.
drivers: Rename all use of system_t to clock_t.
arch: Rename all use of system_t to clock_t.
include: Remove definition of systime_t; rename all use of system_t to clock_t.
Squashed commit of the following:
arch/arm/src/stm32f7: Some minor changes for clean compilation of LTDC.
arch/arm/src/stm32f7: Add overly support for LTDC driver header file.
arch/arm/src/stm32f7: Add overly support for LTDC driver file.
arch/arm/src/stm32f7: Add overly support for DMA2D driver header file.
arch/arm/src/stm32f7: Finishes overly support for DMA2D driver.
arch/arm/src/stm32f7: Partial overly support in DMA2D driver (a lot more to be donw)
arch/arm/src/stm32f7/chip: Clone overlay DMA2D register definitions from F4
arch/arm/src/stm32f7: Clone overlay configuration from stm32 F4
stm32f7: serial: Fix ioctl TIOCSSINGLEWIRE
The TRM notes that UE must be disabled in order to write HDSEL in
USART_CR3. This was not being done, so calls to TIOCSSINGLEWIRE were
silently failing.
This change checks the state of UE in USART_CR1, clears the UE bit
before writing HDSEL, then re-enables it if neccesary.
Approved-by: GregoryN <gnutt@nuttx.org>
LTDC fixes
* stm32_ltdc: Allows to use ltdc without overlay support
Signed-off-by: Marco Krahl <ocram.lhark@gmail.com>
* stm32: Removes overlay dependency when LTDC is enabled
Signed-off-by: Marco Krahl <ocram.lhark@gmail.com>
* stm32: Allows to configure initial chromakey for LTDC layer
Signed-off-by: Marco Krahl <ocram.lhark@gmail.com>
* stm32_ltdc: Fixes another compiler warning when dma2d is disabled
Signed-off-by: Marco Krahl <ocram.lhark@gmail.com>
* stm32_ltdc: Checks for register reload is done before continued
Signed-off-by: Marco Krahl <ocram.lhark@gmail.com>
* stm32f429i-disco: Fixes eliminated register control by compiler optimization
When reading 1 byte from the SPI device the clock must be enabled and
immediately disabled. This section has been optimized by the compiler (-O2) to a
missing active spi clock. A subsequently block read failed because of missing
response from the spi device. This has been lead to a broken display
initializing.
Signed-off-by: Marco Krahl <ocram.lhark@gmail.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Fixes compiler errors when using LTDC and DMA2D
* stm32: ltdc and dma2d are are depends on FB_OVERLAY support
Signed-off-by: Marco Krahl <ocram.lhark@gmail.com>
* stm32_dma2d.h: Makes interface available when FB_OVERLAY is enabled
Signed-off-by: Marco Krahl <ocram.lhark@gmail.com>
* stm32_ltdc: Fixes compiler error when blit support is disabled
Signed-off-by: Marco Krahl <ocram.lhark@gmail.com>
* stm32f429i-disco: Updates lvgl board example
Signed-off-by: Marco Krahl <ocram.lhark@gmail.com>
* stm32f429i-disco: Updates nxwm board example
Still nxwm_main is missing.
Signed-off-by: Marco Krahl <ocram.lhark@gmail.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Signal handlers maybe run with interrupts enabled or disabled, depending on how the task the received the signal was blocked. (i.e.: If sem_wait() is called, then we disable interrupts, then block the currently running task). This could be dangerous, because user code would be running with interrupts disabled.
This change forces interrupts to be enabled in up_sigdeliver() before executing the signal handler calling up_irq_enable() explicitly. This is safe because, when we return to normal execution, interrupts will be restored to their previous state when the signal handler returns.
Squashed commit of the following:
arch/arm/src/stm32/stm32f10xxf30xx_flash.c: Re-implemented Dmitriy Linikov's change to support multi-banked FLASH on the STM32 F1 parts AFTER separating the FLASH support by architecture and implementing more standard base+offset register addressing. Now the change goes in rather cleanly.
arch/arm/src/stm32/stm32f10xxf30xx_flash.c: Use base + offset address to simplify implementation of dual bank flash.
Squashed commit of the following:
arch/arm/src/stm32/stm32f10xxf30xx_flash.c: Be consistent in file naming.
arch/arm/src/stm32l10xxf30xxx_flash.c: Separate STM32F10xx and STM32F30xx FLASH logic into a separate file.
arch/arm/src/stm32l20xx40xxx_flash.c: Separate STM32F20xx and STM32F40xxFLASH logic into a separate file.
arch/arm/src/stm32l15xx_flash.c: Separate STM32L15xx FLASH logic into a separate file.
Kinetis UART must be placed in 9 bit mode (M=1) with when 8 bit
data with parity is required. If left in 8 bit mode (M=0) with
parity then D7 of the TX/RX register becomes parity bit. Hence
what is called 9-bit or 8-bit Mode Select is a misnomer.
8 bit mode when parity is enabled is realy 7 bit with parity.
Previous BRFA was not cleared and or-ed into new BRFA, hence
buadrate was wrong. Where Baud Rate Fractional Divisor (BRFD)
UART baud rate = clock / (16 * (SBR + BRFD))
Squashed commit of the following:
Author: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/imxrt: Add cache operations to permit the Ethernet driver to work with the D-Cache enabled, at least in write-through mode.
Author: Jake Choy <jakearcx@gmail.com>
arch/arm/src/imxrt: The Ethernet driver is now functional, at least with the D-Cache off. The final fix was for the reference clock that needs to be forced to provide and input (SION).
Author: Gregory Nutt <gnutt@nuttx.org>
Fix trivial coding standard issue.
configs/imxrt1050-evk: Correct CONFIG_RAM_SIZE in all configurations (5Kb not 5Mb). I don't believe that CONFIG_RAM_SIZE is used at all in the i.MX RT so this is as grievous an error as it seems. Also enabled built-in applications in all NSH configurations.
arch/arm/src/imxrt/imxrt_enet.c: Trivial and cosmetic.
Cosmetic update to comments.
arch/arm/src/imxrt/imxrt_enet.c: Oops.. put the PHY interrupt init hooks in the wrong place. That is a one-time initialization but imxrt_initphy() is called on each ifup.
arch/arm/src/imxrt/imxrt_enet.c: Add hooks for board-specific PHY initialization (not yet needed, but there when needed).
Remove dangling white space at the end of lines
arch/arm/src/imxrt/Kconfig: Add option for board-specific PHY initialization.
configs/imxrt1050-evk/src: Add basic logic to support PHY interrupts. Incomplete.. needs additional support in imxrt_enet.c to 1. call to initialize PHY interrupt features, and 2. IOCTL commands to access PHY registers.
configs/imxrt1050-evk/README.txt: Trivial update.
configs/imxrt1050-evk/netnsh/defconfig: Disable LED support because pins conflict with PHY. Enable device statists. Enable NSH ifup and ifdown commmands
arch/arm/src/imxrt: Use macros in imxrt_periphclks.h vs. direct CCM CCGR accesses in Ethernet driver.
arch/arm/src/imxrt: Misc changes for a clean compilation of Ethernet deriver. configs/imxrt1050-evk/netnsh: Add an NSH configuration for testing Ethernet.
Author: Jake Choy <jakearcx@gmail.com>
arch/arm/src/imxrt: Initial WIP Ethernet driver.
arch/arm/src/imxrt: May eDMA channel linking a configuration option. Add support to select the DMA channel priority and pre-emption controls.
arch/arm/src/imxrt: Update some HowTo comments in the eDMA header file.
arch/arm/src/imxrt: Fix a logic error in parmater passing. Caller does not know actual channel number when setting up linked channel, only the channel handler.
arch/arm/src/imxrt: Fixes for clean eDMA driver build with Scatter/Gather enabled.
arch/arm/src/imxrt: Fixes for clean eDMA driver build with Scatter/Gather disabled.
arch/arm/src/imxrt: Add flags to DMA configuration to control transfer setup. Remove some user interfaces that are inconsistent with modular design.
arch/arm/src/imxrt: Update DMA channel interrupt handler.
arch/arm/src/imxrt: Add implementation of eDMA imxrt_dmach_start().
arch/arm/src/imxrt: Add implementation of eDMA imxrt_dmach_setup().
arch/arm/src/imxrt: Add eDMA imxrt_tcd_chanlink().
arch/arm/src/imxrt: Add eDMA imxrt_dmach_getcount; free allocated TCDs automatically when the DMA completes or is aborted.
arch/arm/src/imxrt: Add structures to support list of TCDs for Scatter/Gather DMA.
arch/arm/src/imxrt: Add eDMA imxrt_dmach_initconfig().
arch/arm/src/imxrt: Add eDMA imxrt_tcd_instantiate().
arch/arm/src/imxrt: Replacing some of the logic cloned from SAMv7 XDMAC with eDMA logic from NXP sample code. I am thinking that the eDMA is too complex to force into the same pattern as for other MCUs.
arch/arms/src/imxrt/imxrt_edma.c: Add support for in-memory TCDs.
arch/arm/src/imxrt/chip: Add an in-memory representation of the TCD in imxrt_edma.h
configs/stm32f4discovery/include/board.h: Add SPI DMA pins definitions to get CS43L22 audio DAC working
configs/stm32f4discovery/audio: Add board configuration for CS43L22 audio example
configs/stm32f4discovery: Update README
As with the MCU temperature and VREFINT measurement, this patch requires user to enable the corresponding channel first. For Vbat channel the ioctl cmd is IO_ENABLE_DISABLE_VBAT_CH, and its arg should be a pointer to bool which must be true to enable and false to disable the Vbat channel.
Moreover, since Vbat input contains a built-in voltage divider, it is highly suggested to disable Vbat input channel after measurement is done in order to prevent battery drain through the divider.
commit 7fd1f0d78546fa0315f4077b779efdd884e5bd53
Author: William Douglas <william@rocklandscientific.com>
Date: Tue May 15 13:19:31 2018 -0700
Add support for the second SDMMC device.
The second SDMMC device was already supported but
the clock was never enabled. This fixes that.
configs/freedom-k28f: Add button and LED support.
arch/arm/src/kinetis: Fix a couple of additional compile problems.
arch/arm/src/kinetis/chip and configs/freedom-k28f: Add things needed for a successful build. Still need board LED definitions.
