Commit Graph

22251 Commits

Author SHA1 Message Date
jinxiuxu
31fe15b6e0 audio:fix crash when driver_audio capture
sim/posix/sim_alsa.c:728:24: runtime error: member
access within null pointer of type 'const struct sim_codec_ops_s'

Signed-off-by: jinxiuxu <jinxiuxu@xiaomi.com>
2024-08-21 17:59:28 +08:00
qiaohaijiao1
d7088fe376 sim/alsa: use default bps as 16 in offload mode.
Signed-off-by: qiaohaijiao1 <qiaohaijiao1@xiaomi.com>
2024-08-21 17:59:28 +08:00
chenrun1
bb4d710d62 xtensa_cache:Disable clean/flush optimization in case of SMP restriction
In a multicore task scenario, there may be a situation where the task runs on different cores at different time slices (when the task is not bound to a particular core).
When the task calls cache clean/flush(range > cache size), depending on the optimization, clean_all, flush_all are called. however, at this point, there may be dirty data or incomplete data profiles in the cache on the kernel that is running the task, which may result in dirty data being flushed into memory or make the application think that the flushed data should be successfully flushed into memory, leading to unknown consequences.

Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
2024-08-21 03:04:41 +08:00
chenrun1
91cf97ed84 arm_cache:Disable clean/flush optimization in case of SMP restriction
In a multicore task scenario, there may be a situation where the task runs on different cores at different time slices (when the task is not bound to a particular core).
When the task calls cache clean/flush(range > cache size), depending on the optimization, clean_all, flush_all are called. however, at this point, there may be dirty data or incomplete data profiles in the cache on the kernel that is running the task, which may result in dirty data being flushed into memory or make the application think that the flushed data should be successfully flushed into memory, leading to unknown consequences.

Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
2024-08-21 03:04:41 +08:00
wangming9
0c12fb9237 arm/armv8-r: Fix cache interface
Signed-off-by: wangming9 <wangming9@xiaomi.com>
2024-08-21 03:04:41 +08:00
wangming9
0bfd4c5e0d arm/armv8-r: Adding a cache interface to armv8-r
Summary:
1. Add up_get_icache_size、up_get_dcache_size
2. Added L2 cahce PL310 implementation

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2024-08-21 03:04:41 +08:00
fangxinyong
13cb355a4e arm/armv[7|8]-m: add syn barrier for MPU ops
Execute data and instruction sync barriers after writing MPU register,
to ensure MPU setting take effects that the new changes are seen.

testing in lm3s6965-ek:qemu-protected

Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
2024-08-21 02:57:25 +08:00
jianglianfang
1e29b8de1d driver/fb:remove overlay from fb_notify_vsync
Signed-off-by: jianglianfang <jianglianfang@xiaomi.com>
2024-08-21 02:57:08 +08:00
jianglianfang
8122cbd5d2 drivers/video: add fb_vsync_pollnotify
when the vsync comes, fb drivers should call fb_vsync_pollnotify to notify POLLPRI, so that users can catch the synchronization time of vsync and do something.

Signed-off-by: jianglianfang <jianglianfang@xiaomi.com>
2024-08-21 02:57:08 +08:00
guoshichao
24ce8dfbf2 armv7-a/irq: add up_irq_disable method implementation
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
(cherry picked from commit 7059b05e501d67c342f1753e8eb96e723b99d6b8)
2024-08-21 02:53:04 +08:00
guoshichao
0aa7e39eef nuttx/arch/irq: add up_irq_disable method implementation
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-08-21 02:53:04 +08:00
liqinhui
4c69ef988f simwifi: Add the netlink event of connect/disconnect.
Signed-off-by: liqinhui <liqinhui@xiaomi.com>
2024-08-21 02:08:10 +08:00
zhanghongyu
4e79741e7d usbdev: add ncm driver
The compilation and verification commands are shown below:
./tools/configure.sh sim:usbdev
make -j
sudo ./nuttx
nsh> conn 2
nsh> dhcpd_start eth1

Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
2024-08-21 02:01:01 +08:00
hujun5
4cb419866f arch: inline up_testset in arm arm64 riscv xtensa
test:
Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
   -machine virt,virtualization=on,gic-version=3 \
   -net none -chardev stdio,id=con,mux=on -serial chardev:con \
   -mon chardev=con,mode=readline -kernel ./nuttx

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-08-21 01:45:10 +08:00
cuiziwei
7b43a9413a arch/EXTRA_LIBS: link all staging library.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-08-21 01:40:15 +08:00
guoshichao
07c370817c armv7a/irq: enable fiq in tee, enable irq in ap
According to the current design on the armv7-a platform,
only fiq is processed in TEE, while irq and fiq are processed
in REE.
If we enable the irq function in TEE, when we process
some signal-related scenarios in TEE,
such as the ostest sighand testcase, this testcase will
call up_irq_enable() to enable irq interrupt in the
arm_sigdeliver() function. After the signal processing
logic is executed, irq will be disabled again.
During the interval of enabling irq, some external device
irq interrupts will be enabled, but these external device
irqs do not have corresponding handlers registered in TEE,
so an "unexpected irq isr exception" will be triggered.
Therefore, a better implementation is to keep the original
implementation of the up_irq_enable() function, that is,
to enable only fiq in TEE and to enable irq and fiq in REE.
Then  for vendor-specific requirements, such as the need to
briefly enable irq during the TEE initialization process
and then disable irq before starting APz in TEE, we directly
provide a separate implementation of enabling irq in the
vendor, without modifying the implementation of the public
up_enable_irq() function.

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-08-21 01:36:32 +08:00
Filipe Cavalcanti
4d4d8a6ca5 arch/risc-v/esp32c3: fix AP password memcpy typo 2024-08-20 00:50:26 +02:00
cuiziwei
837410fad2 nuttx/sim:By default, stack-use-after-return is not checked when enabling SIM_ASAN.
==263401==ERROR: AddressSanitizer: stack-use-after-return on address 0xf515f260 at pc 0x042434f0 bp 0x9ac24e78 sp 0x9ac24e68
WRITE of size 4 at 0xf515f260 thread T0
    #0 0x42434ef in nxsem_get_value semaphore/sem_getvalue.c:65
    #1 0x413110d in work_thread wqueue/kwork_thread.c:195
    #2 0x412c4f6 in nxtask_start task/task_start.c:129
    #3 0x427b1fc in pre_start sim/sim_initialstate.c:52

Address 0xf515f260 is located in stack of thread T0 at offset 32 in frame
    #0 0x928c9e3 in host_settimer sim/posix/sim_hosttime.c:104

  This frame has 1 object(s):
    [32, 48) 'it' (line 105) <== Memory access at offset 32 is inside this variable
HINT: this may be a false positive if your program uses some custom stack unwind mechanism, swapcontext or vfork
      (longjmp and C++ exceptions *are* supported)

Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-08-19 19:54:17 +08:00
Yanfeng Liu
3166c6d9c6 riscv/qemu-rv: add RPTUN cmake
This adds cmake support for RPTUN.
2024-08-19 19:53:03 +08:00
Windrow14
190c8787ff arch/xtensa/src/esp32s3/Kconfig|Make.defs|esp32s3_sdmmc.c,
arch/xtensa/src/esp32s3/hardware/esp32s3_sdmmc.h|esp32s3_soc.h,
boards/xtensa/esp32s3/common/include/esp32s3_board_sdmmc.h,
boards/xtensa/esp32s3/common/src/Make.defs|esp32s3_board_sdmmc.c,
boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c: add SD/mmc driver

Support 1-bit bus width and 4-bit bus width. Support eMMC high speed SDR mode.
Support transfer data with DMA. Support SD clock frequency up to 40MHZ.

Signed-off-by: Yinzhe Wu <Yinzhe.Wu@sony.com>
Reviewed-by: Yuezhang Mo <Yuezhang.Mo@sony.com>
Reviewed-by: Jacky Cao <Jacky.Cao@sony.com>
Tested-by: Yinzhe Wu <Yinzhe.Wu@sony.com>
2024-08-19 19:52:39 +08:00
chenrun1
12318bd947 xtensa_cache:add up_get_cachesize api
Summary:
  Added up_get_dcache_size and up_get_icache_size common APIs

Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
2024-08-19 13:54:53 +08:00
guoshichao
29e50ebed8 greenhills: add dummy implementation for unused function
add dummy implementation to avoid the link error

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-08-19 10:37:54 +08:00
yanghuatao
b3627bb8c6 toolchain/ghs: Fix zero used for undefined preprocessing identifier "NR_IRQS" warnings
CC:  unistd/lib_setregid.c "/mnt/yang/qixinwei_vela_warnings_04_23/nuttx/include/nuttx/irq.h", line 53: warning #193-D:
          zero used for undefined preprocessing identifier "NR_IRQS"
  #  if NR_IRQS <= 256
        ^
"/mnt/yang/qixinwei_vela_warnings_04_23/nuttx/include/nuttx/irq.h", line 82: warning #193-D:
          zero used for undefined preprocessing identifier "NR_IRQS"
  #if NR_IRQS <= 256
CC:  mount/fs_umount2.c "/mnt/yang/qixinwei_vela_warnings_04_23/nuttx/include/nuttx/irq.h", line 72: warning #193-D:
          zero used for undefined preprocessing identifier "NR_IRQS"
  #if NR_IRQS <= 256

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2024-08-19 10:37:54 +08:00
guoshichao
0cf0bece2e arch/strarg: provide the stdarg implementation for greenhills compiler
the greenhills compiler provide its own implementation of va_start,
va_end, va_arg, va_copy. so if we are build vela with greenhills
compiler, we should using the stdarg implementation provided by
greenhills, not our own

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-08-19 10:37:54 +08:00
xuxin19
9fdd299d32 cmake:split the archive process to avoid parameter problems
refer to:https://cmake.org/cmake/help/latest/variable/CMAKE_LANG_ARCHIVE_APPEND.html

this will solve the problem of too long parameters
when executing ar in cygwin environment such as msys.

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-08-18 23:26:01 +08:00
Yanfeng Liu
b9fde453ce riscv/qemu-rv: add RPTUN support
This adds initial RPTUN support for qemu-rv and rv-virt device.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-18 19:55:27 +08:00
Yanfeng Liu
2af5ad174f riscv/qemu-rv: add RPTUN Kconfig
This add RPTUN related Kconfigs for qemu-rv chip.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-18 19:55:27 +08:00
Eren Terzioglu
e11a53bec9 esp32[c3|c6|h2]: Add adjustable SPI clock speed 2024-08-17 13:43:58 +08:00
Tiago Medicci
69a8e2697f espressif: Fix default pins for SPI bus 2 on ESP32-[C3|C6|H2]
Fix the correct pin number for the SPI 2 bus on ESP32-C3, ESP32-C6
and ESP32-H2.
2024-08-17 13:43:58 +08:00
Eren Terzioglu
61dff51a33 esp32[c3|c6|h2]: Fix SPI clock issue 2024-08-17 13:43:58 +08:00
Jouni Ukkonen
9c2af7284b arch/arm64/imx93: Add more base addresses
mem slice and src base address added

Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-08-16 19:39:02 +08:00
Gao Feng
87ff0ddf6d xtensa/esp32s3: reserve memory for a mutex struct depending on the OS
Enabling CONFIG_PRIORITY_INHERITANCE config causes a build error

Based on Nuttx OS reserve memory for mutex struct.

Pass build based on
 - CONFIG_PRIORITY_INHERITANCE y
 - CONFIG_SEM_PREALLOCHOLDERS 0/8
2024-08-16 15:25:20 +08:00
Gao Feng
ddbbdd7fd3 xtensa/esp32s3: partition name duplicate and free 2024-08-16 15:11:14 +08:00
Jinliang Li
a5bfbca869 arm/armv8-r: invalidate d-cache on boot
Pass CP15_CACHE_INVALIDATE argument with r1 register to cp15_dcache_op_level.
cache level is 0(L1 D-Cache) with r0 register.
prototype:
void cp15_dcache_op_level(uint32_t level, int op)

Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
2024-08-16 13:41:19 +08:00
Jinliang Li
0e825b230d arm/armv8-r: add cp15 ops for mpu
Add some cp15 definitions for mpu configuration

Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
2024-08-16 13:27:31 +08:00
Alexis Guijarro
f05c85e622 arm/stm32h7x3x_rcc.c: Add External Power Supply option to stm32h7x3x targets 2024-08-15 02:52:45 +08:00
pengyiqiang
08cdff2046 arch/sim/Kconfig: set SIM_FBBPP to 32 by default
32bpp is the most commonly used option and should be used as the default

Signed-off-by: pengyiqiang <pengyiqiang@xiaomi.com>
2024-08-15 02:38:31 +08:00
chenxiaoyi
7ce5241f0e types.h: fix windows build error
Windows Kits\10\Include\10.0.22621.0\ucrt\corecrt.h(605,39): error C2371: 'wint_t': redefinition; different basic types
Windows Kits\10\Include\10.0.22621.0\ucrt\corecrt.h(606,39): error C2371: 'wctype_t': redefinition; different basic types

Co-authored-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
Co-authored-by: xuxin19 <xuxin19@xiaomi.com>
2024-08-14 22:36:57 +08:00
chenxiaoyi
f512f5e8a9 windows sim:add MSCV atomic support for fix windows build error
VC\Tools\MSVC\14.40.33807\include\vcruntime_c11_stdatomic.h(36,24): error C2061: syntax error: identifier 'atomic_bool'
VC\Tools\MSVC\14.40.33807\include\vcruntime_c11_stdatomic.h(36,24): error C2059: syntax error: ';'
VC\Tools\MSVC\14.40.33807\include\vcruntime_c11_stdatomic.h(37,23): error C2061: syntax error: identifier 'atomic_char'
VC\Tools\MSVC\14.40.33807\include\vcruntime_c11_stdatomic.h(37,23): error C2059: syntax error: ';'
VC\Tools\MSVC\14.40.33807\include\vcruntime_c11_stdatomic.h(38,30): error C2061: syntax error: identifier 'atomic_schar'
VC\Tools\MSVC\14.40.33807\include\vcruntime_c11_stdatomic.h(38,30): error C2059: syntax error: ';'

Co-authored-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
Co-authored-by: xuxin19 <xuxin19@xiaomi.com>
2024-08-14 22:36:57 +08:00
chenxiaoyi
b65efdba12 sim_hostmemory.c: fix windows build error
nuttx\arch\sim\src\sim\win\sim_hostmemory.c(39,40): error C2146: syntax error: missing ')' before identifier 'exec'
nuttx\arch\sim\src\sim\win\sim_hostmemory.c(39,35): error C2081: 'bool': name in formal parameter list illegal
nuttx\arch\sim\src\sim\win\sim_hostmemory.c(39,40): error C2061: syntax error: identifier 'exec'
nuttx\arch\sim\src\sim\win\sim_hostmemory.c(39,40): error C2059: syntax error: ';'
nuttx\arch\sim\src\sim\win\sim_hostmemory.c(39,44): error C2059: syntax error: ')'
nuttx\arch\sim\src\sim\win\sim_hostmemory.c(40,1): error C2449: found '{' at file scope (missing function header?)
nuttx\arch\sim\src\sim\win\sim_hostmemory.c(42,1): error C2059: syntax error: '}'

Co-authored-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
Co-authored-by: xuxin19 <xuxin19@xiaomi.com>
2024-08-14 22:36:57 +08:00
Yanfeng Liu
41dba46c1d arch/riscv: fix IRQ_SOFT for non-SMP
This fixes software interrupt number for non-SMP cases

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-14 20:59:52 +08:00
xuxin19
b073b3efc1 cmake:bugfix SIM_ASAN cannot automatically link libasan in cmake build
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-08-14 20:58:59 +08:00
simbit18
155517b5fc arch/sim/src/cmake/Toolchain.cmake: macOS fix unknown options: --gc-sections
fix
ld: unknown options: --gc-sections

added -> add_link_options(-Wl,-dead_strip)
2024-08-12 15:10:01 -03:00
Yanfeng Liu
f5b2fc371e riscv/qemu-rv: use cluster PLIC/CLINT configs
This uses cluster speficic PLIC, CLINT and ACLINT devices in NuttX.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-12 20:43:05 +08:00
Yanfeng Liu
6db85498a2 riscv/qemu-rv: add cluster PLIC/CLINT configs
This adds cluster specific configs for PLIC, CLINT and ACLINT
devices.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-12 20:43:05 +08:00
anjiahao
ce6d308cef armv8-m:fix log warnning
armv8-m/arm_securefault.c:72:11: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'uint32_t' {aka 'long unsigned int'} [-Wformat=]
   72 |   sfalert("\tCFSR: %08x HFSR: %08x DFSR: %08x\n", getreg32(NVIC_CFAULTS),
      |           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2024-08-12 01:52:35 +08:00
yanghuatao
fecc5091af toolchain/ghs: Fix SP_DSB warnings
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 252: warning #76-D:
          argument to macro is empty
        SP_DSB();
               ^

"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 261: warning #76-D:
          argument to macro is empty
    SP_DMB();
           ^

"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 252: warning #76-D:
          argument to macro is empty
        SP_DSB();
               ^

"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 261: warning #76-D:
          argument to macro is empty
    SP_DMB();
           ^

"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 296: warning #76-D:
          argument to macro is empty
        SP_DSB();
               ^

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2024-08-11 14:28:12 -03:00
guoshichao
693e869404 arm-m/barrier: fix green hills build ARM_ISB error
according to armv6-m/armv7-m arch reference manual:
the three ISB {<opt>}, DSB {<opt>}, DMB {<opt>} instructions <opt>
field are defined as:
Specifies an optional limitation on the ISB/DSB/DMB operation. Allowered
values are:
Full system ISB/DSB/DMB operation, encoded as option=='1111'. Can be
omitted.
All other encodings of the options are RESERVED.
the "#opt" field of "isb #opt"

So we could remove the options field in Armv7-m platform.
The following are the build error with greenhills compiler:

CC:  common/arm_exit.c [asarm] (error #2071) /tmp/gh_001h70j1.si 92: bad parameter
  isb 15
------^

[asarm] (error #2071) /tmp/gh_001h70j1.si 112: bad parameter
  isb 15
------^

[asarm] (error) errors during processing

According to armv8-m arch reference manual:
the ISB/DMB instruction's "opt" encoding rule is same as
armv6-m/armv7-m, but the "DSB" instruction is different, in armv8-m, the
"DSB {<opt>}" field has two valid encoding options: 0b0000, 0b0100.
and all other encoding options are reserved.

In Armv7-a/Armv8-a, the dsb/dmb option field has 8 valid state value.

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-08-11 14:28:12 -03:00
fangxinyong
6da525704d toolchain/ghs: fix the inline assembly code register alloc compile error
The following are the compile error that reported
by GreenHills compiler:

"/mnt/yang/qixinwei_commit/nuttx/include/arch/syscall.h", line 156 (col. 17): error #2036-D:
          cannot allocate "reg0" to specified caller-saved register

 "/mnt/yang/qixinwei_commit/nuttx/include/arch/syscall.h", line 157 (col. 17): error #2036-D:
          cannot allocate "reg1" to specified caller-saved register

Then we fix this greenhills compilation error by explicitly specifying
the registers in the clobber list in the inline assembly code.
This fix is successful in compiling on the
nuttx/boards/arm/mps/mps2-an500/configs/nsh platform and passes
the ostest test.
However, if we keep the implementation the same for both the default
and Greenhills compilers, the default compiler will report the
following two issues:
1. the "sys_call6" function will report compile error when
compiling on "./vendor/qemu/boards/smartspeaker/configs/smartspeaker-knsh"
platform, the detailed error info:

CC:  proxies/PROXY_mq_getattr.c In file included from /home/guoshichao/work_profile/vela_os/vela_qemu_1/nuttx/include/sys/syscall.h:35,
                 from /home/guoshichao/work_profile/vela_os/vela_qemu_1/nuttx/include/syscall.h:30,
                 from proxies/PROXY_mmap.c:5:
In function 'sys_call6',
    inlined from 'mmap' at proxies/PROXY_mmap.c:9:22:
/home/guoshichao/work_profile/vela_os/vela_qemu_1/nuttx/include/arch/syscall.h:297:3: error: 'asm' operand has impossible constraints
  297 |   __asm__ __volatile__
      |   ^~~~~~~

2. when running on qemu-armv7-a platform, the modification to
"smh_call()" function will make the system fail to boot up, so
we need to keep the default compiler implementation and greenhills
compiler implementation separate

Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
(cherry picked from commit cb48b749b1c9cad8cfb96bff7c5e9b6ebf20fc8a)
2024-08-11 14:28:12 -03:00
yanghuatao
5bb805b229 toolchain/ghs: Fix green hills toolchain build Vela asarm errors
common/gnu/fork.S 29: unknown instruction
  .syntax unified
--^
[asarm] (error #2230) common/gnu/fork.S 81: bad directive
  .type up_fork , function
------------------^
[asarm] (error #2067) armv7-m/arm_saveusercontext.S 31: unknown instruction
  .syntax unified
--^

[asarm] (error #2230) armv7-m/arm_saveusercontext.S 55: bad directive
  .type up_saveusercontext , % function
--^

[asarm] (error #2004) armv7-m/arm_saveusercontext.S 65: not within valid register range
  str r12 , [ r0 , ( 4 * ( ( ( 12 ) + ( 16 ) ) + 4 ) ) ]
------^

[asarm] (error #2004) armv7-m/arm_saveusercontext.S 66: not within valid register range
  str r14 , [ r0 , ( 4 * ( ( ( 12 ) + ( 16 ) ) + 5 ) ) ]
------^

[asarm] (error #2004) armv7-m/arm_saveusercontext.S 67: not within valid register range
  str r14 , [ r0 , ( 4 * ( ( ( 12 ) + ( 16 ) ) + 6 ) ) ]
------^

[asarm] (error #2014) armv7-m/arm_saveusercontext.S 72: expected a register
  str r1 , [ r0 , ( 4 * ( ( ( 12 ) + ( 16 ) ) + 7 ) ) ]
------------------^

[asarm] (error #2004) armv7-m/arm_saveusercontext.S 75: not within valid register range
  add r1 , r0 , ( 4 * ( ( ( 12 ) + ( 16 ) ) + 8 ) )
-----------^

[asarm] (error #2071) armv7-m/arm_saveusercontext.S 89: bad parameter
  stmia r0 ! , { r2 - r11 }
--------^

[asarm] (error #2014) armv7-m/arm_saveusercontext.S 93: expected a register
  mov r1 , - 1
-----------^

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2024-08-11 14:28:12 -03:00