This prevents us from getting stuck while polling the different
network structures in `devif_poll_connections`. This is useful for
Wi-Fi/Bluetooth coexistence, specifically.
- Fix macro values from `arch/xtensa/include/esp32s3/irq.h`
- Remove references to unexisting edge-triggered CPU interrupts
- Add `esp32s3_getirq` to get IRQ based on core and the `cpuint`
RTC subsystem controls not only the RTC itself but functions that
use RTC-enabled features like Bluetooth and Wi-Fi. Initialization
must be performed during the system start-up.
Verification:
Write a packet, the length is bigger than CONFIG_DEV_FIFO_SIZE.
The return value should be -1, and the errno is EMSGSIZE.
Signed-off-by: liqinhui <liqinhui@xiaomi.com>
Verifiction:
Write a bigger packet and read the packet using a smaller buffer.
The return length of reading should be the length of smaller buffer.
Signed-off-by: liqinhui <liqinhui@xiaomi.com>
The error log is as follows:
tcp/tcp_send_buffered.c:376:57: runtime error: member access within misaligned
address 0x10075942 for type 'struct tcp_sack_s', which requires 4 byte alignment
Signed-off-by: liqinhui <liqinhui@xiaomi.com>
Implement I_SUID/I_SGID feature for binfs in the POSIX compliant way.
If set-user-ID bit is set in the file permissions, then the effective
user ID of process shall be set to UID of the new process image file.
test case:
hello example emulates to set uid and file set-user-ID bit, and call
geteuid and getegid API.
UID = 2000
GID = 3000
MODE = 06555
nsh> ls -l /bin/hello
-r-sr-sr-x 2000 3000 0 hello
nsh> hello
geteuid:2000
getegid:3000
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
We use enter_critical_section to protect the read and write of priv structures,
sched_lock is mainly used to prevent active context switching caused by nxsem_post.
We do not actively switch contexts when reading and writing priv structures,
so sched_lock can be removed.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Supported external SDRAM (MT48LC4M32B2B5-6AIT:L) on STM32H745I-DISCO dev board.
Though MT48LC4M32B2B5-6AIT:L SDRAM itself provides 32-bit data bus, STM32H745I-DISCO board
routes only DQ[15:0] bits. Thus only half of the memory can be accessed: the accessible memory
configuration is only 1 Meg x 16 x 4 banks instead of 1 Meg x 32 x 4 banks.
Thus the accessible memory size is 8 MBytes.
Testing:
nsh> ramtest -a 0xD0000000 -s 8388608
RAMTest: Marching ones: d0000000 8388608
RAMTest: Marching zeroes: d0000000 8388608
RAMTest: Pattern test: d0000000 8388608 55555555 aaaaaaaa
RAMTest: Pattern test: d0000000 8388608 66666666 99999999
RAMTest: Pattern test: d0000000 8388608 33333333 cccccccc
RAMTest: Address-in-address test: d0000000 8388608
nsh>
Adding the CONFIG_ARCH_PERF_EVENTS configuration to enable
hardware performance counting，solve the problem that some platform
hardware counting support is not perfect, you can choose to use
software interface.
This is configured using CONFIG_ARCH_PERF_EVENTS, so weak_functions
are removed to prevent confusion
To use hardware performance counting, must:
1. Configure CONFIG_ARCH_PERF_EVENTS, default selection
2. Call up_perf_init for initialization
Signed-off-by: wangming9 <wangming9@xiaomi.com>
