Commit Graph

3 Commits

Author SHA1 Message Date
Xiang Xiao
0eeca0f375 build: Replace "$(shell $(INCDIR) $(CC) ...)" with $(INCDIR_PREFIX)
to unify the way to get include directories

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-06-23 00:11:25 +03:00
Ville Juven
9b5746cb5f riscv/barrier: Define more granular memory barriers
Separate barriers for full (memory + I/O) and local memory (cache) flushing.
2023-06-14 16:14:57 -03:00
Ville Juven
ae64f28344 RISC-V: Implement simple and native NuttX SBI
This is a minimalistic SBI implementation for NuttX.

Provides a single service for now:
- Access to machine timer

Provides a start trampoline to start NuttX in S-mode:
- Exceptions / faults are delegated to S-mode.
- External interrupts are delegated to S-mode.

Machine mode timer is used as follows:
- The timer compare match register reload happens in M-mode, via
  call gate "riscv_sbi_set_timer"
- The compare match event is dispatched to S-mode ISR, which will
  notify the kernel to advance time
- Clearing the STIP interrupt does not work from S-mode,
  so the call gate does this from M-mode

The only supported (tested) target for now is MPFS.
2023-06-07 01:48:15 +08:00