It seems like a wrong copy-and-paste from esp32c3.
Actually, internal memory mapping varies among processors.
esp32s3: lightly tested with wamr aot
esp32s2: not tested (i have no hardware access)
The bc022f8cd8 introduces a static way to calculate idle stack
address for risc-v platform. However, it uses the reverse order
to access idle stack, which breaks boards with smp configuration.
Correct the idle stack order of g_cpux_idlestack.
Fixes: bc022f8cd8 ("arch/risc-v: unify idle stack calculation")
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
As all the board allocate idle stack from _ebss. The idle stack
layout is fix and can be computed directly by using _ebss. There
is no need to use g_cpux_idlestack array anymore, remove it.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
As the stack layout is unified, it is possible to
use a unify formula to calculate the top of idle
stack.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
chip/s698pm_cpustart.c: In function 's698pm_cpu_boot':
Error: chip/s698pm_cpustart.c:74:17: error: unused variable 'tcb' [-Werror=unused-variable]
struct tcb_s *tcb = this_task();
^~~
cc1: all warnings being treated as errors
make[1]: *** [Makefile:99: s698pm_cpustart.o] Error 1
make[1]: Target 'libarch.a' not remade because of errors.
make: *** [tools/LibTargets.mk:164: arch/sparc/src/libarch.a] Error 2
make: Target 'all' not remade because of errors.
/github/workspace/sources/nuttx/tools/testbuild.sh: line 370: /github/workspace/sources/nuttx/../nuttx/nuttx.manifest: No such file or directory
Normalize s698pm-dkit/smp
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Make channels synchronous (i.e. share the same timebase) with the help
of SAMV7_PWMx_CHy_SYNC defines. All the channels share the same
timebase of channel 0, so this channel must be defined too.
Signed-off-by: Stepan Pressl <pressste@fel.cvut.cz>
ESP32 SoC use a static allocated array as idle stack. To fit
the existed idle stack allocation, make idle stack allocated
from ebss for the whole esp32 series.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Optimal size of granule is 64B (the dcache line size).
We can use it now as we don't have max. 32 granules limitation anymore.
Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
This adds SBI specfication v0.3 based `riscv_sbi_system_reset()` to
support SBI firmware based system reset in kernel mode.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
1. Adjust code to avoid PM wakelock->count less than or equal to 0.
2. Fix some document format issues.
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
Although almost all board support allocating idle stack after ebss,
bl602 have a different memory layout for idle stack. To unify them,
make idle stack allocated from ebss for bl602.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
NuttSBI have a simple ecall interface for the kernel, which make
it hard to add new SBI call for NuttSBI. So implement standard
ecall interface for NuttSBI and make life easier.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
With CONFIG_MMCSD_MULTIBLOCK_LIMIT not set. (No limit)
The DMA driver would overwrite the internal buffer.
By adding CONFIG_ARCH_HAVE_SDIO_PREFLIGHT and
CONFIG_FAT_DMAMEMORY we can insure alignment and
maximize performance using no CONFIG_MMCSD_MULTIBLOCK_LIMIT
Using user allocated buffers for DMA transfers is not safe for two reasons:
- User space memory is virtual memory, DMA needs physical memory
- User memory buffer alignment cannot be guaranteed -> cache line ops
are not safe
Add a simple allocator for DMA safe memory. It will provide contiguous
blocks of memory with D-Cache line size alignment.
NOTE: The optimal granule size is the D-Cache line size (64), but due
to restrictions in the granule allocator this would result in a maximum
block size of 2K only, thus use 256B granules instead givin 8K max block
size.
Once the granule allocator is fixed this limitation can be removed.
Option CONFIG_SENSORS_QENCODER might be configured even if SAMv7 qencoder
over timer counter is not used (for example encoder over GPIO is selected
with CONFIG_SAMV7_GPIO_ENC). This can cause compile warnings, also build
of sam_qencoder.c file is unnecessary in that case.
New hidden option CONFIG_SAMV7_QENCODER is added and automatically
selected if at least one timer counter is enabled for qencoder. Build
is triggered on this option.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
PWMx_CHy_LONLY options have been added to Kconfig, too.
If LONLY is selected, it's not possible to use complementary outputs.
If LONLY is not selected, it's possible to use H or complementary
output. If configured correctly with cpol and dcpol attributes,
a H-like behaviour can be achieved. May be useful when you run out
of free MCU pins.
Signed-off-by: Stepan Pressl <pressste@fel.cvut.cz>
The qemu-rv use a small init code for M mode in kernel build.
It is hard-coding and is difficult to change. Due to the fact,
introduce a already mature SBI implement (e.g OpenSBI) to
replace existing code is a better choice.
This patch introduce some change for qemu-rv:
1. use SSTC to provide time interrupt in kernel build
2. remove uncessary M mode trap.
For simplicity, this patch does not add support for booting
nuttx for any core, but force boot core to start core 0 and
let core 0 do the initialization.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
SSTC extension allows nuttx to implement S-mode timer directly,
which is useful for starting at S-mode.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
As `up_get_intstackbase` supports per cpu stack base, fix
the report value with the cpu specific one.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
It is misleading to allocate stack from static array and heap,
make all stack allocated from heap area.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
according to manual:
The FPU is not affected by any security configuration.
Thus, it appears as not present in PERIPHID[n].PERM
register located in the SPU
