This commit enhances SAMV7 serial driver with RS-485 mode available to
USART peripherals. The hardware automatically sets RTS pin high when
data are transfered and low then no transfer occurs. Only USART peripherals
support this mode, UART peripherals do not.
This mode can be enabled by configuration option SAMV7_USARTx_RS485MODE.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Summary:
- Since the stack coloration is done for every 32bits
this function should be done in the same way.
Impact:
- None
Testing:
- Tested with qemu-a53:nsh
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
bc_rxtail/rxtail should always point to newly frame.
If input more than one frame before receive,
missing assignment can result in old frame lost.
Signed-off-by: larry <larry@transtekcorp.com>
N/A
Summary:
Arm64 support for NuttX, Features supported:
1. Cortex-a53 single core and SMP support: it's can run into nsh shell at
qemu virt machine.
2. qemu-a53 board configuration support: it's only for evaluate propose
3. FPU support for armv8-a: FPU context switching at NEON/floating-point
TRAP is supported.
4. psci interface, armv8 cache operation(data cache) and smccc support.
5. fix mass code style issue, thank for @xiaoxiang781216, @hartmannathan @pkarashchenko
Please refer to boards/arm64/qemu/qemu-a53/README.txt for detail
Note:
1. GCC MACOS issue
The GCC 11.2 toolchain for MACOS may get crash while compiling
float operation function, the following link describe the issue
and give analyse at the issue:
https://bugs.linaro.org/show_bug.cgi?id=5825
it's seem GCC give a wrong instruction at certain machine which
without architecture features
the new toolchain is not available still, so just disable the MACOS
cibuild check at present
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
and remove CONFIG_LIBC_LONG_LONG option to simplify the usage.
note: the size will increase 668
before change:
text data bss dec hex filename
168440 348 4480 173268 2a4d4 nuttx
after change:
text data bss dec hex filename
169108 348 4480 173936 2a770 nuttx
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This patch introduces a configuration option USBMSC_WRMULTIPLE,
which is used to store multiple blocks into a larger chunk that
then gets written via the mmcsd_writemultiple() (in case mmcsd
is used).
The bottleneck with the current implementation is the poor
performance due to short block writes. USBMSC_DRVR_WRITE()
always writes only one sector (with eMMC that's usually 512 bytes).
eMMC devices usually erase much larger regions with near constant
time (see Jedec JESD84-B51, Extended CSD register byte [225],
SUPER_PAGE_SIZE): 'This register defines one or multiple of
programmable boundary unit that is programmed at the same time.'
If USBMSC_WRMULTIPLE is defined, then USBMSC_NWRREQS is used to
allocate the write buffer size. We don't want this to be the
default behavior yet as this may reveal unseen bugs in usb drivers
due to the faster overall performance.
Sample configurations with measured performance:
- Without USBMSC_WRMULTIPLE: 470 Kb/s
- With USBMSC_WRMULTIPLE, CONFIG_USBMSC_NWRREQS=4: 1.1 Mb/s
(dd with bs=2k)
- With USBMSC_WRMULTIPLE, CONFIG_USBMSC_NWRREQS=16: 5.2 Mb/s
(dd with bs=8k)
No doubt, this feature alone may make the mass storage work 10
times faster than before with eMMC cards.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
