Commit Graph

18739 Commits

Author SHA1 Message Date
Xiang Xiao
69a6072946 arch/ceva: Replace adj_stack_ptr with stack_base_ptr
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-17 11:06:09 +09:00
Xiang Xiao
814cab1cd1 arch/ceva: Mark the allocated stack with TCB_FLAG_FREE_STACK
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-17 11:06:09 +09:00
Xiang Xiao
f8df491d5d arch/ceva: Update tls handle to the latest mainline
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-17 11:06:09 +09:00
Xiang Xiao
4bc5b246ac arch/ceva: Remove B2C and C2B
since TL420 doesn't support anymore, we
can safely remove the special hack for it

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-17 11:06:09 +09:00
YAMAMOTO Takashi
85af0f37ad arch/sim/src/Makefile: Fix build issues with clang on linux
This commit fixes at least two issues.

* Fix a build with clang on linux

```
/usr/bin/ld: cannot open linker script file nuttx.ld: No such file or directory
clang: error: linker command failed with exit code 1 (use -v to see invocation)
```

* Restore symbol renaming for clang on linux

I guess it actually depends on the linker.
For now, use CONFIG_HOST_MACOS.

This fixed the following crash seen with sim/linux built with clang.

```
    #135462 0x0000000000404a81 in nxtask_exithook (tcb=0x48f310 <g_idletcb>, status=1, nonblocking=0 '\000') at task/task_exithook.c:618
    #135463 0x0000000000402aed in exit (status=1) at task/exit.c:103
    #135464 0x0000000000475833 in host_abort (status=1) at sim/up_hostmisc.c:48
    #135465 0x000000000040e6c6 in up_assert (filename=0x47b167 "semaphore/sem_wait.c", lineno=113) at sim/up_assert.c:126
    #135466 0x000000000040850b in _assert (filename=0x47b167 "semaphore/sem_wait.c", linenum=113) at assert/lib_assert.c:36
    #135467 0x0000000000403a40 in nxsem_wait (sem=0x7fca38b1c2d0) at semaphore/sem_wait.c:113
    #135468 0x0000000000403b43 in sem_wait (sem=0x7fca38b1c2d0) at semaphore/sem_wait.c:271
    #135469 0x000000000040aad3 in lib_stream_semtake (list=0x7fca38b1c2d0) at stdio/lib_libstream.c:159
    #135470 0x000000000040a8e7 in lib_flushall (list=0x7fca38b1c2d0) at stdio/lib_libflushall.c:61
    #135471 0x0000000000404c3c in nxtask_flushstreams (tcb=0x48f310 <g_idletcb>) at task/task_exithook.c:520
    #135472 0x0000000000404a81 in nxtask_exithook (tcb=0x48f310 <g_idletcb>, status=1, nonblocking=0 '\000') at task/task_exithook.c:618
    #135473 0x0000000000402aed in exit (status=1) at task/exit.c:103
    #135474 0x0000000000475833 in host_abort (status=1) at sim/up_hostmisc.c:48
    #135475 0x000000000040e6c6 in up_assert (filename=0x47b167 "semaphore/sem_wait.c", lineno=113) at sim/up_assert.c:126
    #135476 0x000000000040850b in _assert (filename=0x47b167 "semaphore/sem_wait.c", linenum=113) at assert/lib_assert.c:36
    #135477 0x0000000000403a40 in nxsem_wait (sem=0x7fca38b1c2d0) at semaphore/sem_wait.c:113
    #135478 0x0000000000403b43 in sem_wait (sem=0x7fca38b1c2d0) at semaphore/sem_wait.c:271
    #135479 0x000000000040aad3 in lib_stream_semtake (list=0x7fca38b1c2d0) at stdio/lib_libstream.c:159
    #135480 0x000000000040a8e7 in lib_flushall (list=0x7fca38b1c2d0) at stdio/lib_libflushall.c:61
    #135481 0x0000000000404c3c in nxtask_flushstreams (tcb=0x48f310 <g_idletcb>) at task/task_exithook.c:520

```
2022-02-17 09:36:20 +08:00
YAMAMOTO Takashi
7fcfe40821 arch/sim/src/Makefile: Fix whitespace 2022-02-17 09:36:20 +08:00
Peter Kalbus
6abdf73535 sim: Initial support on MacOS M1 and Linux AARCH64 based hosts. 2022-02-17 09:35:09 +08:00
Xiang Xiao
1d963058b4 arch/sparc: Replace adj_stack_ptr with stack_base_ptr
since adj_stack_ptr doesn't exist anymore

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-16 17:19:43 -03:00
Alan Rosenthal
8defb843aa Remove duplicate linker script definitions
## Summary
A lot of linker scripts were listed twice, once for unix, once for windows.

This PR cleans up the logic so they're only listed once.

 ## Impact
Any opportunity to use a single source of truth and reduce lines of code is a win!

 ## Testing
CI will test all build
2022-02-17 02:55:25 +08:00
Oki Minabe
68a305438b fix armv7-a gtm.h GTM_COMP1 and GTM_AUTO defines. 2022-02-16 18:50:42 +01:00
Oki Minabe
c1ea37742b fix arm FPSCR typos in comments. 2022-02-17 01:08:11 +08:00
Simon Filgis
cf008c94cc arch/arm/samv7: fix peripheral id shift during transmit xdma configuration 2022-02-16 17:16:53 +01:00
Masayuki Ishikawa
b60b6120de arch: armv7-a: Fix arm_syscall for SYS_pthread_start
Summary:
- I noticed that pthread always crashes when started
  if CONFIG_BUILD_KERNEL=y
- This commit fixes this issue

Impact:
- None

Testing:
- Tested with sabre-6quad:netknsh (not merged yet)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-02-16 13:06:25 +01:00
Petro Karashchenko
41c95da594 register_driver: fix driver modes accross the code
State of problem:
 - Some drivers that do not support write operations (does not
   have write handler or ioctl do not perform any write actions)
   are registered with write permissions
 - Some drivers that do not support read operation (does not
   have read handler or ioctl do not perform any read actions)
   are registered with read permissions
 - Some drivers are registered with execute permissions

Solution:
 - Iterate code where register_driver() is used and change 'mode'
   parameter to reflect the actual read/write operations executed
   by a driver
 - Remove execute permissions from 'mode' parameter

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-02-16 16:15:29 +08:00
Xiang Xiao
db57e2cd8e Fix the minor style issue
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-15 15:26:38 +01:00
Masayuki Ishikawa
34cf6949ac arch: armv7-a: Add debug messages for addrenv
Summary:
- This commit adds debug messages for addrenv

Impact:
- None

Testing:
- Tested with sabre-6quad:netknsh (not merged yet)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-02-15 17:22:52 +08:00
Masayuki Ishikawa
e7cb1b4fb1 arch: rt8920c: Move -fno-common option to ARCHCFLAGS/ARCHCXXFLAGS
Summary:
- Apply the same style as sabre-6quad

Impact:
- None

Testing:
- Build only

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-02-15 16:27:53 +08:00
Xiang Xiao
6b02e32904 arch/sim: Remove 08 from the format string in up_vfork
to make the code more general for both x86 and x64.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-15 06:44:21 +01:00
Xiang Xiao
e1879e35cd arch/sim: Always typedef xcpt_reg_t to unsigned long
to simplify the code logic

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-15 06:44:21 +01:00
Huang Qi
5cde8c6934 risc-v: Let g_cpu_basestack determined at compile time
Fix the CPU1 idle tasks stack corruption since the cpux's idle stack
is loaded from g_cpu_basestack (data section) before, but on this time
it maybe not ready since it is initialized by CPU0, and the value
from g_cpu_basestack is random.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-15 11:40:34 +09:00
Huang Qi
0d7f30c86d risc-v/k210: Move wfi to entry of the slave cpu boot routine
Fix another potential bug in non-smp case: load a value from overflowed address of g_cpu_basestack.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-15 11:40:34 +09:00
fenghang
555d25633a add phyplus_rel_1.4
update source for phyplus driver rel_1.4

update source  for phyplus driver rel 1.4

update source for phyplus driver 1.4

update phy6222 config files
2022-02-15 10:21:10 +08:00
Xiang Xiao
4207882cdc arm/armv8-m: Handle the special irq correctly in up_secure_irq
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-15 09:45:34 +09:00
David Sidrane
1ca952243c stm32h7:flash can not use usleep
commit 328374f4658d11655f268f968f4c6c7a3942f320

   changed the wait to use usleep. This killed the
   write performace from the published values in the
   datasheet of ~100 us to 2 mS per 256 bits. On
   a 1000 per tick config. It can be 10 X worse
   on the default 100 per tick config.

   This changes uses up_udelay.
2022-02-15 02:09:04 +08:00
David Sidrane
8659a31c9d stm32h7:flash Fix lock violations 2022-02-15 02:09:04 +08:00
David Sidrane
8ca4cf49b1 stm32h7:Fix build for all config {R|T}XDMA states 2022-02-14 18:43:30 +01:00
Xiang Xiao
17a7d612df arch: Replace nx_vsyslog with vsyslog
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-14 09:41:45 -03:00
chao.an
4be416a2a8 arm/backtrace: fix the compile warning
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-14 16:29:38 +08:00
Huang Qi
b8477f857b k210: Use common cpu idle stack implementation
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-14 11:32:34 +08:00
Huang Qi
55d88627a0 risc-v: Implement common up_cpu_idlestack
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-14 11:32:34 +08:00
raiden00pl
00917bfe9d stm32/fdcan: add CAN FD frames support 2022-02-14 10:42:01 +08:00
raiden00pl
dd8408a973 stm32/fdcan: use array indexes when accessing RX/TX FIFO 2022-02-14 10:42:01 +08:00
Michael Jung
70dae3bb3b Add arm_tcbinfo.c to stm32u5's common C sources
And re-order the list of common C sources alphabetically.

Signed-off-by: Michael Jung <mijung@gmx.net>
2022-02-13 16:32:35 +08:00
Michael Jung
5c1c939cdc stm32u5: Architecture Support for STM32U5
Architecture support for STMicroelectronics STMU585xx MCUs.  This is
based on corresponding code for STM32L5, but has been considerably
adjusted.  Tested with a B-U585I-IOT02A board and a simple NSH
configuration, but only running NuttX in the non-secure world with
TrustedFirmware-M.

Signed-off-by: Michael Jung <mijung@gmx.net>
2022-02-13 16:32:35 +08:00
Huang Qi
64130b4775 risc-v: Use _ebss instead of _default_stack_limit as idle stack base
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-13 14:37:57 +08:00
Michal Lenc
56b3fc0ef9 arch/arm/src/samv7: added support for PWM driver
This commit adds initial support for PWM driver to SAM MCU series.
Only general PWM on PWMH output is currently supported, complementary
output on PWML is not allowed. The current state of the driver also does
not support external triggering of other perihperals.

Multichannel option is supported. The functionality of the driver was
tested on an example pwm application and with a real time control system.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2022-02-13 03:20:07 +08:00
Huang Qi
95b0c85f58 arch: Add xxx_tcbinfo.c to SoC level Make.defs
Fix build break with CONFIG_DEBUG_TCBINFO enabled.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-12 21:07:35 +09:00
Peter Kalbus
271518a5ff sim: detect clang native compiler on MacOS. 2022-02-11 21:23:07 +08:00
Huang Qi
3fe9c9523c risc-v: Fix style issue in SoC's Make.defs
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-11 15:20:17 +08:00
Alan C. Assis
d49ad207ef esp32c3: Fix issue #5377 UART1 not working because clock as disabled 2022-02-11 10:01:25 +08:00
zhuyanlin
c833048484 xtensa:kconfig: move ARCH_HAVE_TESTSET config to chip
Some xtensa arch have not implentment testset instructions

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-10 14:22:58 +08:00
Huang Qi
7134220ae2 risc-v: Remove duplicated up_idle logic
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-10 13:09:32 +08:00
Huang Qi
9223547afc risc-v: Support cpu activity led in up_idle
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-10 13:09:32 +08:00
Huang Qi
6f18747dc2 risc-v: Add WFI to up_idle and fix compile issue
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-10 13:09:32 +08:00
zhuyanlin
3ab65f9b08 armv7-a/r: use flush/clean_all if size large than cache size
For cache flush/clean performance

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-09 18:16:31 +01:00
zhuyanlin
4eba2f3527 armv7-a/r:cache: add cp15_cache_size function
Add cp15_cache_size function for armv7-a/r

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-09 18:16:31 +01:00
Huang Qi
9d91d69ee0 arch/risc-v/mpfs: Remove riscv_pthread_exit.c in Make.defs
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-09 21:21:43 +08:00
Huang Qi
c0a0de97ce Revert "libc: Call pthread_exit in user-space by up_pthread_exit"
This reverts commit f4a0b7aedd.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-09 21:21:43 +08:00
Alin Jerpelea
0cfdfde6c7 arch: sim: update licenses for FishSemi
FishSemi is part of Xiaomi and according to xiaoxiang781216
the SGA covers those files

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2022-02-09 19:58:52 +08:00
Alin Jerpelea
7a674b6287 Makefiles: change license to Apache
Make files are recipes based on contributions from from Gregory Nutt

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2022-02-09 19:58:52 +08:00
Alin Jerpelea
e2725d536a arch: sim: update licenses to Apache
Gregory Nutt is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2022-02-09 19:58:52 +08:00
zhuyanlin
cc8ab23550 armv7-r/a: fix a4 register use in xxx_invalidate/flush/clean_all.S
Use sub loop instead of add loop

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-08 19:39:43 +09:00
SPRESENSE
8de07b2ae8 boards: cxd56xx: audio: Support I2S input
Enable the driver setting of I2S input.
2022-02-08 10:47:03 +01:00
Xiang Xiao
963feca4a1 arch/sim: Don't add up_tls_size in up_use_stack before foward to up_create_stack
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-07 08:45:34 +01:00
Xiang Xiao
202b8141a6 arch/sim: Adjust the stack size for up_use_stack too
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-07 13:36:51 +08:00
Xiang Xiao
5749ea6604 arch/sim: Unify the return value of usrsock_xxx_handler
All handler should return the result of usrsock_send_[dack|event]

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-07 13:18:19 +08:00
raiden00pl
bc178344a9 net/can: add an option to control CAN EXTID support 2022-02-06 17:09:11 +08:00
raiden00pl
341bbe38d5 arch/stm32: add FDCAN SocketCAN support 2022-02-06 17:09:11 +08:00
Petro Karashchenko
e545c440f4 arch/arm/samv7/sam_progmem: insert DMB instruction into data write loop
This change fix the regression that was introduced with
https://github.com/apache/incubator-nuttx/pull/4904

In case if D-Cache in configured in Write-Through mode there is
Cortex-M7 erata 1313001 that describes a situation when linefill
buffer or cache contains stale data. Even if progmem write loop
does not fully matches the description there is a possibility
to program stale data if there is no DMB instruction after each
write operation to progmem latch buffer.

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-02-05 03:14:07 +08:00
Petro Karashchenko
47a09ed255 arch/arm/samv7: add arm_systemreset.c to CMN_CSRCS
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-02-04 16:40:50 +08:00
Abdelatif Guettouche
f826e053ae arch/xtensa/esp32: Remove the QEMU special case when initializing the
heap.

QEMU had a different ROM image that used the regions of PRO CPU for both
CPUs.  This was causing crashes when running SMP mode as the heap was
being corrupted when the APP CPU starts.

QEMU is now loading the same image as the hardware chip and thus this
special case doesn't exist anymore.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-02-03 16:18:09 -03:00
chao.an
3ab557e748 arch/xtensa: correct the netlock handling
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-03 11:09:18 -03:00
chao.an
ed4f852073 arch/arm: correct the sched_lock/spin_lock handling
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-03 11:09:18 -03:00
zouboan
ad3f16358e enable sparc's daily ci and eliminate some warnings 2022-02-03 14:43:21 +01:00
chao.an
0be55bef64 arch/renesas: fix nxstyle warning
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-02 21:45:13 +08:00
chao.an
8e004839b6 arch/renesas: fix leaving from critical section
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-02 21:45:13 +08:00
chao.an
d59931159a arch/arm: fix leaving from critical section
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-02 21:45:13 +08:00
Xiang Xiao
4c167b0729 Correct the code alignment
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-01 21:22:21 -03:00
Xiang Xiao
f987668068 serial: Consolidate the general termios in the common place
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-01 21:22:21 -03:00
zouboan
95542f193b sparc adaptive patch 2022-02-01 17:16:21 +08:00
Petro Karashchenko
601a0e8a32 arch/arm/samv7: fix leaving from critical section in HSMCI callback
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-31 16:56:52 -03:00
Abdelatif Guettouche
f49a579721 esp32c3/: Remove unused exported variables from ROM and add declaration
for the one used.
2022-01-31 23:35:50 +08:00
Xiang Xiao
2c3020ddaf arch/Toolchain.defs: Replace --print-file-name=libgcc.a with --print-libgcc-file-name
to more compatable with clang: https://reviews.llvm.org/D25338

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-31 09:46:04 +01:00
Xiang Xiao
e0b62bf677 arch/Toolchain.defs: Don't expand EXTRA_LIBS immediately
since board's Make.defs may overwrite ARCHCPUFLAGS

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-30 11:04:35 +09:00
David Sidrane
0f1342f36b stm32:Add OTG ID GPIO disable 2022-01-30 01:50:37 +08:00
David Sidrane
99083b8dd1 stm32{f|h}7:Fixed typo in Kconfig help 2022-01-30 01:49:57 +08:00
chao.an
7d8c2c1ad6 cortex-m/doirq: do not update the CURRENT_REGS on nested interrupt handling
current implementation incorrectly update CURRENT_REGS to interrupt context if
trigger nested interrupt, (e.g, hard fault occurs during interrupt handling)
this would ambiguous for programs using CURRENT_REGS, this patch will prohibit
the update of CURRENT_REGS on nested interrupt handling

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-01-29 01:04:00 +08:00
Xiang Xiao
1c2c0e4707 arch/Toolchain.defs: Simplify the builtin library addition for EXTRA_LIBS
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-28 12:02:38 +01:00
Alexander Lunev
b2f3cefe3d sim/netdev,tapdev: implemented emulation of TX done and RX ready interrupts
and removed two tcp_send_txnotify() calls from tcp_sendfile (they are not needed anymore).

As a result, the TX throughput of both the tcp_send_buffered and tcp_send_unbuffered
is significantly boosted in case of TUN/TAP network device.
2022-01-28 18:16:42 +08:00
Gustavo Henrique Nihei
b0d24f53c4 xtensa: Add initial support for ESP32-S3
Co-authored-by: Alan Carvalho de Assis <alan.carvalho@espressif.com>
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-27 13:46:50 -03:00
Fotis Panagiotopoulos
f8ba016d72 sim: Added Kconfig option for UART buffer size. 2022-01-27 17:15:17 +01:00
Ville Juven
7c116efe05 Add support for a ROMFS image for MPFS
The image must be placed into:
boards/risc-v/mpfs/icicle/include/boot_romfsimg.h

The image is mounted by mpfs_bringup, which is run by the application
itself, or by board_late_initialize() in the case when
CONFIG_BOARD_LATE_INITIALIZE is defined, e.g. with CONFIG_BUILD_KERNEL
2022-01-27 11:06:43 -03:00
Petro Karashchenko
0ffffe19b1 typo: change evernt to event in comments
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-27 09:57:31 -03:00
Xiang Xiao
f903a55102 sched/tcbinfo: Fix the compile warning
Update tcbinfo struct

armv8-m/arm_tcbinfo.c:109:3: warning: excess elements in struct initializer
  109 |   TCB_REG_OFF(REG_S31),
      |   ^~~~~~~~~~~
armv8-m/arm_tcbinfo.c:109:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:110:3: warning: excess elements in struct initializer
  110 |   0,
      |   ^
armv8-m/arm_tcbinfo.c:110:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:111:3: warning: excess elements in struct initializer
  111 |   TCB_REG_OFF(REG_FPSCR),
      |   ^~~~~~~~~~~
armv8-m/arm_tcbinfo.c:111:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:112:3: warning: excess elements in struct initializer
  112 |   0,
      |   ^
armv8-m/arm_tcbinfo.c:112:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:37:1: warning: missing braces around initializer [-Wmissing-braces]
   37 | {

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-27 17:36:27 +08:00
Ville Juven
4bd1bd177b RISC-V MMU: Add missing implementation for PTE getter
For some reason this was (mistakenly) left out from the patch
that was supposed to have it.
2022-01-27 10:22:30 +01:00
zhuyanlin
644c2be3aa armv7-a/r:cache: implemention clean&flush_dcache_all
For armv7-a/r cache:
And clean_dcache_all, flush_dcache_all

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-27 15:15:28 +08:00
zhuyanlin
1b08f607be arm/xtensa:cache: flush/clean dcache all if size large than cache size
For performance, if size large than cache size, use xxx_all instead

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-27 15:15:28 +08:00
zhuyanlin
4d5c2586a9 armv7-a/r:cp15_invalidate_dcache_all: fix Sets mask error.
As NumSets field is bits 13-27, use 0x7fff instead.
And add way to get from CCSIDR.
2022-01-27 15:13:08 +08:00
Petro Karashchenko
311efcd180 arch/z80: fix garbage collector option to linker
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-26 16:50:59 +08:00
Petro Karashchenko
48211f90d3 ci: select ARMV7A_TOOLCHAIN_GNU_EABIL for ARMv7-A based builds
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-25 20:24:28 +08:00
Ville Juven
fc3cd308d5 Wipe the PMP configuration in MPFS bootloader start routine
This way old PMP configurations are removed upon warm reset.
2022-01-25 20:22:34 +08:00
Ville Juven
81188d9c94 Extend the RISC-V PMP functionality
- Add test for mode support, which is architecture dependent
- Add tests for address alignment and region size
- Add option to query for access rights
 - The function goes through every PMP entry and tests if an address
   range from [base, base+size] has been configured for desired
   access rights.
 - If several PMP entries match the range and access rights, the
   information is combined
 - End result is either no access, a partial match was found, or a full
   match was found. Details about the partial match are not provided.

The intent for testing access rights and not just blindly applying them
is a case where they are already set in e.g. a bootloader. In this
case, nothing should be done, unless the configuration does not match,
in which case the software must not continue further.
2022-01-25 20:22:34 +08:00
Ville Juven
8a4881c4e5 Implement CONFIG_BUILD_PROTECTED with MMU
NOTE: THIS ONLY WORKS WHEN KERNEL RUNS IN M-MODE FOR NOW

This frees the PMP for other use, e.g. HART memory separation.

The page tables are statically allocated, 1 per level.

This feature is now behind CONFIG_MPFS_USE_MMU_AS_MPU, because
only the MPFS target supports this (others are not tested).

If the MMU is used for memory separation within a HART, the PMP must
still be configured to allow user access to the memory mapped for the
HART, because PMP *rekoves* access by default. At this point all of
the user memory as well as the kernel RAM are opened.

A more flexible solution for PMP configuration will follow.
2022-01-25 20:22:34 +08:00
Ville Juven
7eb726d57f Add proper user/kernel space linker scripts for knsh target
The old implementation used the default ld.script for the kernel side
which did not obey the memory.ld limits whatsoever.

Also, provide the user space addresses from the linker script to get rid
of the pre-processor macros that define (incorrect) default values for
the user space composition.
2022-01-25 20:22:34 +08:00
Masayuki Ishikawa
7b1cf2dfac arch: arm: Fix make export for armv7-a SoCs
Summary:
- I noticed that make export does not work with swama5d4-ek:knsh
- This commit fixes this issue.
- NOTE: apps/Makefile also needs to be updated.

Impact:
- CONFIG_BUILD_KERNEL=y only

Testing:
- Build (make and make export) with sama5d4-ek:knsh

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-01-25 11:05:22 +08:00
Jukka Laitinen
49085eebae arch/risc-v/src: Cleanups for opensbi
- remove some unneeded includes
- tab/space fixes
- change DEBUGPANIC to PANIC in noreturn function, otherwise it compiles only in DEBUG builds

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-25 00:10:46 +08:00
Jukka Laitinen
5bb3936212 arch/risc-v/src/opensbi: Update 3rd party opensbi version into Make.defs
This fixes build errors with more strict compiler settings

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-25 00:10:46 +08:00
Jukka Laitinen
8a6d62423d Revert "risc-v/mpfs: switch to NuttX types for opensbi"
This reverts commit d611e2d99b.
2022-01-25 00:10:46 +08:00
Eero Nurkkala
eb462a2eb3 risc-v/mpfs: configure harts according to CONFIG_MPFS_HART*_SBI
The following options need to be taken in account while determining
the proper hart_index2id -table:
  CONFIG_MPFS_HART1_SBI
  CONFIG_MPFS_HART1_SBI
  CONFIG_MPFS_HART3_SBI
  CONFIG_MPFS_HART4_SBI

Unused harts should be marked with -1. Hart0 is never used so it
stays at -1.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-01-24 23:25:53 +08:00
Huang Qi
71d3ff1045 arch/risc-v: Remove g_serial_ok
`WFI` is enough to wait the ready signal from master core,
so we can remove it.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-23 18:28:37 +08:00