This commit removes the initialization of the Wi-Fi partition
from the Wi-Fi board logic and moves it to the SPI Flash board code.
It creates 2 different partition (one for Wi-Fi and one for general
use).
It also allows these partitions to be mounted over several FSs.
The name used in Tensilica support file core-isa.h for all vendors is
`XCHAL_NUM_INTLEVELS`.
Use a new name may be confused by newer porting xtensa arch.
Change-Id: Ie108d3fdfcc02c81f0eacfca852a1cfc9eea17de
The PRO CPU and APP CPU have different peripherals for GPIO interrupts.
Each CPU needs to allocate an interrupt and attach it to its GPIO
peripheral.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Matrix.
This allows manipulating interrupts from both CPUs. Internal interrupts
however, still need to be disabled/enabled by each CPU.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
They do the same thing (manipulate interrupts) keeping them separated
was making things harder.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Allocating and attaching interrupts were both exported outside, however
these two move hand in hand and we don't have to expose these details.
Also, the parameters passed are saved and will be used to retrieve
information about the interrupt and the attached peripheral.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
interrupt.
That function will have a parameter to decide whether to allocate a
level sensitive interrupt or an edge sensitive interrupt.
All the drivers are also updated with this API change.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
are do not go through the regular process where we attache the CPU
interrupt to a peripheral and update our map, also, they are fixed and a
have reserved CPU interrupt, thus hard code their values at startup.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
At this point we are in a critical section and have all the necessary
information to disable the interrupt properly (CPU, and CPU interrupt).
Leaving it to the drivers will complicate things as converting from IRQs
to CPU interrupts could be tricky in SMP mode.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
This map also keeps track of the CPU that attached the IRQ. This will
be used to properly disable the interrupt in the correct CPU in SMP
mode.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
ESP32 uses a different function to start the app CPU and no other xtensa
CPU uses this __cpu1_start function.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Consider follow coprocessor configuration case:
\#define XCHAL_CP_NUM 1 /* number of coprocessors */
\#define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */
\#define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */
\#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
\
\#define XCHAL_CP1_NAME "AudioEngineLX"
\#define XCHAL_CP1_IDENT AudioEngineLX
\#define XCHAL_CP1_SA_SIZE 208 /* size of state save area */
\#define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
\#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
In this case, XTENSA_CP_ALLSET is 0x1, but valid coprocessors
bitmap is 0x2, use marco XCHAL_CP_MASK instead, it is bitmap of all
vaild coprocs.
Change-Id: I63ec01e4bd0cbafc62d56636cc11bdc4a2f7857f
Many duplicate code when more chips add-in,
follow arch/arm/include/irq.h method, use chip/irq.h instead.
Change-Id: I42f516c1dda68e973939c669f627c457cd0bc65e
In levelx(2,3,4,5)_handler, first need to save sp in a12,
then after dispatch_c_isr we can restore sp from a12.
Change-Id: Idb6b64a782da866670a4db80b33435a9b63f02c3
Some toolchain such as xtensa-xcc is unrecognize with constraint letter 'I',
letter 'i' is more common in GNU assembler.
Change-Id: I00f6a33fd7a5f2b95508c683e9954d402b68755f
In config with no "CONFIG_SPINLOCK", include arch/spinlock.h will lead to
build error as multi definition with spinlock_t. Nuttx/spinlock.h will
include arch/spinlock.h when needed.
Change-Id: I33b48503f679ec79af3a0ef1f0fb1536aaf1ce7c
Currently the "esp32_spiflash_alloc_mtdpart" allocates a
statically-defined partition from "offset" and "size" set via
Kconfig.
This commit changes the function interface to receive those information
as arguments, enabling the creation of multiple MTD partitions with
different offsets and sizes.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Cleaning during `clean_context` had the issue of remaking everything
when `menuconfig` was issued. That's because `menuconfig` has a
`clean_context` on its way.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
use the same condition check in declaration and reference
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I7b05316e914708fceeddac394d784ee3720a3c1b
it's more simple to make mm_heap_s opaque outside of mm
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I5c8e435f6baba6d22b10c5f7e8d9191104fb5af2
needed anymore.
Decouple the IRAM heap from the text allocator since that heap can
still be used as a generic pool of memory.
Implement the up_extraheaps_init function to initialize all of the
additional heaps.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Write protection must be disabled before performing changes to the WDT
registers. Furthermore, the routine was resetting the wrong field from
the RTC WDT register.
The RTC_CNTL_WDT_FLASHBOOT_MOD_EN field relates to Flash Boot Protection
and it is enabled by the 1st stage bootloader. The 2nd stage bootloader
takes care of disabling it.
Then the 2nd stage bootloader enables the RTC WDT for checking the
startup sequence of the application image.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
This memory region can be accessed by both I & D buses, so the heap can
be used for data storage and code execution.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Summary:
- I noticed that the getcoreid macro in the latest esp-idf
is much simpler than the current NuttX's.
- This commit replaces the macro with the latest esp-idf's
Impact:
- SMP only
Testing:
- Tested with esp32-devkitc:wapi_smp
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
instead calling kmm_heapmember or umm_heapmember because:
1.The stack supplied by caller may allocate from heap too
2.It's hard to implement these two function in ASan case
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I196377822b7c4643ab4f29b7c1dc41dcd7c4dab1
Summary:
- According to the Xtensa ISA document, this ISYNC instruction
between WSR SCOMPARE1 and S32C1I is unnecessary
Impact:
- SMP only
Testing:
- Tested with esp32-devkitc:wapi_smp
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I noticed that DEBUGASSERT sometimes happens in nxsem_wait()
when testing Wi-Fi with esp32-devkitc:wsifi_smp
- The call stack was not from an interrupt handler and actually
g_current_regs[] were correct, even though asserted with
(up_interrupt_handler() == false)
- Finally, I found that we need to call rsync after we set
a new value to the PS register which is described in the
Xtensa document.
- This commit fixes this issue
Impact:
- All xtensa architectures
Testing:
- Tested with esp32-devkitc:wifi_smp and esp32-devkitc:wifi
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
All modern desgin support stack pointer and it's also an
important information, so let's standardize this interface.
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Summary:
- SP_SECTION was introduced to allocate spinlock in non-cachable
region mainly for Cortex-A to stabilize the NuttX SMP kernel
- However, all spinlocks are now allocated in cachable area and
works without any problems
- So SP_SECTION should be removed to simplify the kernel code
Impact:
- None
Testing:
- Build test only
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- The CONFIG_SMP_IDLETHREAD_STACKSIZE was introduced to optimize
the idle stack size for other than CPU0
- However, there are no big differences between the idle stacks.
- This commit removes the config to simplify the kernel code
Impact:
- All SMP configurations
Testing:
- Tested with ostest with the following configs
- spresense:smp, spresense:rndis_smp
- esp32-devkitc:smp (QEMU), maix-bit:smp (QEMU)
- sabre-6quad:smp (QEMU), sabre-6quad:netnsh_smp (QEMU)
- raspberrypi-pico:smp, sim:smp (x86_64)
Signed-off-by: Masayuki Ishikawa <asayuki.Ishikawa@jp.sony.com>
This config is only useful when there is a > 4MB PSRAM and thus needs to
be selected by the user explicitly.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
arch: Allocate the space from the beginning in up_stack_frame
and modify the affected portion:
1.Correct the stack dump and check
2.Allocate tls_info_s by up_stack_frame too
3.Move the stack fork allocation from arch to sched
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
I've seen a module with 16 bytes .rodata alignment for xmm operations.
It was getting SEGV on sim/Linux because of the alignment issue.
The same module binary seems working fine after applying this patch.
Also, tested on sim/macOS and esp32 on qemu,
using a module with an artificially large alignment. (64 bytes)
Some ESP32 GPIO pins (2, 4, 12, 13, 25, 27, 32) weren't accepting
pull-up/pull-down resistors. These pins are RTC GPIO pins and need
to have pull-up/pull-down configured in the RTC registers.
Co-authored-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
All supported arch uses a push-down stack:
The stack grows toward lower addresses in memory. The stack pointer
register points to the lowest, valid working address (the "top" of
the stack). Items on the stack are referenced as positive(include zero)
word offsets from sp.
Which means that for stack in the [begin, begin + size):
1.The initial SP point to begin + size
2.push equals sub and then store
3.pop equals load and then add
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Espressif Systems has submitted the SGA and we can migrate the licenses
to Apache.
Gregory Nutt has submitted the SGA and we can migrate the licenses
to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Previously SPI interrupts were enabled on DMA initialization. But since
the addition of SPI Mixed mode it created a side-effect, breaking
polling transfers. So now interrupts are enabled before the DMA
transactions and disabled once they are finished.
Furthermore, the transaction done flag is also cleared before a new
transaction starts.
Commit 6382b2ba introduced the possibility of using SPI in Mixed mode,
i.e. performing SPI transfers via both polling and interrupts. However,
setbits was only applying the configuration if DMA was not enabled.
is enabled.
That region is technically part of the PRO CPU and we should be able to
allocate it early. However, QEMU uses a slightly different bootloader
image that uses the same part for both CPU. So, when APP CPU starts
during the SMP bring up it will corrupt some data.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
In case CONFIG_MM_REGIONS doesn't include all the available memory
regions the user will have a warning to increase it.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Internal heap was occupying the region straight after .data up to
HEAP_REGION1. The issue with this is if static allocation is large,
we'll end up with too little memory left for the internal heap.
Moving it to the beginning of region 2 gives us more room to play with.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
