Commit Graph

268 Commits

Author SHA1 Message Date
Abdelatif Guettouche
39016f6d68 risc-v/esp32c3: Configure clock and call board initialize at startup.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-25 22:13:26 -08:00
hotislandn
651b905b99 arch:rv64:add API up_copyfullstate for later FPU support.
Signed-off-by: hotislandn <hotislandn@hotmail.com>
2021-02-25 11:26:27 -08:00
Gustavo Henrique Nihei
7fe096c65e risc-v: Fix typos reported by codespell 2021-02-25 16:25:47 +00:00
hotislandn
30cb7d3983 arch:rv32:up_sigdeliver missing fpu contexts.
Signed-off-by: hotislandn <hotislandn@hotmail.com>
2021-02-24 23:42:18 -08:00
Gustavo Henrique Nihei
6edeb9ebd9 risc-v/esp32c3: Free CPU interrupt if irq_attach fails 2021-02-24 15:56:26 +00:00
Gustavo Henrique Nihei
5c24c98880 risc-v/esp32c3: Invalidate CPU interrupt number after free 2021-02-24 15:56:26 +00:00
Abdelatif Guettouche
fb68a4b777 esp32c3: Add system reset.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-23 18:13:02 -08:00
Gustavo Henrique Nihei
48ff647fe9 risc-v/esp32c3: Fix erroneous references to ESP32-C3 2021-02-23 18:12:16 -08:00
Gustavo Henrique Nihei
af8e71d9e9 risc-v/esp32c3: Fix inconsistent guard comment 2021-02-22 09:24:14 -08:00
Gustavo Henrique Nihei
628e2288aa risc-v/esp32c3: Add missing header guard for lowputc 2021-02-22 09:24:14 -08:00
Gustavo Henrique Nihei
ca30c1db69 risc-v/esp32c3: Build serial driver only when selected 2021-02-22 09:24:14 -08:00
Abdelatif Guettouche
491a4c1ed2 risc-v/esp32c3: Don't reserve any vectors for any special use.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-22 09:21:24 -08:00
Gustavo Henrique Nihei
291a5755cc risc-v/esp32c3: Add support for MWDT0 and MWDT1 2021-02-22 17:18:01 +00:00
Abdelatif Guettouche
067da56d0c esp32c3: Some cosmetics and style fixes.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-21 10:29:43 -03:00
Abdelatif Guettouche
10822799fb esp32c3: Add GPIO IRQ support.
The GPIO example was also extended to include testing an interrupt pin.

Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Co-authored-by: Alan Carvalho <alan.carvalho@espressif.com>
2021-02-21 10:29:43 -03:00
Alan Carvalho
4a42998f36 esp32-c3: Add the GPIO driver.
This commits adds support for the ESP32-C3 IO Mux and GPIO Matrix.  It
also includes necessary board logic to run the GPIO example with 2
outputs.

Co-authored-by: Alan Carvalho <alan.carvalho@espressif.com>
Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-21 10:29:43 -03:00
Abdelatif Guettouche
4c3412faaa risc-v/esp32c3: Add clock configuration
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-18 01:21:53 -08:00
Sara Souza
998f7e5d4c risc-v/esp32c3: Add basic UART support for console 2021-02-18 01:21:53 -08:00
Dong Heng
b11a5ca8b2 risc-v/esp32c3: Add ESP32-C3 basic support
Co-authored-by: Dong Heng <dongheng@espressif.com>
Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-18 01:21:53 -08:00
David Jablonski
41bddc8461 litex: fix mtime and mtimecmp register address 2021-02-13 15:24:28 -08:00
David Jablonski
11167857c3 litex: nsh working 2021-02-13 15:24:28 -08:00
jpeng
af42079cc7 fix spi bug 2021-02-13 10:31:25 -08:00
liang
5914af84c7 arch/risc-v/bl602: spi_master support. 2021-02-13 10:31:25 -08:00
hotislandn
84daebf2cc arch:risc-v:bl602: enable FPU for this target. 2021-02-08 00:29:34 -08:00
Masayuki Ishikawa
d87f350831 arch, boards, drivers, include, sched, wireless: Change spinlock APIs.
Summary:
- This commit changes spinlock APIs (spin_lock_irqsave/spin_unlock_irqrestore)
- In the previous implementation, the global spinlock (i.e. g_irq_spin) was used.
- This commit allows to use caller specific spinlock but also supports to use
  g_irq_spin for backword compatibility (In this case, NULL must be specified)

Impact:
- None

Testing:
- Tested with the following configurations
- spresnse:wifi, spresense:wifi_smp
- esp32-devkitc:smp (QEMU), sabre6-quad:smp (QEMU)
- maxi-bit:smp (QEMU), sim:smp
- stm32f4discovery:wifi

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-02-07 21:28:56 -08:00
Abdelatif Guettouche
6547c3df55 arch/riscv: Fix file names in headers that were still using the old 'up_' prefix.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-05 21:19:20 -03:00
Abdelatif Guettouche
5447f28742 riscv: Remove the nx_start prototype from riscv_internal.h
This function is already declared in include/nuttx/init.h include this
file instead.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-02 17:48:40 -03:00
Abdelatif Guettouche
db2a8f0dc5 arch/risc-v: Remove incorrect ARM references.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-02 17:48:06 -03:00
Abdelatif Guettouche
37b93bd498 arch/risc-v: Don't declare riscv_addregion if CONFIG_MM_REGIONS is < 1.
Don't declare riscv_addregion if CONFIG_MM_REGIONS is < 1, so we won't
have to provide a dummy stub for every chip.
Also rename the function from up_addregion to riscv_addregion since it's
not exported outside the arch directory.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-01 18:45:25 -08:00
Abdelatif Guettouche
52b4c73a61 arch/riscv: Remove references to MIPS.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-01-30 15:46:38 -08:00
Abdelatif Guettouche
0f2b774dec arch/risc-v: Remove unused and undefined file section "Public Variables"
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-01-27 18:40:10 -08:00
Xiang Xiao
94da3e4c3a arch: Remove critical section inside up_schedule_sigaction
since nxsig_tcbdispatch already hold it for us

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I2fe6ad840bdca3ec0eaa76a9af3b6929c7d5a721
2021-01-22 08:34:07 +01:00
liang
caf2d1430e arch/risc-v/bl602: add gpioirq and i2c(master) driver 2021-01-14 08:55:03 -08:00
liang
32708ab849 arch/risc-v/bl602 : add spiflash(hardware sf controller) 2021-01-11 17:59:00 -08:00
liang
2889315c20 arch/risc-v/bl602 : add pwm onshot watchdog driver. 2021-01-06 23:40:37 -08:00
Brennan Ashton
dd26d9c9f9 BL602: Add support for system reboot modes
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
2021-01-02 00:14:37 -06:00
Brennan Ashton
c8db3293bb BL602: Use sig mask instead of number for AHB swrst 2020-12-30 23:27:42 -06:00
Brennan Ashton
e062bd08ce bl602: Update register defines and drivers 2020-12-30 23:27:42 -06:00
Virus.V
5f71e2be79 fix ci build failed 2020-12-29 01:52:09 -08:00
Virus.V
3e0a84182e check bl602 license 2020-12-29 01:52:09 -08:00
yangyue
d354a2f19f fix some code style 2020-12-29 01:52:09 -08:00
Virus.V
12258d72d2 Fix the BL602 mtimer frequency error. 2020-12-29 01:52:09 -08:00
Virus.V
2b8e0945a9 Fix BL602 CI Build failed.
Modify the default configuration in KConfig.
Sync latest commit from mainline.

Remove unused demo configuration

fixup bl602 nsh defconfig cause CICD failed

Rebase from mainline code
2020-12-29 01:52:09 -08:00
Virus.V
7e84874cb1 Reconstruct bl602 readme; move up_irq_save/restore declaration to common place 2020-12-29 01:52:09 -08:00
Virus.V
ce40edbd11 Solve the problems pointed out in the comments 2020-12-29 01:52:09 -08:00
Virus.V
417d0d4ccd fix checkpatch warning 2020-12-29 01:52:09 -08:00
Lei Chen
58bd873729 Add Basic support for BL602(UART timer CLIC) 2020-12-29 01:52:09 -08:00
liang
b074ebec9e fix redefined CSR_INSTRET 2020-12-23 01:34:14 -06:00
Masayuki Ishikawa
ec73a4e69c arch & sched: task: Fix up_exit() and nxtask_exit() for SMP
Summary:
- During repeating ostest with sabre-6quad:smp (QEMU),
  I noticed that pthread_rwlock_test sometimes stops
- Finally, I found that nxtask_exit() released a critical
  section too early before context switching which resulted in
  selecting inappropriate TCB
- This commit fixes this issue by moving nxsched_resume_scheduler()
  from nxtask_exit() to up_exit() and also removing
  spin_setbit() and spin_clrbit() from nxtask_exit()
  because the caller holds a critical section
- To be consistent with non-SMP cases, the above changes
  were done for all CPU architectures

Impact:
- This commit affects all CPU architectures regardless of SMP

Testing:
- Tested with ostest with the following configs
- sabre-6quad:smp (QEMU, dev board), sabre-6quad:nsh (QEMU)
- spresense:wifi_smp
- sim:smp, sim:ostest
- maix-bit:smp (QEMU)
- esp32-devkitc:smp (QEMU)
- lc823450-xgevk:rndis

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-12-21 23:29:56 -06:00
Xiang Xiao
92cefb0a78 arch/risc-v: Move CSR register bit definition to csr.h
to avoid the macro duplication

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-12-20 20:27:13 -08:00