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39183d37b8
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3818 Commits

Author SHA1 Message Date
Gregory Nutt
39183d37b8 Change all time conversions. Yech. New timer units in microseconds breaks all existing logic that used milliseconds in the conversions. Something likely got broken doing this, probably because I confused a MSEC2TICK conversion with a TICK2MSEC conversion. Also, the tickless OS no appears fully functional and passes the OS test on the simulator with no errors 2014-08-07 18:00:38 -06:00
Gregory Nutt
8b2a8fceba Change CONFIG_MSEC_PER_TICK to CONFIG_USEC_PER_TICK. This gives more options for system timers in general, but more importantly, let's us realize higher resolution for the case of CONFIG_SCHED_TICKLESS=y -- of course, at the risk of some new interger overvflow problems 2014-08-07 13:42:47 -06:00
Gregory Nutt
f140e112e0 Implements the tickless OS 2014-08-07 11:39:16 -06:00
Gregory Nutt
c275ebef35 Add support for a simulated interval timer support verification of the tickless OS. 2014-08-06 18:29:29 -06:00
Gregory Nutt
595ec296fb Don't build in sched_processtimer.c if CONFIG_SCHED_TICKLESS is selected. 2014-08-06 18:27:10 -06:00
Gregory Nutt
94afad9b70 if CONFIG_SCHED_TICKLESS is defined, then the global variable g_system_timer does not exist 2014-08-06 18:26:16 -06:00
Gregory Nutt
594083d870 Rename up_timerinit() to up_timer_initailize(); Add prototypes for candidate interfaces for the tickless OS; Don't build existing timer initialization logic if CONFIG_SCHED_TICKLESS is defined. 2014-08-06 16:26:01 -06:00
Gregory Nutt
d4a29fcf7e SAMA5D3 HSMCI: TX DMA is again disabled 2014-08-05 07:07:39 -06:00
Gregory Nutt
553a16fac5 SAMA5 PCK: Add Main clock as an option for the PCK clock source 2014-08-03 10:17:50 -06:00
Gregory Nutt
1fc8f2b06d SAMA5 SSC: Verify that the requested bit width is supported. Correct some alignment tests that depend upon the data bit width. 2014-08-02 14:26:49 -06:00
Gregory Nutt
715cf207ea SAMA5 WM8904: Fix errors in programmable clock output configuration 2014-08-01 15:18:58 -06:00
Gregory Nutt
5e92347d60 SAMA5 SSC: Start Delay is now configurable 2014-08-01 14:10:37 -06:00
Gregory Nutt
d68a6059e0 SAMA5 SSC: Frame Synch Delay is now configurable 2014-08-01 12:25:31 -06:00
Gregory Nutt
c2c2921901 SAMA5D SSC: Needs to account for data offset in audio buffer. 2014-07-31 19:14:24 -06:00
Gregory Nutt
513329fd24 SAMA5D3X-EK: Add support for the WM8904 audio CODEC 2014-07-31 11:14:57 -06:00
Gregory Nutt
ffcc0b8da3 SAMA5: Changes needed for a clean SAMA5D3 build after all of the recent SAMA5D4 changes. 2014-07-31 11:09:56 -06:00
Gregory Nutt
c0c4cda763 SAMA5 HSMCI: e-enable TX DMA and verify that DMA writes to the SD card are functional. They are so now TX DMA is re-enabled in the driver. This might affect the SAMA5D3 platforms where the TX DMA problem was found. The SAMA4D3 and 4 use the same HSMCI driver. Much has change since then and it is not surprising that DMA is now functional. However, the has not be re-verified on the SAMA5D3 which has a different DMA controller. 2014-07-30 11:20:06 -06:00
Gregory Nutt
611ea42dbf SAMA5D HSMCI: Fix a problem on card insertion/removal callback handling. Interrupts were being disable so that the callbacks occurred with interrupts disabled. This resulted in loss of some interrupts and some not-so-good behaviors. The solution is to perform all callbacks on the work thread unconditionally (2014-7-29). 2014-07-30 10:19:41 -06:00
Gregory Nutt
059812c872 SAMA5D HSMCI: Add method to do RX transfer without DMA. The 8-byte SCR transfer was failing silently with the DMA transfer, leaving the SD card in single bit mode 2014-07-29 21:13:28 -06:00
Gregory Nutt
8bbbc5b255 Cosmetic changes to comments 2014-07-29 07:17:01 -06:00
Gregory Nutt
e053158f95 SAMA5D-EK: Correct system timer frequency. Input clock is MCK/2, not MCK 2014-07-29 07:12:36 -06:00
Gregory Nutt
29ea8ab0e4 Cosmetic changes to comments 2014-07-29 07:11:16 -06:00
Gregory Nutt
42a975af74 Fixes to last SAMA5 PMIC checkin 2014-07-28 17:09:37 -06:00
Gregory Nutt
99927e918d LPC17xx: DC updates from Max. Also fixes some syntax errors that I introduced in the last commit. 2014-07-28 07:23:49 -06:00
Gregory Nutt
dd4be66f1c ARM: Move L2 cache initialization to much later in the sequence 2014-07-27 10:03:33 -06:00
Gregory Nutt
b57d2182ab ARMv7-A L2 Cache currently depends on EXPERIMENTAL because it does not yet work properly 2014-07-26 18:48:54 -06:00
Gregory Nutt
6f5280d284 ARMv7 L2 Cache: Minor bugfixes/improvements 2014-07-26 18:48:26 -06:00
Gregory Nutt
ee59870325 Enables cache early in boot-up sequence 2014-07-26 18:48:00 -06:00
Gregory Nutt
4e146d2ec2 Change naming from cp_XYZ_cache() to arch_XYP_cache() so that all cache operations will pick up L2 support if it is enabled 2014-07-26 18:47:33 -06:00
Gregory Nutt
873788bf5a New cache.h file. Renames cp15_XYZ_cache() to arch_XYZ_cache() and addes L2 cache support if L2 cache is enabled 2014-07-26 18:46:52 -06:00
Gregory Nutt
2eb526253b Rename ARMv7-A cache.h to cp15_cache.h. Things will be broken on this commit until I get the new cache.h in place. 2014-07-26 16:54:19 -06:00
Gregory Nutt
6d9ca195ee arch/arm/src/armv7-a/arm_l2cc_pl310.c, l2cc.h, l2cc_pl310.h, Kconfig: Add initiali support for the ARM L2CC-PL310 L2 cache. 2014-07-26 16:50:08 -06:00
Gregory Nutt
fcbf89c6f6 ARMv7-A: L2CC PL310 address filtering is an optional feature 2014-07-25 19:46:09 -06:00
Gregory Nutt
a007fa3f5e ARMv7-A: Add missing L2CC PL310 bit definitions 2014-07-25 19:41:35 -06:00
Gregory Nutt
e74f37445b rch/arm/armv7-a/l2cc_pl310.h: Move arch/arm/sama5/chip/sam_l2cc.h to arch/arm/armv7-a/l2cc_pl310.h. Adjust the two corresponding Kconfig files as well. 2014-07-25 17:25:17 -06:00
Gregory Nutt
2ec0ab3b5e 3rd time is a charm. Max is right, the initial priority setting should be NVIC_SYSH_PRIORITY_MIN 2014-07-24 16:51:07 -06:00
Gregory Nutt
1366ce0a02 Oops, should have been NVIC_SYSH_PRIORITY_DEFAULT 2014-07-24 16:42:15 -06:00
Gregory Nutt
a3d20b2fa1 LPC17 Ethernet: Added option to use the kernel worker thread to do most of the workload with CONFIG_NET_WORKER_THREAD option in Kconfig. Eliminated a problem with PHY DP83848C : it doesn't need a specific initialization on mbed. Critical bufix: From time to time (after some hours) the Ethernet receiver would lose one receive interrupt and the IP stack never recover because there is no receive watchdog as the transmit watchdog. From Max 2014-07-24 16:39:18 -06:00
Gregory Nutt
dd74e75d1e Added burstmode ADC conversion mode, with CONFIG_ADC_BURSTMODE option in Kconfig. From Max 2014-07-24 16:23:31 -06:00
Gregory Nutt
21d67c5b1b Mostly cosmetic changes from Max 2014-07-24 16:00:21 -06:00
Gregory Nutt
43a578d2d3 Eliminate warnings. From Max 2014-07-24 15:50:37 -06:00
Gregory Nutt
5e19807250 Correct the initial value of the BASEPRI register. This was apparently never being initialized. From Max 2014-07-24 15:37:13 -06:00
Gregory Nutt
949e002d76 Fix a recently introduced typo that was being masked by some bad conditional compilation 2014-07-22 11:45:14 -06:00
Gregory Nutt
d57c3b4e82 Update ChangeLog 2014-07-22 07:25:01 -06:00
Gregory Nutt
45c03e5a1a STM32 OTGFS device: Various changes to try to reduce that amount of time in interrupts handles and with interrupts disbled. Needs verification on other platforms. From Petteri Aimonen 2014-07-22 07:23:17 -06:00
Gregory Nutt
615b7d6c7a Fix typos in the STM32 DAC header file. From Petteri Aimonen 2014-07-22 07:13:33 -06:00
Gregory Nutt
af8f5f4bdc SAMA5D4 XDMAC: Never sets a channel as secure. Will probably have to revisit this 2014-07-21 17:46:35 -06:00
Gregory Nutt
4ce2e094ba SAMA5D4: Fix some HSMCI issues when XDMAC0 is enabled 2014-07-21 17:45:48 -06:00
Gregory Nutt
80c0b5628d SAMA5 HSMCI: Correct multi-block DMA setup; Fixes related to DMA timeout. Still problems with HSMCI DMA via XDMAC 2014-07-21 16:49:56 -06:00
Gregory Nutt
519c8f3e97 SAMA5 XDMAC: Missing some CUBC bits 2014-07-21 16:47:16 -06:00