In some special chipsets, multiple CPUs may be bundled in one hardware
thread cluster, which results in hartid and cpuindex not being exactly
the same. The new option will decouple Scratch-based Per-CPU storage
with S-Mode to distinguish the real cpu index.
Signed-off-by: chao an <anchao@lixiang.com>
RISC-V provided fetch-and-op style atomic primitives as they scale
to highly parallel systems better than LR/SC or CAS. A simple
microarchitecture can implement AMOs using the LR/SC primitives,
provided the implementation can guarantee the AMO eventually
completes. More complex implementations might also implement AMOs
at memory controllers, and can optimize away fetching the original
value when the destination is x0.
Signed-off-by: chao an <anchao@lixiang.com>
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Most of the functions used to describe the SoCs capabilities are
available for all Espressif's chips. This commit uses this set of
common functions and remove outdated functions that perform the
same operations in a chip level.
1. pm configuration demonstrates the use of power management present on the ESP32-S3.
2. You can use the pmconfig command to test the power management, for details look at
``Documentation/platforms/xtensa/esp32s3/boards/esp32s3-devkit/index.rst``
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
acpi_init() must be called early during boot, some system components may be
unavailable at this stage, so debug messages won't work
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
This driver supports both eDMA3 and eDMA4 (also referred to as DMA0 / DMA1
in some contexts..)
The IP blocks are almost identical, with sufficiently minor differences
to use them via a unified driver. The price is a great amount of code
obfuscation in the hardware description layer.
This fixes names of program entry and linker script files so that to
support building kernel mode apps using CMake and export package.
flat and protected mode should be the same as before.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
rsdp memory may be not mapped when provided from multiboot2 header.
For some reason the previous code worked on some machines.
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
add simple ACPI parser for intel64.
For now RSDP signature can be found in BIOS legacy region or can be provided by multiboot2
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
In file included from common/addrenv.h:33,
from common/riscv_initialstate.c:36:
common/riscv_initialstate.c: In function 'up_initial_state':
common/riscv_internal.h:136:16: warning: declaration of 'regval' shadows a previous local [-Wshadow]
136 | uintptr_t regval; \
| ^~~~~~
common/riscv_initialstate.c:74:12: note: in expansion of macro 'READ_CSR'
74 | regval = READ_CSR(CSR_VLENB);
| ^~~~~~~~
common/riscv_initialstate.c:63:13: note: shadowed declaration is here
63 | uintptr_t regval;
| ^~~~~~
Signed-off-by: chao an <anchao@lixiang.com>
LLVM supports (to various degrees) a number of experimental extensions.
All experimental extensions have experimental- as a prefix. There is
explicitly no compatibility promised between versions of the toolchain,
and regular users are strongly advised not to make use of experimental
extensions before they reach ratification.
Fix compile error:
riscv64-unknown-elf-clang: error: invalid arch name 'rv64gcv_zfh_zvfh', requires '-menable-experimental-extensions' for experimental extension 'zvfh'
Signed-off-by: chao an <anchao@lixiang.com>
- Add ARCH_KVMA_MAPPING to guard kernel mapping.
- Set dependency from MM_KMAP to ARCH_KVMA_MAPPING, as per commit
70de321de3.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
icr is tested below with macros like GPIO_INT_LOWLEVEL et al. Those macros
are shifted left by GPIO_INTCFG_SHIFT, so the temporary icr variable
should not be shifted right.
The SAMV7's qencoder driver now supports the GETINDEX ioctl call
which does not reset the internal Timer/Counter and returns
the current position, position of the last index and the number
of captured indexes to a struct qe_index_s pointer. Because the
SAMV7's timers are 16bit, the extension to 32 bits must be done.
Select CONFIG_SAMV7_QENCODER_ENABLE_GETINDEX in the Kconfig to
enable this functionality.
This driver does not obey the instructions given in the ATSAMV7
2023 datasheet because the recommended trigger resets the internal
counter which is not desired. Instead, a capture into capture A
and capture B registers is used. This way if an event happens
(the rising edge of the index signal), the current counter's value
is captured.
Signed-off-by: Stepan Pressl <pressste@fel.cvut.cz>
The Simple Boot feature for Espressif chips is a method of booting
that doesn't depend on a 2nd stage bootloader. Its not the
intention to replace a 2nd stage bootloader such as MCUboot and
ESP-IDF bootloader, but to have a minimal and straight-forward way
of booting, and also simplify the building.
This commit also removes deprecated code and makes this bootloader
configuration as default for esp32s3 targets and removes the need
for running 'make bootloader' command for it.
Other related fix, but not directly to Simple Boot:
- Instrumentation is required to run from IRAM to support it during
initialization. `is_eco0` function also needs to run from IRAM.
- `rtc.data` section placement was fixed.
- Provide arch-defined interfaces for efuses, in order to decouple
board config level from arch-defined values.
Signed-off-by: Almir Okato <almir.okato@espressif.com>
Currently Simple Boot image have fixed 2 ROM segments and
2 RAM segments, then the parsing iterator must stop when all
ROM segments are found.
Signed-off-by: Almir Okato <almir.okato@espressif.com>
- Add missing include guard
- Add missing C++ guard
- Fix the initialization ordering in IOMUX_PADCFG macro. Why ? Becaused of:
imx9_iomuxc.h:54:3: error: designator order for field 'iomux_padcfg_s::dsyreg' does not match declaration order in 'iomux_padcfg_s'
54 | }
|
The original assumption was that the interrupt numbers are divided
so that 16 pins from 1 port are handled by a single interrupt source.
So source 0 would handle pins 0-15 and source 1 would handle pins 16-31.
This assumption is wrong, each pin has two sources, thus there are two
interrupt lines for each pin.
The driver uses source 0, and leaves source 1 disabled.
According to the qemu source code, hw/arm/virt.c.
The secure memory of the ARM Virt board is [0xe000000~0xf000000]
and the non-secure memory is configured as [0x40000000~0xffffffff].
We made the following adjustments based on the above virt board configuration
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Using CSR name depends on compiler support heavily, but CSR
encoding does not have this problem. It also make it easy to
add new CSR support even if the compiler does not support.
Unify CSR access by using the CSR encoding macro.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
This patch adds more debug related CSR definitions
to arch/risc-v/include/csr.h.
These definitions are from the RISC-V Debug Specification
Version 1.0 rc1 (https://github.com/riscv/riscv-debug-spec).
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Extracting global variable information using scripts:
kasan_global.py:
1. Extract the global variable information provided by the -- param asan globals=1 option
2. Generate shadow regions for global variable out of bounds detection
Makefile:
1. Implement multiple links, embed the shadow area into the program, and call it by the Kasan module
Signed-off-by: W-M-R <mike_0528@163.com>
RTC data was not being correctly placed on RTC's memory data due to
linker issues. Also, the image's RTC memory segment was not being
properly parsed by the bootloader.
This is a high resolution PWM driver, utilizing one 16-bit Flex-IO timer for
generating PWM period and the rest of the timers to generate PWM duty cycles.
This means that the period has to be the same for every PWM generated from one
FLEXIO block, but this way we can get 16-bit resolution for the PWM signals.
For a typical IMX9 HW there are 8 timers for each Flex-IO block, which means
that by using this driver one can get 7 PWM outputs from one block.
This driver can be later extended to have configuration options to use all
8 channels per flex-io by either using 8+8 -bit timer (less resolution) or by
using an external trigger from an LPIT.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This commit implements the common RMT driver (already available for
the other Espressif's xtensa-based devices) for ESP32.
This allows us to have a proper separation between the lower and
upper-half drivers and use the 'ws2812' example to drive WS2812 RGB
LEDs.
1.
In file included from chip/stm32_rtc.c:31:
chip/stm32_rtc.c: In function 'rtchw_set_alrmar':
chip/stm32_rtc.c:761:11: warning: format '%x' expects argument of type 'unsigned int',
but argument 3 has type 'uint32_t' {aka 'volatile long unsigned int'} [-Wformat=]
761 | rtcinfo(" ALRMAR: %08x\n", getreg32(STM32_RTC_ALRMAR));
| ^~~~~~~~~~~~~~~~~~
chip/stm32_rtc.c:761:25: note: format string is defined here
761 | rtcinfo(" ALRMAR: %08x\n", getreg32(STM32_RTC_ALRMAR));
| ~~~^
| |
| unsigned int
| %08lx
2.
arm-none-eabi-ld: staging/libdrivers.a(userled_lower.o): in function `userled_setled':
drivers/leds/userled_lower.c💯 undefined reference to `board_userled'
Regression:
stm32h7/linum-stm32h753bi: add support to leds
Signed-off-by: chao an <anchao@lixiang.com>
This commit just rearranges the order of the types, data and
functions without modifying them. This is done to make it look more
similar with ESP32's ble adapter and ease maintanence.
Most of the functions used to set the peripherals are available for
all Espressif's chips. This commit uses this set of functions and
remove outdated functions that perform the same operations in a
chip level.
This commit updates the Wi-Fi and the BLE driver of ESP32. Most of
the changes rely on using the common sources and header files for
xtensa-based Espressif's SoCs.
The new Wi-Fi driver supports WPA3-SAE for both Station and SoftAP
mode. BLE's coexistence mode was enhanced according to the latest
libraries.
Please note that other sources required minor changes in order to
be compatible with the common sources.
Whenever a SPI flash operation will take place, it's necessary to
disable the cache and run no code from the flash. This includes
pausing the other CPU (when `CONFIG_SMP=y`). This commit prevents
an error to occur when the CPU core is evaluated before the task
is increased to the max priority.
Whenever a SPI flash operation will take place, it's necessary to
disable the cache and run no code from the flash. This includes
pausing the other CPU (when `CONFIG_SMP=y`). This commit prevents
an error to occur when the CPU core is evaluated before the task
is increased to the max priority.
adjust link options for userspace elf
specify system libs and apps lib to only link with nuttx target in flat build mode
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
Avoid using static mutex and recursive mutex as the resource to be
acquired/release. Instead, create a specific lock for each call if
it does not exist.
Avoid using static mutex and recursive mutex as the resource to be
acquired/release. Instead, create a specific lock for each call if
it does not exist.
Avoid using static mutex and recursive mutex as the resource to be
acquired/release. Instead, create a specific lock for each call if
it does not exist.
As __start must be placed at a precise location, a separate, explicit
input section is needed to guarantee this.
Why is this an issue ? NuttX uses --entry=__start which puts __start in
its correct location, but out-of-tree builds won't work, so it more robust
to use an explicit section for the startup code and enforce its placement
in the linker script.
This fixes build error (Werror):
Error: chip/stm32_foc.c:1918:12: error: 'stm32_foc_info_get' defined but not used [-Werror=unused-function]
1918 | static int stm32_foc_info_get(struct foc_dev_s *dev, struct foc_info_s *info)
| ^~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
If a context switch occurs in syscall, the g_running_task need to be recorded for assert logic.
This copies the logic from arm platforms
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
When entering the function from an external bootloader, the CPU could be using PSP. But the following
code expects MSP to be in use.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
We shouldn't panic the kernel when a user task excepts, we can just kill the user task and
it's children. Do this by returning to _exit() in kernel context.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Adds support for NXP i.MX9-series System-on-Module chips.
- Support for i.MX93 is added
- CPU is Cortex A55 / ARMv8.2A
- The chip also contains a Cortex M33, but no support is provided
- Supported drivers include lpuart only for now
We can decide whether use trustzone
After this patch, we can support the following mode:
ARCH_HAVE_TRUSTZONE ARCH_TRUSTZONE_DISABLED ARCH_TRUSTZONE_SECURE ARCH_TRUSTZONE_NONSECURE
Without Security Extensions n n n n
CHIP have NO trustzone
With Security Extensions y y n n
Only one bin in sec mode
With Security Extensions y n y n
TEE bin in sec mode
With Security Extensions y n n y
REE bin in non-sec mode
Signed-off-by: ligd <liguiding1@xiaomi.com>
Purpose: make the the os crash when busyloop with interrupt disable
Follow the arm gicv2 spec, if we want to use the IRQ and FIQ
simultaneously when not using the processor Security Externsions.
We should:
1. IRQ to Group 1 and FIQ to Group 0;
2. Set CICC_CTLR.FIQEn to 1;
Then in NuttX:
1. implement the arm_decodefiq and directly crash in it;
2. provide interface to change the IRQ to FIQ, e.g. change the
watchdog IRQ to FIQ, so the watchdog can trigger even with the
interrupt disabled (up_irq_save() called);
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
Currently only FLAT mode development can enjoy cmake build system. This
patch tries to add initial kernel mode support. It can build NuttX kernel
and libproxies.a, the latter will be further checked though.
This can already help to build an AMP remote node image as it can share
userland apps living in the AMP master node.
Major changes:
- in top folder:
- CMakeLists.txt adjust for KERNEL mode, separate from PROTECTED mode.
- in `syscall`:
- CMakeLists.txt add mksyscall target for stubs/proxies generation
- in `syscall/stubs`:
- CMakeLists.txt use dependency to mksyscall
- in `syscall/proxies`:
- CMakeLists.txt use dependency to mksyscall
- in `arch`:
- CMakeLists.txt separate KERNEL from PROTECTED mode.
- in `arch/risc-v/src`:
- CMakeLists.txt separate from PROTECTED mode, add sub folders.
- in `arch/risc-v/common`:
- CMakeLists.txt add sources and sub-folders for KERNEL mode.
- in `arch/risc-v/k230`:
- CMakeLists.txt add sources for KERNEL mode.
- in `boards/risc-v/k230/canmv230/src`:
- CMakeLists.txt adjust k230 specific scripts for kernel mode.
New additions:
- in `arch/risc-v/src/nuttsbi/` add CMakeLists.txt
- in `arch/risc-v/src/common/supervisor/` add CMakeLists.txt
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This patch fixes the issue that k230_hart_is_big() doesn't work in
S-mode. It also adds convenient debug macros to ease debugging process
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Some stm32 has alternate USART6 pinout on G9/G14 but others have it
on A12/A11. Unfortunately it's very difficult to make proper ifdefs for
this since position is based on package (and pincount) and not chip
itself. Creating such list would take a lot of time. Because of that
I just added another possible config for this pin and moved responsibility
of proper selection onto board code.
Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
Onewire driver wants to use "struct up_dev_s *priv", which is extracted
from "struct uart_dev_s" and "struct inode". But inode and uart dev are
only declared when TERMIOS or BSDCOMPAT is also enabled. Without these
driver fails to compile with missing declaration errors. Adding some
additional "#if defined()" to these declarations fix the issue and driver
compiles and works properly (tested with ds18b20 temp sensor).
Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
This driver is used with QEMU, to make it possible
to use networking.
This is not the MAC in ESP32, however, it can be used with QEMU.
The code was shamelessly copied from 31dac92e5f
This patch simplifies PMP handling for K230 using common APIs.
It also uses `g_misa` variable to expose the MISA issue.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
check if interrupt is busy when IRQCHAIN is disabled
this allows user to catch configuration errors and fail early when the
already busy vector is reused
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
at default x86_64 supports SSE, SSE2, this commit adds support for
SSE3, SSSE3, SSE41, SSE42 and SSE4A
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
