Replace risky DEBUGASSERT()s with real sanity checks. Also,
do a few more checks as the system might occasionally fire an
interrupt if the system has been restarted while in middle of
an i2c transaction.
Yet, modify i2c_transfer() function so that up_disable_irq()
is always called at the end to better prevent ill-timed irqs.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
priv->msgid may grow past its boundaries, causing
struct i2c_msg_s *msg = &priv->msgv[priv->msgid]
to read data out of boundaris.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Current mmu_flush_cache() hook lacks the reg param which needed by
some targets. So this PR adds the param and update existing targets
using that hook.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Weak function sometimes can't have strong implementation linked.
This patch uses NUTTSBI_LATE_INIT config and normal function instead
to avoid those issues.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Previously NuttX runs on little core of K230, this patch allows NuttX to
run on the big core as well.
Within folder `arch/risc-v/src/k230`:
- Changes:
- CMakeLists.txt add k230_hart.c to sources list
- Make.defs add k230_hart.c to sources list
- chip.h add inclusion to k230_hart.h etc
- k230_irq.c move sbi_late_init() to k230_hart.c
- k230_start.c add support to run on big core
- hardware/:
- k230_memorymap.h add T-Head C908 specific CSR
- Additions:
- k230_hart.c sbi_late_init w/ hart initialization
- k230_hart.h header file
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
add defintions for vector extension and additional user-mode
extension fields for MSTATUS and SSTATUS registers.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Adding CMakeLists.txt files to support CMake build system.
Note that only FLAT build works now due to limitations of current
CMake build system.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
After warm reset the interrupt source in the HW block is not explicitly
cleared, thus once the interrupt source is enabled the old / stale interrupt
fires immediately.
This causes a DEBUGASSERT() failure on line 808 mpfs_spi_unload_rx_fifo:
DEBUGASSERT(nwords > 0);
This commit fixes building native MCUboot from sources by getting
the required sources from `esp-hal-3rdparty` repository and enable
building MCUboot and using it as the 2nd stage bootlaoder.
- A pre-built IDF bootloader is used by default;
- `ESP32C3_PARTITION_TABLE` requires the IDF bootloader to be built
from sources.
- Native MCUboot also can be used to boot the device. It will be
built from sources and depends on !ESP32C3_PARTITION_TABLE.
Simple boot is a method of booting that doesn't depend on a 2nd
stage bootloader. Please note that some of the ESP-IDF bootloader
features are not available using simple boot, such as partition
tables and OTA: most of these features are implemented in NuttX
and MCUboot.
The Simple Boot feature for Espressif chips is a method of booting
that doesn't depend on a 2nd stage bootloader. Its not the
intention to replace a 2nd stage bootloader such as MCUboot and
ESP-IDF bootloader, but to have a minimal and straight-forward way
of booting, and also simplify the building.
This commit also makes this bootloader configuration as default
for esp32c3-generic target and removes the need for running
'make bootloader' command for it.
Signed-off-by: Almir Okato <almir.okato@espressif.com>
Ox64 BL808 crashes with a Page Fault when we run `getprime` then `hello`. This is caused by the T-Head C906 MMU incorrectly accessing the MMU Page Tables of the Previous Process (`getprime`) while starting the New Process (`hello`).
To fix the problem, this PR flushes the MMU Cache whenever we point the MMU SATP Register to the New Page Tables. We execute 2 RISC-V Instructions that are specific to T-Head C906:
- DCACHE.IALL: Invalidate all Page Table Entries in the D-Cache
- SYNC.S: Ensure that all Cache Operations are completed
This is derived from the T-Head Errata for Linux Kernel. More details here: https://lupyuen.github.io/articles/mmu#appendix-flush-the-mmu-cache-for-t-head-c906
Modified Files:
- `arch/risc-v/src/common/riscv_mmu.h`: If needed, `mmu_write_satp()` calls `mmu_flush_cache()` (weak function) to flush the MMU Cache. (Like for T-Head C906)
- `arch/risc-v/src/bl808/bl808_mm_init.c`: Flush the MMU Cache for T-Head C906. Extend `mmuflags` from 32-bit to 64-bit to be consistent with `mmu_ln_setentry()`.
- `boards/risc-v/bl808/ox64/configs/nsh/defconfig`: Enable `ostest` in the Build Config. Update `CONFIG_BOARD_LOOPSPERMSEC` according to `calib_udelay`.
Ubuntu stock toolchain `gcc-riscv64-unknown-elf` complains about
current CMake system (see issue#11573). This tries to fix it so
that both newer XPack and stock toolchains can be used with CMake.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
To avoid build break:
ld: riscv-none-elf/lib/rv64imafdc_zicsr/lp64d/crt0.o: in function `.L0 ':
(.text+0x8): undefined reference to `__bss_start'
ld: (.text+0x10): undefined reference to `_end'
ld: (.text+0x36): undefined reference to `main'
collect2: error: ld returned 1 exit status
Signed-off-by: chao an <anchao@lixiang.com>
Newly added logging in `sched/task_exit.c` obsoletes the existing
ones in `arch/up_exit()`, thus remove the latter to reduce duplications.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Previously k230 kernel build needs OpenSBI wrapping for use on
target, thus leading to larger program and memory overheads.
This patch adds alternative small overhead kernel build support.
Changes:
- in arch/risc-v/src/k230:
- k230_head.S entrance renamed for sake of NUTTSBI
- k230_irq.c add M-mode handling for NUTTSBI case
- k230_mm_init.c add L3 table for smaller RAM case
- hardware/k230_plic.h add PLIC_CTRL definition
- Make.defs use CHIP_ASRCS to fix entrance selection
- in boards/risc-v/canmv230/scripts:
- Make.defs add support for NUTTSBI case
Additions:
- in boards/riscv/canmv230/:
- scripts/ld-nuttsbi.script link script for NUTTSBI case
- configs/nsbi/defconfig config for NUTTSBI case
The artifact nuttx.bin from this configuration can be used directly
on target as OpenSBI wrapping is not needed.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
fix typo
Some devices have special preparations before entering S-mode, thus
a hook is needed from NUTTSBI to give them the chance.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Chips like K230 has ARCH_RV64 but only supports 32-bit MMIO. So using
ARCH_RV_MMIO_BITS is more proper here.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This is not the right place to modify DMA memory protection values.
Why not? These are designed to protect other AMP mode instances. Opening
the entire SoC's memory for the USB DMA kind of defeats this purpose.
Also, the driver cannot know how to configure these registers correctly,
only opening up the whole SoC "works".
Fully linked apps take less storage and are efficient to load. This
is to enable them for rv-vrit configurations in KERNEL build.
Changes:
- arch/risc-v/Kconfig select BINFMT_ELF_EXECUTABLE for QEMU-RV
- boards/risc-v/qemu-rv/rv-virt/configs
- knsh32/defconfig enable ELF_EXECUTABLE, LIBM, OSTEST
- knsh64/defconfig enable ELF_EXECUTABLE, LIBM, OSTEST
- ksmp64/defconfig enable ELF_EXECUTABLE, LIBM, OSTEST
- knetnsh64/defconfig enable ELF_EXECUTABLE, LIBM, OSTEST
- knetnsh64_smp/defconfig enable ELF_EXECUTABLE, LIBM, OSTEST
Additions:
- boards/risc-v/qemu-rv/rv-virt/scripts/
- gnu-elf.ld apps linker script
The ARCH_TEXT_VBASE of knsh32 is set to same as that of 64bit to reuse
the apps linker script.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Previously apps in kernel build are partially linked, thus are
big and inefficient. This enables full link for kernel mode apps
to reduce size and speed up loading.
Changes:
- arch/risc-v/Kconfig select HAVE_ELF_EXECUTABLE for K230
- boards/../scripts/Make.defs adjust LDELFLAGS
- boards/../knsh/defconfig enable BINFMT_ELF_EXECUTABLE
Additions:
- boards/../scripts/gnu-elf.ld apps linker script
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Current LITEX_LAST_IRQ looks like a typo that blocks compilation of
`arty_a7/knsh` configuration.
This fixes the build but I have no such device for test.
Found it was LITEX_IRQ_LAST before commit #ee84ea3 so likely typo was
introduced by then.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
The implementation of the RISC-V Timer for BL808 SoC is incomplete. This PR implements the BL808 RISC-V Timer by calling OpenSBI. The code is derived from NuttX for RISC-V QEMU.
The implementation of `up_timer_initialize` with OpenSBI is explained in this article: https://lupyuen.github.io/articles/nim#appendix-opensbi-timer-for-nuttx
Changes:
- Documentation/platforms/risc-v/k230 revised for both modes
- arch/risc-v/include/k230/irq.h add S-mode IRQs
- under arch/risc-v/src/k230 folder:
- Make.defs drop use of k230_exception_m.S
- hardware/k230_clint.h add S-mode defs, revised freq
- k230_head.S unified flat/kernel mode support
- k230_irq.c add S-mode support with debug dump
- k230_mm_init.c revised for K230 S-mode
- k230_start.c revised for flat/s-mode,
- arch/risc-v/src/k230/k230_timerisr.c unified flat/s-mode support.
- under boards/risc-v/k230/canmv230 folder:
- configs/nsh/defconfig fix RAM size
- include/board_memorymap.h cleanup for S-mode
- src/.gitignore ignore romfs_boot.c
- src/Makefile add romfs support
Renames:
- under boards/risc-v/k230/canmv230/src/ folder:
- canmv_init.c from k230_appinit.c making room for more k230 devices
Dropped:
- under arch/risc-v/src/k230/
- k230_exception_m.S as hybrid mode not ready yet.
New files in boards/riscv/k230/canmv230:
- configs/knsh/defconfig S-mode config
- scripts/ld-kernel.script S-mode linker script
- src/romfs.h User space ROMFS defs needed in S-mode
- src/romfs_stub.c Stub ROMFS image
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
The code is mainly derived from the NuttX qemu-rv/rv-virt codebase.
Major changes:
- boards/Kconfig: add new BOARD_K230_CANMV
- arch/risc-v/Kconfig: add new CHIP_K230 chip and ARCH_RV_MMIO_BITS
- arch/risc-v/src/common/riscv_mtimer.c: use ARCH_RV_MMIO_BITS to
select MMIO access width
New additions:
- arch/risc-v/include/k230/: k230 SoC definitions
- arch/risc-v/src/k230/: k230 SoC sources
- boards/risc-v/k230/canmv230/: CanMV-K230 board sources and configs
- Documentation/platforms/risc-v/k230/: simple doc
Note that only FLAT build works for canmv230 now.
This PR has changes in RiscV common layer thus may affect other RiscV ports
It changes the mtime/mtimecmp access control from using config ARCH_RV64 to
newly intorduced config ARCH_RV_MMIO_BITS.
Original design uses ARCH_RV64 to select 64bit MMIO in riscv_mtimer.c, this
can't cope with the situation with K230 --- it has ARCH_RV64 but only can do
32bit MMIO. So a new ARCH_RV_MMIO_BITS config has been introduced. Its value
depicts the MMIO width in bits. The MMIO_BITS defaults to 32/64 for RV32/
RV64 respectively. This allows the macro to replace current use of ARCH_RV64
in riscv_mtimer.c.
The new MMIO_BITS config is a derived one, and for RiscV chips with
equal CPU and MMIO widths there is no need to explicitly set it as the
default rule will do that. Only chips with different CPU and MMIO widths
need set it in Kconfig.
So by design this change should be safe but RiscV ports should be checked.
"ostest" verification has been done for:
- canmv230/nsh
- rv-vivt/nsh
- rv-virt/nsh64
configuration generation and manual check of derived RV_MMIO_BITS has been
done for:
- star64/nsh
- arty_a7/nsh
- bl602evb/nsh
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
The `xxx_ipv6multicast` function in each driver is not adapted to
multiple IPv6 addresses yet, and they're redundant, so try to take them
into common code.
Change:
1. Add MAC `g_ipv6_ethallnodes` and `g_ipv6_ethallrouters` in
`icmpv6_devinit` and call them in `netdev_register`
2. Add multicast MAC for Neighbor Solicitation when adding any IPv6
address, and remove them when IPv6 address is removed
3. Select `NET_MCASTGROUP` when `NET_ICMPv6` because now we need
`d_addmac` when we have ICMPv6
Note:
We want modules outside net stack to call functions like
`netdev_ipv6_add` and never touch the related MAC address, so these MAC
functions are added as internal functions to `net/netdev/netdev.h`
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
DMA directly to user (virtual) memory won't work, as the DMA engine(s)
don't do address translations, i.e. they require a physical address.
Using kernel heap is fine as it is mapped vaddr=paddr. Also, the USB DMA
engine does not have any alignment requirements.
The hack just opens the entire SoC memory unconditionally, which is not
a good idea.
Test features can be used ad-hoc, they don't need to be supported by the
build.
There is a problem with the current elf loader for risc-v: when a pair of
PCREL_HI20 / LO12 relocations are encountered, it is assumed that these
will follow each other immediately, as follows:
label:
auipc a0, %pcrel_hi(symbol) // R_RISCV_PCREL_HI20
load/store a0, %pcrel_lo(label)(a0) // R_RISCV_PCREL_LO12_I/S
With this assumption, the hi/lo relocations are both done when a hi20
relocation entry is encountered, first to the current instruction (addr)
and to the next instruction (addr + 4).
However, this assumption is wrong. There is nothing in the elf relocation
specification[1] that mandates this. Thus, the hi/lo relocation always
needs to first fixup the hi-part, and when the lo-part is encountered, it
needs to find the corresponding hi relocation entry, via the given "label".
This necessitates (re-)visiting the relocation entries for the current
section as well as looking for "label" in the symbol table.
The NuttX elf loader does not allow such operations to be done in the
machine specific part, so this patch fixes the relocation issue by
introducing an architecture specific cache for the hi20 relocation and
symbol table entries. When a lo12 relocation is encountered, the cache
can be consulted to find the hi20 part.
[1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc
The macro LOG2_CEIL is intended to be used in the pre-processor phase. If
used run-time it will generate a massive amount of extra code (~3.5K) which
is a problem, as the PMP configuration is quite often executed from a first
stage bootloader with a limited amount of code memory.
Code size differences pre- and post:
Memory region Used Size Region Size %age Used
envm: 112064 B 112384 B 99.72%
Memory region Used Size Region Size %age Used
envm: 108952 B 112384 B 96.95%
This PR adds support for the Bouffalo Lab BL808 SoC, based on T-Head C906 64-bit RISC-V Core. This will be used by the upcoming port of NuttX for PINE64 Ox64 SBC.
Most of the code was derived from NuttX for Star64 JH7110. The UART Driver was derived from BL602 NuttX. The source files are explained in the articles here: https://github.com/lupyuen/nuttx-ox64
`Kconfig`: Added ARCH_CHIP_BL808 for BL808 SoC
`include/bl808/chip.h`: BL808 Definitions
`include/bl808/irq.h`: External Interrupts
`src/bl808/chip.h`: Interrupt Stack Macro
`src/bl808/bl808_allocateheap.c`: Kernel Heap
`src/bl808/bl808_head.S`: Linux Header and Boot Code
`src/bl808/bl808_irq.c`: Configure Interrupts
`src/bl808/bl808_irq_dispatch.c`: Dispatch Interrupts
`src/bl808/bl808_memorymap.h`: Memory Map
`src/bl808/bl808_mm_init.c`, `bl808_mm_init.h`: Memory Mgmt
`src/bl808/bl808_pgalloc.c`: Page Allocator
`src/bl808/bl808_serial.c`, `bl808_serial.h`: UART Driver
`src/bl808/bl808_start.c`: Startup Code
`src/bl808/bl808_timerisr.c`: Timer Interrupt
`src/bl808/hardware/bl808_memorymap.h`: PLIC and UART Base Address
`src/bl808/hardware/bl808_plic.h`: PLIC Register Addresses
`src/bl808/hardware/bl808_uart.h`: UART Register Addresses
`src/bl808/Kconfig`: BL808 Config
`src/bl808/Make.defs`: Makefile
Currently RISC-V NuttX supports 32-bit MMU Flags inside a Page Table Entry. This PR extends the MMU Flags to 64-bit, to support T-Head C906 Core and the new RISC-V Svpbmt Extension.
T-Head C906 uses Bits 59 to 63 in a Leaf Page Table Entry to configure the Memory Type: Cacheable / Bufferable / Strongly-Ordered. For the upcoming port of NuttX to PINE64 Ox64 BL808 SBC, we need to set the Memory Type to Strongly-Ordered for I/O Memory, which requires 64-bit MMU Flags.
Details of C906 MMU: https://lupyuen.github.io/articles/plic3#t-head-errata
Newer RISC-V Cores will use the Svpbmt Extension to configure the Memory Type (Cacheable / Strongly-Ordered). Svpbmt uses Bits 61 to 62 in a Leaf Page Table Entry to define the Memory Type. This also requires 64-bit MMU Flags.
Details of Svpbmt: https://github.com/riscv/riscv-isa-manual/blob/main/src/supervisor.adoc#svpbmt
Add registration function instrumentation API,
which can achieve instrumentation of entering and
exiting functions through the compiler's functionality.
We can use CONFIG_ARCH_INSTRUMENT_ALL to add instrumentation for all
source, or add '-finstrument-functions' to CFLAGS for Part of the
source.
Notice:
1. use CONFIG_ARCH_INSTRUMENT_ALL must mark _start or entry noinstrument_function,
becuase bss not set.
2. Make sure your callbacks are not instrumented recursively.
use instrument_register to register entry function and exit function.
They will be called by the instrumented function
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
The divider should be rounded to the next full integer to ensure that
the resulting SPI frequency is <= target frequency, i.e. the SPI is
not overclocked.
After this, RISC-V fully supports the kmap interface.
Due to the current design limitations of having only a single L2 table
per process, the kernel kmap area cannot be mapped via any user page
directory, as they do not contain the page tables to address that range.
So a "kernel address environment" is added, which can do the mapping. The
mapping is reflected to every process as only the root page directory (L1)
is copied to users, which means every change to L2 / L3 tables will be
seen by every user.
Replace DEBUGASSERTs with sanity checks. DEBUGASSERT()s are
not necessarily enabled at all, thus risking the functionality
especially in that case. Remove PANICs as well.
Don't enable the ihc irq too early. If enabled, and the master
is already up, the irq is being issued so that the system gets
stuck or is severely slowed down. Master may be already up if
this NuttX hart only is rebooted, for example.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Version 1.3.1 is the latest tagged version as of November
the 21st, 2023. This patch prepares the required changes
to make v1.3.1 work.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Some APIs are implemented both in common code and CHIP-specific code,
and the link needs to be based on the implementation in CHIP, so move
NUTTX_CHIP_ABS_DIR before common src.
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
Connecting the static page tables to each other was done with the page
table virtual address (riscv_pgvaddr) when the page table physical address
is needed.
I can never remember whether the static page table list contains the
table's physical or kernel virtual address.. Add the fact as a comment
there.
Also add the limitations that come from this static page table approach
for Sv32.
This adds option to do PMP configuration via mpfs_board_pmp_setup instead
of just opening up everything. In this case, it is up to the specific
board to implement the PMP configuration in whichever way it sees fit.
Previously, GPIO interrupts were not correctly mapped to the peripheral base register responsible for the interrupt.
Change the IRQ number calculation so the interrupts work correctly on all GPIO peripheral bases.
For TOR: Any size and 4-byte aligned address is required
For NA4: Only size 4 and 4-byte aligned address is good
For NAPOT: Minimum size is 8 bytes, minimum base alignment is 8 bytes,
and size must be power-of-two aligned with base
This commit simplifies these checks and removes all the nonsense added
by a misunderstanding of how the MPFS / Polarfire SoC's PMP works.
These options are just wrong and a result of misunderstanding of the
Polarfire SoC spec. There are no feature limitations in the CPU PMP
implementation -> remove any configuration options added.
Fix case where NULL is de-referenced via tx/rx buffer or descriptor. Only
1 queue is currently set up for each, so the indices 1,2,3 are not valid
and should not be handled.
The BIT macro is widely used in NuttX,
and to achieve a unified strategy,
we have placed the implementation of the BIT macro
in bits.h to simplify code implementation.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
All kernel memory is mapped paddr=vaddr, so it is trivial to give mapping
for kernel memory. Only interesting region should be kernel RAM, so omit
kernel ROM and don't allow re-mapping it.
