In the previous implementation, PerformanceCounter would cause overflow
after running for a long time, This commit will separate the calculation
of the sec/ms part to avoid this issue, Reference:
https://github.com/cygwin/cygwin/blob/main/winsup/cygwin/clock.cc#L194-L217
Signed-off-by: chao an <anchao@xiaomi.com>
On a GICv2 implementation, setting GICC_CTLR.EOImode to 1 separates
the priority drop and interrupt deactivation operations.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Summary:
- Support arm64 pmu api, Currently only the cycle counter function is supported.
- Using ARM64 PMU hardware capability to implement perf interface, modify all
perf interface related code.
- Support for pmu init under smp.
Signed-off-by: wangming9 <wangming9@xiaomi.com>
Otherwise, a request will never be transferred and there is no
information to the user that something is wrong.
For example, when using default values for TXFIFO in HS mode,
USBMSC will never work because the maximum request len is 512B
which is lower than the default TXFIFO size for IN EP.
sim_x11events should process all x11 events in each event loop,
otherwise it will cause events to accumulate in the queue and affect the interaction.
Signed-off-by: pengyiqiang <pengyiqiang@xiaomi.com>
Summary:
- I noticed that 'sleep 1' on nsh took 10 seconds on QEMU-6.1,
though the old version (e.g. QEMU-5.2) works correctly.
- I think we should implement PLL for the QEMU environment.
However, this fix works as a tentative solution.
Impact:
- K210 on QEMU only
Tested
- Tested with QEMU-7.1
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This commit fixes#7857 and #7193 by saving Wi-Fi parameters and
set them at once, avoiding unknown behaviors of the Wi-Fi driver.
This commit also enables setting the auth of the STA/softAP modes
while connecting to/providing the wireless network.
RISCV has a modular instruction set. It's hard to define cpu-model to support all toolchain.
For Zig, cpu model is this formal: generic_rv[32|64][i][m][a][f][d][c]
For Rust, cpu model is this formal: riscv[32|64][i][m][a][f][d][c]
So, it's better to map the NuttX config to LLVM builtin cpu model, these models supported by
all LLVM based toolchain.
Refer to : https://github.com/llvm/llvm-project/blob/release/15.x/llvm/lib/Target/RISCV/RISCV.td
These models can't cover all implementation of RISCV, but it's enough for most cases.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This has been a long issue for me as it results in random crashes when
asynchronous events occur when the idle process is active.
The problem is that the kernel cannot access user memory, because the CPU
status prevents it.
Current Toolchain.defs set the compile flags directly, it's OK for
target specified gcc toolchain.
But some LLVM based toolchains (Rust/Zig etc) use single toolchain to handle all supported paltform.
In this patch, arch level Toolchain.defs export standard LLVM style arch flags, and let <Lang>.defs to map them into internal style,
This will simplify the intergration of non-c language.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
