The following errors are intentionally left.
(Hardware constants like DMA2D_xGPFCCR_CCM.)
arch/arm/src/stm32/stm32_dma2d.c:484:12: error: Mixed case identifier found
arch/arm/src/stm32/stm32_dma2d.c:692:13: error: Mixed case identifier found
arch/arm/src/stm32/stm32_dma2d.c:701:18: error: Mixed case identifier found
arch/arm/src/stm32/stm32_dma2d.c:706:18: error: Mixed case identifier found
arch/arm/src/stm32/stm32_dma2d.c:711:18: error: Mixed case identifier found
arch/arm/src/stm32/stm32_dma2d.c:725:14: error: Mixed case identifier found
arch/arm/src/stm32/stm32_dma2d.c:732:18: error: Mixed case identifier found
The following nxstyle errors are intentionally left.
They are "Lx" constants shared among multiple files.
arch/arm/src/stm32/stm32_ltdc.c:1774:10: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1775:10: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1779:11: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1780:11: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1784:11: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1785:11: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1804:10: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1805:10: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1806:10: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1845:16: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1849:17: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1903:11: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1903:34: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1907:12: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1907:35: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1987:16: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1991:17: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:2027:16: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:2031:17: error: Mixed case identifier found
arch/arm/src/stm32/stm32_oneshot.c:
arch/arm/src/stm32/stm32_oneshot.h:
arch/arm/src/stm32/stm32_oneshot_lowerhalf.c:
arch/arm/src/stm32/stm32_dbgmcu.h:
* Fix nxstyle errors.
arch/arm/src/stm32/stm32_lsi.c:
* Fix nxstyle errors.
* Also a minor grammar fix in a comment: add "in" to "setting the
LSION bit in the RCC CSR register."
stm32f7, stm32h7, stm32l4 and stm32f0l0g0 do it this way and there is no
reason for classic stm32 to differ. Also manipulation of priv->ie was not
atomic with respect to interrupts.
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
Summary:
- Apply the same logic added to cxd56_cpupause.c
Impact:
- SMP only
Testing:
- Tested with lc823450-xgevk:rndis
- Run smp and ostest
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same logic added to cxd56_cpupause.c
Impact:
- SMP only
Testing:
- Tested with sabre-6quad:smp (QEMU and dev board)
- Run smp and ostest
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I noticed that sched_add_readytorun() runs on multiple CPUs simultaneously
- Finally, I found the root cause which was described in TODO
- Actually, the task newly scheduled on remote CPU did not acquire g_cpu_irqlock
- This commit fixes this issue by adding a critical section to the pause handler
- Which will acquire g_cpu_irqlock on the remote CPU explicitly
Impact:
- SMP only
Testing:
- Tested with spresense:wifi_smp (NCPUS=2 and 4)
- Run smp, ostest, nxplayer
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I noticed that Cortex-A SGI can be masked
- We thought the SGI is not maskable
- Although I can not remember how I tested it before
- It actually works as expected now
- Also, fixed the number of remaining bugs in TODO
Impact:
- No impact
Testing:
- Tested with sabre-6quad:smp (QEMU and dev board)
- Add the following code in up_idle() before calling asm("WFI");
+ if (0 != up_cpu_index())
+ {
+ up_irq_save();
+ }
- Run the hello app, you can see "Hello, World!!"
- But nsh will freeze soon because arm_pause_handler is not called.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
It seems that part of the patch
stm32l4: correct build of stm32l4_can.c to respect L4 variant
has been lost on its way to mainline.
Signed-off-by: Pavel Pisa <ppisa@pikron.com>
Summary:
- Remove unnecessary d-cache operation to make boot fast
Impact:
- armv7-a SMP only
Testing:
- Tested with sabre-6quad:smp (QEMU and dev board)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit fixes armv7-a deadlocks with D-cache in SMP mode.
- In SMP mode, MMU for SDRAM area must be set to shareable
Impact:
- SMP only
Testing:
- Tested with sabre-6quad:smp (QEMU and dev board)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
arch/arm/src/stm32/hardware/stm32_dmamux.h,
arch/arm/src/stm32/hardware/stm32g47xxx_dmamux.h:
* New files, based on STM32G474RE reference manual, RM0440 Rev 4.
Used reference manual for STM32G071CB. The F0 and L0 families do not
appear to have a DMAMUX.
arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h:
* Remove all mentions of DMAMUX12 from comments. This family has
at most DMAMUX1 only.
* Add missing defines DMAMUX_CCR_SPOL_NONE,
DMAMUX_CCR_SPOL_RISING, DMAMUX_CCR_SPOL_FALLING, and
DMAMUX_CCR_SPOL_BOTH.
* DMAMUX_CCR_SYNCID_SHIFT: Fix comment. Was "Bits 24-26" (3 bits)
but datasheet shows bits 24-28 (5 bits).
* DMAMUX_CCR_SYNCID_MASK: Fix mask. Was 0x7 (3 bits) but datasheet
shows (5 bits) 0x1f.
* DMAMUX1_CSR_SOF(x): Add parenthesis around macro parameter
expansion.
* DMAMUX1_CFR_SOF(x): Rename to DMAMUX1_CFR_CSOF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMUX_RGCR_GPOL_MASK: Fix incorrect mask. Was 0x7 (3 bits) but
datasheet shows only 2 bits (0x3).
* Add missing defines DMAMUX_RGCR_GPOL_NONE,
DMAMUX_RGCR_GPOL_RISING, DMAMUX_RGCR_GPOL_FALLING, and
DMAMUX_RGCR_GPOL_BOTH.
* DMAMUX_RGCR_GNBREQ_SHIFT: Fix incorrect value. Was 17 (collision
with DMAMUX_RGCR_GPOL_SHIFT) but datasheet and comment both show
this bitfield at bits 19-23.
* DMAMUX_RGCR_GNBREQL_MASK: Fix incorrect mask. Was 0x7 (3 bits)
but datasheet shows 5 bits (0x1f).
* DMAMUX1_RGSR_SOF(x): Rename to DMAMUX1_RGSR_OF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMUX1_RGCFR_SOF(x): Rename to DMAMUX1_RGCFR_COF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMAP_MAP(d,c): Add parenthesis around macro parameter
expansion.
* Fix nxstyle errors.
arch/arm/src/stm32/hardware/stm32_spi.h:
* Avoid numerous ifdef on STM32 part numbers and make the
different variations of SPI peripheral features more
self-documenting: based on STM32_HAVE_IP_SPI_V* defines
from chip.h, define some or all of HAVE_SPI_I2S,
HAVE_SPI_TI_MODE, HAVE_SPI_ARB_DATA_SIZE, HAVE_SPI_FIFOS,
HAVE_SPI_NSSP, HAVE_SPI_I2S_ASTRT, and make decisions on
which registers and bitfields to define based on them.
* Define registers and bitfields for STM32_HAVE_IP_SPI_V4,
currently used only for STM32G47XX family MCUs, including
SPI_CR1_CRCL, SPI_CR2_NSSP, SPI_CR2_FRXTH, SPI_CR2_LDMARX,
SPI_CR2_LDMATX, SPI_CR2_DS_SHIFT/SPI_CR2_DS_MASK,
SPI_SR_FRLVL_SHIFT/SPI_SR_FRLVL_MASK, and
SPI_I2SCFGR_ASTRTEN.
* SPI_I2SCFGR_I2SSTD_PHILLIPS: Was defined incorrectly as
(xx << SPI_I2SCFGR_I2SSTD_SHIFT). Corrected this to
(0 << SPI_I2SCFGR_I2SSTD_SHIFT).
* SPI_I2SCFGR_I2SSTD_MSB: Was defined incorrectly as
(0 << SPI_I2SCFGR_I2SSTD_SHIFT). Corrected this to
(1 << SPI_I2SCFGR_I2SSTD_SHIFT).
* Fix nxstyle errors.
arch/arm/include/stm32/chip.h:
* Add new section "Peripheral IP versions" and specify version of
SPI IP block for STM32F10XX, STM32F20XX, STM32F30XX, STM32F33XX,
STM32F37XX, STM32F4XXX, STM32G47XX, and STM32L15XX.
arch/arm/src/stm32h7/hardware/stm32_dmamux.h:
* DMAMUX1_CSR_SOF(x): Add parenthesis around macro parameter
expansion.
* DMAMUX1_CFR_SOF(x): Rename to DMAMUX1_CFR_CSOF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMUX_RGCR_GPOL_MASK: Fix incorrect mask. Was 7 (3 bits) but
datasheet shows only 2 bits.
* Add missing defines DMAMUX_RGCR_GPOL_NONE,
DMAMUX_RGCR_GPOL_RISING, DMAMUX_RGCR_GPOL_FALLING, and
DMAMUX_RGCR_GPOL_BOTH.
* DMAMUX_RGCR_GNBREQ_SHIFT: Fix incorrect value. Was 17 (collision
with DMAMUX_RGCR_GPOL_SHIFT) but datasheet and comment both show
this bitfield at bits 19-23.
* DMAMUX_RGCR_GNBREQL_MASK: Fix incorrect mask. Was 7 (3 bits) but
datasheet shows 5 bits.
* DMAMUX1_RGSR_SOF(x): Rename to DMAMUX1_RGSR_OF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMUX1_RGCFR_SOF(x): Rename to DMAMUX1_RGCFR_COF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMAP_MAP(d,c): Add parenthesis around macro parameter
expansion.
This change improves upon current support for pin interrupts. Before,
a pin interrupt was handled (with nrf52_gpiote_setevent) using one
of the eight available GPIOTE channels. Moreover, it didn't event let
the user specify which channel to use (simply tried to get a free one).
Also, it was buggy since it did not consider unsetting the callback.
Besides GPIOTE channels, there is another way to deal with pin interrupts.
The GPIO peripheral is capable of generating a PORT event
(for the whole GPIO port) depending on the pin SENSE configuration
(HIGH or LOW, or NONE) and GPIO DETECTMODE register
(latching or non-latching).
This change then renames nrf52_gpiote_setevent into nrf52_gpiote_set_ch_event,
maintaining functionality of original function, but now allows specifying
channel (and correctly handles unsetting the callback). Then, a
new nrf52_gpiote_set_pin_event is added, which allows to set a callback
for a given pin. During initialization, interrupt for the PORT event is
enabled and handled in such way that for each pin whose corresponding
bit in LATCH register (indicates the result of pin SENSEing) the
callback for this pin will be invoked. This mechanism means that
every pin can get an ISR. It also avoids using GPIOTE channels for this
purpose which carry higher current consumption.
This new per-pin callback mechanism has some added memory requirement
so it can be disabled and its default is dependant on DEFAULT_SMALL.
When disabled, a callback for the PORT event can be set directly
with nrf52_gpiote_set_port_event
There was only one use of nrf52_gpio_setevent() which was migrated
into nrf52_gpio_set_ch_event() passing channel zero.
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_flash.h:
* Merge comments when they are section separators for
similar/related registers:
- TIVA_FLASH_FWPWRITE*
- TIVA_FLASH_FSM_SECTOR1*
- TIVA_FLASH_FSM_BSLE*
- TIVA_FLASH_FSM_BSLP*
When HAVE_HSI_CONTROL, adc_reset_hsi_disable() calls adc_reset()
followed by adc_shutdown() and this combination is called before
adc_setup() by upper level ADC driver. Without this patch,
priv->initialized wraps from 0 to 255 in this case.
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi3_refsys.h:
* Fix syntax error. The define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MIN
had an unintentional comment closing "*/" in the middle of its
name.
This separation allows to interact with the watchdog from OS code,
for example initiating the watchdog very early on boot. Moreover,
these changes make the lower-half driver support an already running
watchdog, which may happen if there's a bootloader which already
started it.
Summary:
- This commit fixes kernel stack dump information
Impact:
- Affects armv7-a with kernel build
Testing:
- Built with sama5d4-ek:knsh
- Not tested
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same logic for armv7-m
- NOTE: stack pointer alignment is 4-byte
Impact:
- Affects armv6-m with interrupt stack enabled
Testing:
- Built with freedom-kl25z:nsh (CONFIG_ARCH_INTERRUPTSTACK=2048)
- Not tested but should work
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same logic for armv7-m
- NOTE: stack pointer alignment is 8-byte
Impact:
- Affects armv8-m with interrupt stack enabled
Testing:
- Not tested but should work
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same logic for armv7-a
- NOTE: stack pointer alignment is 8-byte
Impact:
- Affects armv7-r with interrupt stack enabled
Testing:
- Not tested but should work
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same logic for armv7-a
- NOTE: stack pointer alignment is 4-byte
Impact:
- Affects arm (arm7/9) and c5471 with interrupt stack enabled
Testing:
- Built with c5471evm.nsh (CONFIG_ARCH_INTERRUPTSTACK=2048)
- Built with ea3131:nsh (CONFIG_ARCH_INTERRUPTSTACK=2048)
- Not tested but should work
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Remove -4/-8 offset coding in imx_irq.c and arm_vectors.S
- Instead, add SP adjustment after calling setirqstack/setfiqstack
- Fix off-by-one irq/fiq stack allocation in 8-byte aligned arch
- Fix comments on the user stack pointer in arm_vectors.S
- Also, fix up_dumpstate() to extract the user stack pointer
- NOTE: stack pointer alignment is 8-byte
Impact:
- Affects armv7-a with interrupt stack enabled
Testing:
- Tested with sabre-6quad:smp with QEMU
- Tested with sabre-6quad:nsh with QEMU
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit fixes CPUx IDLE stack top for SMP
- Also removes SMP_STACK_TOP from smp.h
Impact:
- Affects armv7-a SMP only
Testing:
- Tested with sabre-6quad:smp (QEMU)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
There is a good case on sim platform:
When we input some cmd and click enter key to start application in terminal,
this context will change to application from IDLE loop. Althrough entey key '\r'
has been received to recv buffer and complete post semaphore of reader, but
pollnotify may not be called because context change. So when application run
poll function, because no events happend and poll enter wait, context will
again change to IDLE loop, this pollnotify of IDLE loop will run to send poll
events, poll function of applicaton will wake up. It's wrong!
Change-Id: I812a889f2e90781a9c3cb4b0251cccc4d32bebd1
Signed-off-by: dongjiuzhu <dongjiuzhu1@xiaomi.com>
Summary:
- Modify arm_intstack_base() to return "top" of the IRQ stack for the current CPU
- This change fixes IRQ stack dump information for ARM SMP
- Add arm_intstack_alloc() to return "bottom" of the IRQ stack for the current CPU
- Also, these functions are now implemented in xxx_irq.c (imx/cxd56/lc823450)
- up_color_intstack() and up_check_intstack() now call arm_intstack_alloc()
- These semantics are now consistent with non-SMP case
- up_color_intstack() now initializes whole IRQ stack region for SMP
- Adjust IRQ stack top address for each CPU (e.g. -8)
- Fix setintstack to handle in case of NCPUS=1 (cxd56, lc823450)
- Adjust INTSTACK_SIZE to 8 bytes alignment (cxd56, lc823450)
- Refactor setintstack for lc823450
- Remove old IRQ stack coloring code from up_irqinitialize() (lc823450)
- Introduce g_cpu_intstack_top for lc823450
- Refactor header files
Impact:
- Affects imx6/cxd56xx/lc823450 SMP with interrupt stack enabled
Testing:
- Tested with sabre-6quad:smp (with QEMU, NCPUS=1 and 4)
- Tested with spresense:wifi_smp (NCPUS=1 and 2)
- Tested with lc823450-xgevk:rndis (NCPUS=1 and 2)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
cfsetispeed() now stores baud rate to c_cflag member of
struct termios, so it must not be overridden later on.
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
1.Get the stack pointer from sp instead of .Lstkinit's field
2.Make g_idle_topstack point to the end of the idle stack
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
arch/arm/src/tiva/cc13xx/cc13x0_rom.h,
arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v2_rom.h:
* Fix nxstyle errors; nxstyle was complaining about lack of a
space after comma because of the presence of line
continuation backslashes immediately after the comma.
Removed these backslashes as they are not necessary: these
lines are typedefs, not preprocessor defines.
arch/arm/src/tiva/cc13xx/cc13x2_v2_trim.c:
* Fix nxstyle errors.
* No functional changes; however modified one function,
trim_wakeup_fromshutdown(), to avoid blocks that existed
only to declare variables mid-function; nxstyle was
complaining about the positions of the opening and
closing braces of those blocks.
Summary:
- During Wi-Fi audio streaming test, I noticed data corruption in tcb
- Finally, I found an issue in IRQ request handing with IPI
- This commit fixes this issue
Impact:
- Affects SMP only
Testing:
- Tested with spresense:wifi_smp
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit adds interrupt stack for SMP
Impact:
- Affects SMP only
Testing:
- Tested with spresense:wifi_smp with CONFIG_ARCH_INTERRUPTSTACK=2048
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- The handle_irqreq() is used for remote IRQ control.
- The logic is called via IPI (Inter-Processor Interrupt)
- And the handler should handle only one request
- However, I noticed that the handler handles up to two requests
- This commit fixes this issue
Impact:
- Affects SMP cases only
Testing:
- Tested with spresense:wifi_smp
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Not all boards have an interrupt line from the phy to
the Soc. This commit allows the phy to be polled for
link status.
This may not work on all MAC/PHY combination that
have mutually exclusive link management and operating
modes. The STM32F7 and LAN8742AI do not have such a
limitation.
Summary:
- I found an issue with up_interrupt_context() when testing.
- And finally found that up_interrupt_context() is not atomic.
- This commit fixes the issue
Impact:
- Affects SMP only
Testing:
- Tested with spresense:wifi_smp and sabre-6quad:smp (qemu)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
There was no error handling before and it would block on common
cases like NACK which meant that you could not use the i2ctool
to perform a scan of the bus.
This does not handle the interrupt flow which also has incomplete
error handling.
When the Head to Tail relationship was H < T, then
only the tail to end of buffer was sent.
The fix is: In the txdma completion to do a second
the DMA operation using nbuffer if the nlength is
non zero.
stm32f7:serial UART5 use actual size
UART5 was using the CONFIG_UART5_TXBUFSIZE
not the UART5_TXBUFSIZE_ADJUSTED.
Since the buffer size was adjusted up, this
has no dcache implications.
If the UART5_TXBUFSIZE_ADJUSTED is larger
then CONFIG_UART5_TXBUFSIZE it will present
a larger usable buffer to the system's
serial driver.
This implements the missing callback hooks nrf52_spi0/1/2/3register
that are usually used with mmcsd for card detection.
This also stubs out the missing spi trigger function which is not
used on this platform.
The card detect was tested with the nRF52-feather board and a
modified KeyBoard FeatherWing.
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
and remove the special handling in the stack dump
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Ia1ef9a427bd4c7f6cee9838d0445f29cfaca3998
The current EasyDMA implementation will fail if a transfer of over
255 bytes is requested with no warning.
Also we do not set the RX and TX transfer lengths to 0 if the
buffer is NULL which can cause data to be written to the old
address as well as cause unexpected transaction lenghts.
Example:
transfer 1:
rx_len = 10
rx_buff != NULL
tx_len = 10
tx_buff != NULL
transfer 2:
rx_len = 2
rx_buff != NULL
tx_buff == NULL
Total transaction length for the second would be 10 because it
would still be using the old rx length of 10 and would
corrupt data in the old rx buffer.
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
EXTRAFLAGS is already applied to *FLAGS in board's Make.defs (and
it applies to whole build, not just arch-code). EXTRAFLAGS is passed
around each make call to the complete build.
KDEFINE is already added to EXTRAFLAGS in main Makefile so no need
to add it again in arch-level Makefile
1.Reduce the default size of task_group_s(~512B each task)
2.Scale better between simple and complex application
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Ia872137504fddcf64d89c48d6f0593d76d582710
This commit exends systimer options for nRF52 arch. It is possible
to use ARM SysTick either for tickless or non-tickless mode. Also,
it is possible to use the RTC peripheral for tickless mode. This
also re-enables support for WFI/WFE sleep if RTC is used, since
this counter continues to run in this mode (in contrast to SysTick).
Summary:
- I noticed that ldrex/strex on cxd56xx have an issue
- The issue is still under investigation
- This commit introduces a custom testset to avoid the issue
Impact:
- Affects cxd56xx in SMP mode if it is enabled
Testing:
- Tested with spresense:wifi_smp
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I noticed that ostest sometimes stops with DEBUGASSERT
- Finally I found a bug that cpu1 can not disable interrupt
- This commit initializes nvic to fix this bug
Impact:
- Only affects cxd56 in SMP mode
Testing:
- spresense:smp and spresense:wifi_smp with DEBUG_ASSERTIONS=y
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
arch/arm/src/stm32/stm32_lowputc.c:
* stm32_lowsetup(): Ensure the USART is disabled before attempting
to configure it because some register bits cannot be modified
otherwise. This solves an issue that was encountered when a
serial bootloader did not perform a full teardown/cleanup before
launching NuttX.
Summary:
- ARCH_GLOBAL_IRQDISABLE was initially introduced for LC823450 SMP
- At that time, i.MX6 (quad Cortex-A9) did not use this config
- However, this option is now used for all CPUs which support SMP
- So it's good timing for refactoring the code
Impact:
- Should have no impact because the logic is the same for SMP
Testing:
- Tested with board: spresense:smp, spresense:wifi_smp
- Tested with qemu: esp32-core:smp, maix-bit:smp, sabre-6quad:smp
- Build only: lc823450-xgevk:rndis, sam4cmp-db:nsh
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
PR #1450 broke the Cygwin build. Refer to Issue #1672.
The use of of logic like:
EXTRA_LIBPATHS += -L "${dir ${shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libgcc.a}}"
fails when the Toolchain $(CC) is a native Windows toolchain. That is because the returned path is a Windows-style patch which cannot be handled by the make 'dir' command. Commit 4910d43ab0 reorganized a lot of definitions and replaced the correct code with the use of the limit make 'dir' command. The original code used the Bash dirname command which does not suffer from this limitation; it can handle both POSIX and Windows paths.
This was verified using the stm32f4discover:nsh toolchain with the Windows native ARM Embedded toolchain. That toolchain returns:
arm-none-eabi-gcc --print-file-name=libgcc.a
c:/program files (x86)/gnu tools arm embedded/9 2019-q4-major/bin/../lib/gcc/arm-none-eabi/9.2.1/libgcc.a
Comments only. No functional changes. See STM32G474 Reference Manual
(RM0440 Rev 4), section 3.4.1, Table 11, "Option byte organization."
arch/arm/src/stm32/hardware/stm32g47xxx_memorymap.h:
* STM32_OPTION_BASE: The comment incorrectly said the range was
0x1fff7800-0x1fff780f for a total of 16 Option Bytes. Corrected
this to 0x1fff7800-0x1fff782f, as the device has 48 Option Bytes
for this option block.
* STM32_OPTION_BASE2: The comment incorrectly said the range was
0x1ffff800-0x1ffff80f for a total of 16 Option Bytes. Corrected
this to 0x1ffff800-0x1ffff82f, as the device has 48 Option Bytes
for this option block.
Summary:
- This commit improves SPI performance.
- For small data, it does not use DMA.
Impact:
- All use cases which use SPI with DMA
Testing:
- Tested with spresense:wifi and spresense:example_lcd
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit fixes IRQ control for the following use case
- The gs2200m Wi-Fi driver requests SPI-DMA to receive a packet.
- cxd56_dma.c enables IRQ for the SPI-DMA and start transfer.
- Then LCD driver requests SPI-DMA to display an image.
- These SPI-DMAs use different DMA channels but share the DMA controller.
- Also, they share the same IRQ.
- When the first SPI-DMA finishes the transfer, it disables the IRQ.
- And if the second SPI-DMA finishes the transfer just after the IRQ disabled.
- The second SPI-DMA will be in a deadlock condition.
- To resolve this issue, do not control IRQ during DMA transfer.
- Instead, up_enable_irq() is called in up_dma_initialize()
Impact:
- All use cases which use DMA
Testing:
- Tested with spresense:wifi with LCD
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
boards: metro-m4 Add support for starting the watchdog timer on the metro-m4.
Testing:
- Build check only
Signed-off-by: Leomar Mateus Radke <leomar@falker.com.br>
Summary:
- This commit adds SMP support to cxd56_farapi.c
- nxplayer now works in SMP mode
Impact:
- Spresense in SMP mode only
Testing:
- Add the following configs to spresense:wifi
- +CONFIG_SCHED_INSTRUMENTATION=yy
- +CONFIG_SCHED_INSTRUMENTATION_BUFFER=y
- +CONFIG_SMP=y
- +CONFIG_SMP_NCPUS=2
- +CONFIG_SPINLOCK_IRQ=y
- Run nxplayer and play an WAV file on uSD card
- NOTE: http streaming playback would cause deadlocks
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Fixes:
##[error]net/tun.c:837:13: error: conflicting types for 'tun_poll_expiry'
837 | static void tun_poll_expiry(FAR void *arg)
| ^~~~~~~~~~~~~~~
net/tun.c:196:13: note: previous declaration of 'tun_poll_expiry' was here
196 | static void tun_poll_expiry(wdparm_t arg);
| ^~~~~~~~~~~~~~~
And
##[error]net/tun.c:881:57: error: passing argument 4 of 'wd_start' makes integer from pointer without a cast [-Werror=int-conversion]
881 | wd_start(&priv->txpoll, TUN_WDDELAY, tun_poll_expiry, priv);
| ^~~~
| |
| struct tun_device_s *
In file included from /github/workspace/sources/nuttx/include/nuttx/sched.h:41,
from /github/workspace/sources/nuttx/include/sched.h:34,
from /github/workspace/sources/nuttx/include/nuttx/arch.h:81,
from net/tun.c:60:
/github/workspace/sources/nuttx/include/nuttx/wdog.h:134:42: note: expected 'wdparm_t' {aka 'long unsigned int'} but argument is of type 'struct tun_device_s *'
134 | wdentry_t wdentry, wdparm_t arg);
| ~~~~~~~~~^~~
And
chip/cxd56_rtc.c: In function 'up_rtc_initialize':
##[error]chip/cxd56_rtc.c:358:3: error: too many arguments to function 'cxd56_rtc_initialize'
358 | cxd56_rtc_initialize(1, NULL);
| ^~~~~~~~~~~~~~~~~~~~
chip/cxd56_rtc.c:253:13: note: declared here
253 | static void cxd56_rtc_initialize(wdparm_t arg)
| ^~~~~~~~~~~~~~~~~~~~
boards: metro-m4 Add support for starting the watchdog timer on the metro-m4.
Testing:
- Build check only
Signed-off-by: Leomar Mateus Radke <leomar@falker.com.br>
to save the preserved space(1KB) and also avoid the heap overhead
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I694073f68e1bd63960cedeea1ddec441437be025
Interrups were blocked 1*n/baud Seconds. The former comment indicates
there was an asumption that the TXE would be set at DMA completion.
In reality this is not true. There can be 1 char in the TX Shift
register and one in the TX holding register, when DMA completes.
Waiting on TXE is not needed at all. The DMA will resume on the
DMA req when the TX holding register is written to the TX Shift
register.
boards: metro-m4 Add support for starting the watchdog timer on the metro-m4.
Testing:
- Build check only
Signed-off-by: Leomar Mateus Radke <leomar@falker.com.br>
Summary:
- Fix typo in Kconfig so that we can configure IMXRT_ENET_NRXBUFFERS.
Impact:
- imxrt family with ethernet configuration
Testing:
- imxrt1060-evk:netnsh
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
