Commit Graph

218 Commits

Author SHA1 Message Date
Xiang Xiao
41d576f62b arch/riscv: Reuse the common up_schedule_sigaction implementation
to avoid the code duplication

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-12-20 20:26:27 -08:00
Xiang Xiao
d42c5a0bf6 arch/risc-v: Move csr.h to common place
since CSR definition is same for 32bit and 64bit arch

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-12-19 08:41:33 +09:00
Xiang Xiao
fe8122ee2b arch/risc-v: Remove duplicated declaration for up_irq_save and up_irq_restore
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-12-19 08:29:42 +09:00
Abdelatif Guettouche
ecede04263 arch/*/src/Makefile: Generate dependencies for head files.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-12-15 21:00:52 -06:00
Xiang Xiao
625eef20f0 arch: Remove the special check for idle thread in up_use_stack
since the idle thread don't call up_use_stack anymore

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-12-16 09:54:29 +09:00
Xiang Xiao
efee1c6ded arch: Initialize the idle thread stack info directly
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-12-16 09:54:29 +09:00
John Bampton
ba12c6c0cf Fix spelling 2020-12-12 19:18:08 +01:00
Masayuki Ishikawa
409c65ce0b arch, sched: Fix global IRQ control logics for SMP
Summary:
- This commit fixes global IRQ control logic
- In previous implementation, g_cpu_irqset for a remote CPU was
  set in sched_add_readytorun(), sched_remove_readytorun() and
  up_schedule_sigaction()
- In this implementation, they are removed.
- Instead, in the pause handler, call enter_critical_setion()
  which will call up_cpu_paused() then acquire g_cpu_irqlock
- So if a new task with irqcount > 1 restarts on the remote CPU,
  the CPU will only hold a critical section. Thus, the issue such as
  'POSSIBLE FOR TWO CPUs TO HOLD A CRITICAL SECTION' could be resolved.
- Fix nxsched_resume_scheduler() so that it does not call spin_clrbit()
  if a CPU does not hold a g_cpu_irqset
- Fix nxtask_exit() so that it acquires g_cpu_irqlock
- Update TODO

Impact:
- All SMP implementations

Testing:
- Tested with smp, ostest with the following configurations
- Tested with spresense:wifi_smp (NCPUS=2,4)
- Tested with sabre-6quad:smp (QEMU, dev board)
- Tested with maix-bit:smp (QEMU)
- Tested with esp32-core:smp (QEMU)
- Tested with lc823450-xgevk:rndis

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-12-10 08:33:42 +01:00
Huang Qi
4078548ae3 risc-v: Introduce basic setjmp support
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2020-12-04 09:40:07 -03:00
YAMAMOTO Takashi
e0d535c317 arch/risc-v/src/common/riscv_createstack.c: Fix a syslog format 2020-11-24 22:31:33 -08:00
YAMAMOTO Takashi
67ea358f96 arch/risc-v/src/litex/litex_schedulesigaction.c: Fix syslog formats 2020-11-24 22:31:33 -08:00
Masayuki Ishikawa
37dad5dd04 Revert "arch: k210: Fix the pause handler for SMP"
This reverts commit a500bd0238.
2020-11-25 00:02:37 +01:00
YAMAMOTO Takashi
21a84e4558 arch/risc-v/src/rv64gc/riscv_sigdeliver.c: Fix a syslog format 2020-11-22 19:01:05 -08:00
YAMAMOTO Takashi
9e04704cb6 arch/risc-v/src/k210/k210_schedulesigaction.c: Fix syslog formats 2020-11-22 19:01:05 -08:00
YAMAMOTO Takashi
982061a9e0 arch/risc-v/src/rv64gc/riscv_swint.c: Fix a syslog format 2020-11-22 19:01:05 -08:00
YAMAMOTO Takashi
c934214bb3 arch/risc-v/src/rv32im/riscv_sigdeliver.c: Fix a syslog format 2020-11-22 19:01:05 -08:00
YAMAMOTO Takashi
d8c5095fa7 arch/risc-v/src/fe310/fe310_schedulesigaction.c: Fix syslog formats 2020-11-22 19:01:05 -08:00
YAMAMOTO Takashi
263e4b991f arch/risc-v/src/rv32im/riscv_swint.c: Fix a syslog format 2020-11-22 19:01:05 -08:00
YAMAMOTO Takashi
35449e4d14 risc-v: Don't use non existent "saved_status"
It seems like a copy-and-paste leftover from mips.
Replace them with saved_int_ctx.
(Shouldn't these files inherit the copyright notice from mips?)
2020-11-22 05:18:55 -08:00
YAMAMOTO Takashi
9ceb61d3a9 risc-v 64-bit: Fix SCN/PRI.PTR definitions 2020-11-22 05:18:29 -08:00
Matias N
d5b6ec450f Parallelize depend file generation 2020-11-22 09:02:59 -03:00
Masayuki Ishikawa
a500bd0238 arch: k210: Fix the pause handler for SMP
Summary:
- Apply the same logic added to cxd56_cpupause.c

Impact:
- SMP only

Testing:
- Tested with maix-bit:smp (QEMU)
- Run smp and ostest

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-11-20 00:49:25 -08:00
YAMAMOTO Takashi
cce626b545 risc-v: Add _intmax_t and _uintmax_t 2020-11-19 00:49:56 -08:00
YAMAMOTO Takashi
e99321bf9d risc-v 32-bit: Fix types to match what the compiler expects
spacetanuki% riscv64-unknown-elf-gcc -march=rv32im -mabi=ilp32 -dM -E - < /dev/null | grep INT32_TYPE
    #define __INT32_TYPE__ long int
    #define __UINT32_TYPE__ long unsigned int
    spacetanuki% riscv64-unknown-elf-gcc -march=rv32im -mabi=ilp32 -dM -E - < /dev/null | grep INT64_TYPE
    #define __INT64_TYPE__ long long int
    #define __UINT64_TYPE__ long long unsigned int
    spacetanuki% riscv64-unknown-elf-gcc -dM -E - < /dev/null | grep LP64
    #define __LP64__ 1
    #define _LP64 1
    spacetanuki%
2020-11-19 00:49:56 -08:00
YAMAMOTO Takashi
723cc14009 risc-v: Switch int64_t from long long to long
So that it matches what the toolchain expects.

    spacetanuki% riscv64-unknown-elf-gcc --version
    riscv64-unknown-elf-gcc (SiFive GCC 8.3.0-2019.08.0) 8.3.0
    Copyright (C) 2018 Free Software Foundation, Inc.
    This is free software; see the source for copying conditions.  There is NO
    warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

    spacetanuki% riscv64-unknown-elf-gcc -dM -E - < /dev/null | grep UINT64_TYPE
    #define __UINT64_TYPE__ long unsigned int
    spacetanuki%
2020-11-19 00:49:56 -08:00
zhongan
a396b191d4 rv32im: set compressed instruction enabled as default.
Signed-off-by: zhongan <zhongan@xiaomi.com>
2020-11-17 18:53:10 -08:00
zhongan
9eae6edfde rv32im: fix typo.
Signed-off-by: zhongan <zhongan@xiaomi.com>
2020-11-17 18:53:10 -08:00
YAMAMOTO Takashi
0390037472 arch/risc-v/src/gap8/gap8_uart.c: Fix a type mismatch 2020-11-16 08:29:00 -08:00
YAMAMOTO Takashi
1170d0f71c arch/risc-v/src/fe310/fe310_serial.c: Fix a type mismatch 2020-11-16 08:29:00 -08:00
YAMAMOTO Takashi
ce7fae15e4 arch/risc-v/src/k210/k210_serial.c: Fix a type mismatch 2020-11-16 08:29:00 -08:00
YAMAMOTO Takashi
316ca6cd86 arch/risc-v/src/litex/litex_serial.c: Fix a type mismatch 2020-11-16 08:29:00 -08:00
YAMAMOTO Takashi
ee06d08548 arch/risc-v/src/nr5m100/nr5_serial.c: Fix a type mismatch 2020-11-16 08:29:00 -08:00
YAMAMOTO Takashi
f752b360f6 risc-v inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
Juha Niskanen
d65acc6db4 arch: serial: fix typos and run nxstyle
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
2020-10-31 15:39:50 +01:00
Xiang Xiao
eb4121ce38 Change all 'Nuttx' to 'NuttX'
Unify the naming convention

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-10-20 01:45:06 -07:00
liuhaitao
d5c6bfe6cf arch: Add custom arch chip build support
Just like custom board build support, add custom arch chip build
support.

Change-Id: I71c87e6b2195501a1b1d728b71d7cbe344951057
Signed-off-by: liuhaitao <liuhaitao@xiaomi.com>
2020-10-20 14:48:16 +08:00
Abdelatif Guettouche
609a5fa4f0 arch/: Add the ARCH_SRC directory to the context and clean_context
targets

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-10-17 22:46:27 +09:00
Yoshinori Sugino
444a05131c arch/risc-v/include: Fix nxstyle warnings
No functional changes
2020-10-10 14:24:52 +01:00
Yoshinori Sugino
aae4e15d9b arch/risc-v/src: Fix nxstyle warnings
No functional changes
2020-10-10 11:44:26 +01:00
Masayuki Ishikawa
e8ec8fb4b4 arch: risc-v: Fix up_interrupt_context() for SMP
Summary:
- Apply the same fix for Arm SMP

Impact:
- Affects SMP only

Testing:
- Tested with maix-bit:smp (qemu)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-09-30 08:32:25 -06:00
Yoshinori Sugino
3de85be15a arch/risc-v/src: Branch to up_sigdeliver() with interrupts disabled
When executing an MRET instruction, MIE is set to MPIE.
In order to branch to up_sigdeliver() with interrupts disabled,
we need to change MPIE, not MIE.
2020-09-28 22:41:46 -07:00
Yoshinori Sugino
2adec1f366 arch/risc-v/src/fe310: Branch to up_sigdeliver() with interrupts disabled
When executing an MRET instruction, MIE is set to MPIE.
In order to branch to up_sigdeliver() with interrupts disabled,
we need to change MPIE, not MIE.
2020-09-28 22:41:46 -07:00
Yoshinori Sugino
698008d1e5 Fix typos 2020-09-28 13:54:43 +08:00
zhongan
6240977341 rv32im: add missing call of 'up_savefpu'.
Change-Id: Iaf2e212a4fdea2f5f04a178d24755e0e37a30ef6
Signed-off-by: zhongan <zhongan@xiaomi.com>
2020-09-23 10:22:45 +01:00
zhongan
07dd053e86 risc-v: add putreg64 for mtimer registers.
Change-Id: I18fe312c95c73966f5c09fd18081b0c72923e2ac
Signed-off-by: zhongan <zhongan@xiaomi.com>
2020-09-23 10:22:45 +01:00
zhongan
657d1c9fdc Add and fix CSR macros listed in RISC-V spec V1.10.
Add csr operatiing macros.

Change-Id: Ia5c148d10709c21424c5ecaaca01b7d200fb8e01
Signed-off-by: zhongan <zhongan@xiaomi.com>
2020-09-21 07:35:56 -07:00
Xiang Xiao
bf7399a982 arch: Initialize idle thread stack information
and remove the special handling in the stack dump

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Ia1ef9a427bd4c7f6cee9838d0445f29cfaca3998
2020-09-16 06:57:29 -07:00
Matias N
166242c171 use "export" to expose TOPDIR to all child make instead of passing it around every time 2020-09-15 21:11:33 -07:00
Matias N
3d1159007f Remove extra application of EXTRAFLAGS and KDEFINE and the arch-level
EXTRAFLAGS is already applied to *FLAGS in board's Make.defs (and
it applies to whole build, not just arch-code). EXTRAFLAGS is passed
around each make call to the complete build.

KDEFINE is already added to EXTRAFLAGS in main Makefile so no need
to add it again in arch-level Makefile
2020-09-14 13:59:57 +09:00
Xiang Xiao
b0797263ca libc/stdio: Allocate file_struct dynamically
1.Reduce the default size of task_group_s(~512B each task)
2.Scale better between simple and complex application

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Ia872137504fddcf64d89c48d6f0593d76d582710
2020-09-11 17:58:17 +08:00