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41e3d9f174
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9731 Commits

Author SHA1 Message Date
David Sidrane
41e3d9f174 Kinetis:Refactor you use SIM_SOPT2_PLLFLLSEL, added warning 
The warning has been added because: SIM_SOPT2_PLLFLLSEL
  is a clock selection that may feed many clock subsystem:
   USB, TPM, SDHCSRC, LPUARTSRC. Therefore, there needs to
  be a global board level setting to select  the source for
  SIM_SOPT2_PLLFLLSEL and then  derive all the  sub selections
  and proper fractions/divisors for each modules clock.
 2017-02-22 10:42:52 -10:00
David Sidrane
12c24f2644 Kinetis:kinetis_clockconfig uses the correct ACKISO 
ACKISO is located in the PMC_REGSC on the majority
   of the Kinetis SoCs. With the exception of the
   MK40DXxxxZVLQ10 where ACKISO is located in LLWU_CS
 2017-02-22 10:42:52 -10:00
David Sidrane
1324b8c00a Kinetis:Resolves issues where Freescale moved ACKISO 
ACKISO is located in the PMC_REGSC on the majority
  of the Kinetis SoCs. With the exception of the
  MK40DXxxxZVLQ10 where ACKISO is located in LLWU_CS
 2017-02-22 10:42:52 -10:00
David Sidrane
a4b985f865 Kinetis:PMC defines are based on PMC feature configuration 2017-02-22 10:42:52 -10:00
David Sidrane
381ffa3083 Kinetis:SIM defines are based on SIM feature configuration 2017-02-22 10:42:52 -10:00
Gregory Nutt
bb059432ea Move local variables to top of function for compliance with coding standard. 2017-02-20 17:54:04 -06:00
Jussi Kivilinna
4dfb8268f3 stm32f7: stm32_allocateheap: allow use DTCM memory for heap 
STM32F7 has up to 128KiB of DTCM memory that is currently left unused.

This patch adds DTCM to main heap if CONFIG_STM32F7_DTCMEXCLUDE is not enabled.
 2017-02-20 08:42:51 -06:00
Gregory Nutt
4b4f0dc4df STM32L4 COMP: Remove some unused definitions 2017-02-20 08:41:43 -06:00
Gregory Nutt
0fc226dd53 Changes from review of last PR 2017-02-19 14:58:37 -06:00
Marc Rechté
1838171d43 Add twr-k64f120m config and fix some ENET related problems 2017-02-19 21:20:56 +01:00
Gregory Nutt
4033953878 STM32L4 COMP: Port from Motorola MDK. 2017-02-19 11:33:35 -06:00
Gregory Nutt
e61ded4a14 STM32L4: Add Comparator register definition file. 2017-02-19 10:09:17 -06:00
Gregory Nutt
d900e1fac0 STM32L4: Bring LPTIM driver in from the Motorola MDK. 2017-02-18 11:06:20 -06:00
Gregory Nutt
6bafdb1cdc Remove some dangling whitespace at the end of some lines. 2017-02-18 10:20:08 -06:00
Gregory Nutt
085616d651 STM32L4: Bring power management logic from Motrola MDK into NuttX 2017-02-18 10:18:42 -06:00
Gregory Nutt
6fe94b5724 Trivial cosmetic, alignement changes. 2017-02-17 17:50:56 -06:00
Gregory Nutt
e4e7528b1a Port STM32L4 SAI driver from MDK. 2017-02-17 15:13:36 -06:00
Gregory Nutt
377fadc816 STM32L4: Add SAI register definition header file. 2017-02-17 13:52:22 -06:00
Jussi Kivilinna
dd1aa2357b Allow board to configure HSE clock in bypass-mode. This is needed to enable HSE with Nucleo-F746ZG board. 2017-02-17 07:15:22 -06:00
Masayuki Ishikawa
add2fbfa85 LM3S Ethernet: Fix interrupt work in the last big commit. 2017-02-17 17:40:58 +09:00
Gregory Nutt
a49b349614 C library: Add swab() 2017-02-16 14:42:27 -06:00
Gregory Nutt
3b351615be Kinetis K66: Change necessary for correct build. 2017-02-16 11:33:36 -06:00
Spahlinger, Michael
42e8b12ec3 Fix for SAMv7 SPI: DLYBS value wass calculated, but never written to any registers. This led to incorrect timings on the bus. 2017-02-16 07:42:37 -06:00
Gregory Nutt
c3bfccf293 Kinetis PWM: Purely cosmetic changes from review. 2017-02-15 17:54:55 -06:00
David Sidrane
c83af148b1 Kinetis:Add FTM3 to PWM 2017-02-15 13:42:36 -10:00
David Sidrane
a95a6c43d3 Kinetis Support RMII clock source select 
This defined the RMII clock source select bits and allows
  the selection to be made via Kconfig
 2017-02-15 13:42:36 -10:00
Gregory Nutt
1474300276 LPC43: Rename HAVE_CONSOLE to HAVE_SERIAL_CONSOLE. We can, of course, always have a some console other than a serial console. 2017-02-15 07:23:18 -06:00
Alan Carvalho de Assis
058f06cc94 Fix typos introduced in previous commit 2017-02-15 07:16:15 -06:00
Gregory Nutt
077adf863e Merge branch 'master' of bitbucket.org:nuttx/nuttx 2017-02-14 19:31:58 -06:00
Alan Carvalho de Assis
1b996f1c7c Add usbnsh config to Bambino 200E board 2017-02-14 19:31:39 -06:00
Gregory Nutt
4043dd4aa0 LPC43 serial: Correct conditional logi that selects /dev/ttySN. Problem noted by Alan Carvalho de Assis. 2017-02-14 19:12:11 -06:00
David Sidrane
3423a4ecc2 Kinetis: Add comment the Freedom-K66F uses KSZ8081 PHY 2017-02-14 09:15:23 -10:00
David Sidrane
35fc713931 Kinetis K64 and K66 share mpu files 2017-02-14 09:15:23 -10:00
David Sidrane
84b206bf7e Kinetis K66 FMC 
Added K66 FMC register definition
 2017-02-13 14:35:52 -10:00
David Sidrane
7d80db5919 Kinetis K66 Pin Mux 2017-02-13 14:35:51 -10:00
David Sidrane
e28781ebeb Include K66 memory map 2017-02-13 14:35:51 -10:00
David Sidrane
6597e46ce7 Define Alternate addresses for IP blocks in both AIPS0 & AIPS1 
Added ALT version of RNGA, FTM2, DAC0 as a facility to later
   define secondary access via AIPS1 to these peripherals
 2017-02-13 14:35:51 -10:00
David Sidrane
bd7d7edcf8 Kinetis: Updated comment in clockconfig 2017-02-13 13:24:47 -10:00
David Sidrane
3840c802d1 Kinetis SPI and I2C are 0 based 
The K whole family line has max 4 or each. But the supported
  parts have the maximums listed below:

    K46 and K66    3 SPI SPI0-SPI2
    K46 and K66    4 I2C I2C0-I2C3
 2017-02-13 13:24:47 -10:00
David Sidrane
ddd1f8c507 Kinetis SDHC - Enable clock after selected 2017-02-13 13:24:47 -10:00
Manohara HK
b154531838 I found an issue inside the cp15_coherent_dcache function in file, arch/arm/src/armv7-r/cp15_coherent_dcache.S. 
The "mcr CP15_BPIALLIS(r0)" instruction is used for invalidating entire branch predictor.  But the problem is, since this is the generic code and can be called on any armv7-r architecture based CPU's.  It is a problem, if this instruction is called in uni processor configuration. Because, BPIALLIS (c7, 0, c1, 6) instruction is only added as part of the "Multiprocessing Extensions" (As per ARM® Architecture Reference Manual /ARMv7-A and ARMv7-R edition)

So in my opinion, this instruction should be under SMP configuration. In non-SMP configuration this instruction could become undefined.
 2017-02-13 06:33:15 -06:00
David Sidrane
a907bbc5d3 Typo up_exit.c edited online with Bitbucket 2017-02-09 20:38:15 +00:00
Gregory Nutt
3329a534f7 Remove spurious blank line. 2017-02-09 13:06:42 -06:00
Gregory Nutt
c55d8f15a1 Merged in david_s5/nuttx/upstream_bkp_fix (pull request #206) 
STM32 & STM32F7 Fixes the bkp reference counter issue

Approved-by: Gregory Nutt
 2017-02-09 19:03:04 +00:00
David Sidrane
550d259a28 STM32F7: Fixes the bkp reference counter issue 2017-02-09 08:39:51 -10:00
David Sidrane
169b3982a2 STM32: Fixes the bkp reference counter issue 2017-02-09 08:39:51 -10:00
Gregory Nutt
a292da29d0 Costmetic changes from review of last PR. 2017-02-09 08:39:31 -10:00
David Sidrane
7262a788c4 Better granualarity and erro checking of the board's MCG settings 
Allow for complete MCG_C2 definition from the boart.h file
  Moved #ifdef out of code by setting default values for
  Allow for individule bit setting in MCG_C2 for
    BOARD_EXTCLOCK_MCG_C2
    BOARD_MCG_C2_FCFTRIM
    BOARD_MCG_C2_LOCRE0
  Added range and sanity checking
 2017-02-09 08:39:31 -10:00
David Sidrane
b2deadd569 Support the Indexed name LOCK->LOCK0 2017-02-09 08:39:30 -10:00
David Sidrane
eee029eec1 MCG defines are based on the MCG feature configuration 
We define the bits as a common set of names. This means that
  an index may be added to a name i.e. LOCK is LOCK0 as that is
  the superset name.
 2017-02-09 08:39:30 -10:00