This adds initialization of the ksz9477 switch when used instead of
a PHY, directly connected to SGMII
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This change fixes the issue when SAMv7 GMAC sometimes does not start packet
transmission. The issue is that EMAC_NCR_TSTART is written to EMAC_NCR register
while tx descriptor is not delivered to memory.
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
According to the current implementation, "cxd56_cpu1siguninit" will only
be called once during the NuttX startup phase,
and it won't involve scenarios of multi-threaded concurrent access.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Some SD card connectors do not have separate card detection pin. In that
case card detection has to be done on CD/DAT3 data line. This means
software (i.e. architecture level driver) has to take care of pin
configuration switching (pin has to be set as data pin in case of
transfer and as interrupt card detection pin when there is no action
on data line).
This commit adds CD/DAT3 line card detection support for SAMv7 MCU.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Add a function to read PolarFire's serial number from system controller, and use the first five digits as device's mac address
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Workaround to avoid deadlock situation: The RX shall not try to wait for complete
frame in case there is RX errors detected.
In case mpfs_receive is called, it keeps waiting for complete frame and
also keeps the net_lock locked. In the mean while, the TX may run out of free
descriptors, but can not get net_lock mutex lock to be able to release used
descriptors. If there are no free TX descs it disables RX interrupts because
it may require to send response to the received frame.
So, TX side keeps RX interrupts disabled due to lack of free descriptors and
RX blocks TX to release those descs by stubbornly waiting for complete frame.
RPMSG is associated with the use of HPWORK / LPWORK queues.
After sending a message to the remote end (Linux), the system
waits for an ack before proceeding. Unfortunately this may
take sometimes more time than one would expect. Ack waiting is
also unnecessary: nothing is done with that information. Even
worse, the net_lock() is also held during the blocked time so
it blocks other network stacks that are unrelated to this.
Also reorganize the mpfs_opensbi_*.S so that the trap
handler is easily relocated in the linker .ld file without
the need to relocate the utils.S. This makes it easier to
separate the files into own segments. The trap file should be
located in the zero device.
Moreover, provide support for simultaneous ACK and message
present handling capabilities in both directions. There are
times when both bits are set but only other is being handled.
In the end, the maximum throughput of the RPMSG bus increases
easily 10-20% or even more.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This commits adds support of UART2 for EPS32S3 and fixes pin mode
assignment for iomux mode
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
The master clock frequency should be multiple of the sample rate
and bit clock at the same time. Then, check if the current master
clock satisfies such a condition and set it accordingly otherwise.
In order to gracefully stop the I2S stream, add an interface to set
a `streaming` status variable that sets the `AUDIO_APB_FINAL` flag
that will be handled by the upper layers of the audio subsystem.
According to RX/TX operation, the DMA descriptors (inlink/outlink)
should be set differently. When setting the inlink, the `suc_eof`
field must be cleared by software (it will be set by hardware when
a packet is received). Similarly, the `length` field will be set
by hardware a packet is received.
Define macros used to access the registers of the GDMA channels
according to the selected channel in the header file, enabling them
to be used by other drivers.
By splitting into two different functions the setup of the DMA
descriptors and the action of loading it to the GDMA outlink
register, it enables us to "cache" DMA descriptors ready to be send
and, then, just load them whenever we are able to actually send it.
The macro `SET_BITS` only sets the bits according to the bit mask
and, once it's being used to set the address field of the GDMA
inlink/outlink register, it's necessary to clean all the bits
corresponding to that field that were eventually setup previously
to avoid messing with the bits that correspond to the current
address being setup.
This option enables architecture-specific memory copy for dynamic code loading.
For example, Ambiq has MRAM regions for instruction which can't load by
the memcpy directly.
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
SiFive document: "ECC Error Handling Guide" states:
"Any SRAM block or cache memory containing ECC functionality needs to be
initialized prior to use. ECC will correct defective bits based on memory
contents, so if memory is not first initialized to a known state, then ECC
will not operate as expected. It is recommended to use a DMA, if available,
to write the entire SRAM or cache to zeros prior to enabling ECC reporting.
If no DMA is present, use store instructions issued from the processor."
Clean the cache at this early stage so no ECC errors will be flooding later.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Check that the base address and region size are properly aligned with
relation to each other.
With NAPOT encoding the area base and size are not arbitrary, as when
the size increases the amount of bits available for encoding the base
address decreases.
Implement the previously empty mpfs_ddr_rand with adapted "seiran128" code
from https://github.com/andanteyk/prng-seiran
This implements a non-secure prng, which is minimal in size. The DDR training
doesn't need cryptographically secure prng, and linking in the NuttX crypto
would increase the code size significantly for bootloaders.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Also move the DDRC clock enablement and reset to mpfs_init_ddr. This doesn't
change the functionality, but is the cleaner place for it.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Especially the write calibration must bail out if the memory test timeouts,
otherwise the device will get stuck in running the memory test in sequence,
and it will always timeout.
Negative error value was also not properly returned from mpfs_mtc_test.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
It doesn't make sense to try to auto-determine write latency, it may pass with too low value.
Keep the existing implementation if the write latency has been set to minimum
value, otherwise just set it.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Current implementation of QSPI in SPI mode was available only for MCUs
that do not have standard SPI at all. MCUs with both QSPI and SPI can
however also use QSPI in SPI mode and thus have one more SPI bus. This
commit adds required defines and config options to support QSPI in SPI
mode for all SAMv7 MCUs.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Calculate how long an I2C transation will take in microseconds, and use
this as the timeout for mpfs_i2c_sem_waitdone.
The reason for doing this is not to keep an i2c bus reserved for the full
1 second timeout, if e.g. a sensor is not on the bus / is faulty and
non-responsive. Reading the other sensors will be blocked for a relatively
long time (1 second) in this case. This fixes such behavior.
