Abdelatif Guettouche
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0f2b774dec
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arch/risc-v: Remove unused and undefined file section "Public Variables"
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
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2021-01-27 18:40:10 -08:00 |
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Xiang Xiao
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d42c5a0bf6
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arch/risc-v: Move csr.h to common place
since CSR definition is same for 32bit and 64bit arch
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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2020-12-19 08:41:33 +09:00 |
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Ouss4
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6eb6d31c32
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Fix nxstyle complaints
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2020-05-06 21:56:40 -06:00 |
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Ouss4
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a4dd967440
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arch/: Implement up_tls_info() for the rest of the architectures.
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2020-05-06 21:56:40 -06:00 |
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Nathan Hartman
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679b4fbee2
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arch: Fix included directed -> included directly
This typo had been copied and pasted into numerous irq and syscall
headers.
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2020-04-05 22:31:15 +01:00 |
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Xiang Xiao
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68951e8d72
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Remove exra whitespace from files (#189)
* Remove multiple newlines at the end of files
* Remove the whitespace from the end of lines
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2020-01-31 09:24:49 -06:00 |
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Gregory Nutt
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1c5ec07414
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arch/: Remove dangling space at the end of lines.
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2017-06-28 13:16:48 -06:00 |
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Ken Pettit
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201a32cf8c
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Add support for the RISC-V architecture and configs/nr5m100-nexys4 board. I will be making the FPGA code for this available soon (within a week I would say). The board support on this is pretty thin, but it seems like maybe a good idea to get the base RISC-V stuff in since there are people interested in it.
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2016-10-16 09:47:07 -06:00 |
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