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4664642cf7
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15783 Commits

Author SHA1 Message Date
Gregory Nutt
4664642cf7 Board specific code moved to boards directory and ipv6 support added 
Added support to crashdump for rx65n on sbram
Board specific code moved to boards directory and ipv6 support added
 2020-05-13 06:46:44 -06:00
Xiang Xiao
9607152e68 arm/gic: Don't pirnt log in arm_decodeirq 
it is unsafe place to do this

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I47fdb1a34a7f1d5c5d3c4f3c0030a60bf01c43c2
 2020-05-13 06:33:56 -06:00
Xiang Xiao
7ffafa3654 Remove executable bit from source code 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-05-13 06:32:13 -06:00
Masayuki Ishikawa
77f15c8b17 arch: cxd56xx: Apply the latest cxd56_dma.c and cxd56_spi from SDK 
See the following commit in SDK:

  commit 62a2fb4fd3001aefad9ec3b2e2e7c47e5b0f21e1
  Author: SPRESENSE <41312067+SPRESENSE@users.noreply.github.com>
  Date:   Fri Jan 24 13:32:04 2020 +0900

      Enable dummy transfer by SPI using DMA

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2020-05-13 13:11:08 +02:00
Xiang Xiao
517974787f Rename clock_systime[r|spec] to clock_systime_[ticks|timespec] 
follow up the new naming convention:
https://cwiki.apache.org/confluence/display/NUTTX/Naming+of+OS+Internal+Functions
 2020-05-10 14:35:50 -06:00
Gregory Nutt
3ac629bdfb Run all .c and .h files modifed by the PR though nxstyle. 2020-05-09 16:58:42 -03:00
Gregory Nutt
f92dba212d sched/sched/sched.h: Make naming of all internal names consistent: 
1. Add internal scheduler functions should begin with nxsched_, not sched_
2. Follow the consistent naming patter of https://cwiki.apache.org/confluence/display/NUTTX/Naming+of+OS+Internal+Functions
 2020-05-09 16:58:42 -03:00
Gregory Nutt
4b44b628ea Run nxstyle against all .c and .h files modified by this PR. 
All complaints fixed except for those that were not possible to fix:

- Used of Mixed case identifier in ESP32 files.  These are references to Expressif ROM functions which are outside of the scope of NuttX.
 2020-05-09 14:19:08 -03:00
Gregory Nutt
a4218e2144 include/nuttx/sched.h: Make naming of all internal names consistent: 
1. Add internal scheduler functions should begin with nxsched_, not sched_
2. Follow the consistent naming patter of https://cwiki.apache.org/confluence/display/NUTTX/Naming+of+OS+Internal+Functions
 2020-05-09 14:19:08 -03:00
Xiang Xiao
b7d922960f Fix nxstyle issue 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-05-08 07:20:49 -06:00
Gregory Nutt
2d78ed7c7e arch/sim/src/nuttx-names.dat: Add __errno() 
Needed to avoid collision with the host on simulator build.
 2020-05-08 01:58:25 +01:00
Ouss4
958999c443 arch/mips/src/common/mips_usestack.c: Include tls.h header. 2020-05-07 18:41:43 -06:00
Gregory Nutt
3dca5eba15 Completes the Implementation of the TLS-based errno 
- Remove per-thread errno from the TCB structure (pterrno)
- Remove get_errno() and set_errno() as functions.  The macros are still available as stubs and will be needed in the future if we need to access the errno from a different address environment (KERNEL mode).
- Add errno value to the tls_info_s structure definitions
- Move sched/errno to libs/libc/errno.  Replace old TCB access to the errno with TLS access to the errno.
 2020-05-07 23:11:34 +01:00
Ouss4
a6da3c2cb6 arch/*/*_checkstack.c: Get aligned address only when CONFIG_TLS_ALIGNED is 
enabled.
 2020-05-07 12:04:51 -06:00
Ouss4
e74899ff6d arch/risc-v/src/common/riscv_createstack.c: Fix the stack_color name. 2020-05-07 12:04:32 -06:00
Gregory Nutt
c2244a2382 Remove CONFIG_TLS 
A first step in implementing the user-space error is force TLS to be enabled at all times.  It is no longer optional
 2020-05-07 12:04:16 -06:00
Pierre-Olivier Vauboin
8d8ceee838 boards/arm/stm32h7/stm32h747i-disco: support for FMC SDRAM 2020-05-07 10:29:01 -06:00
Masayuki Ishikawa
1cf62c7db9 arch: k210: Fix cpu1 hangup during boot with qemu 2020-05-07 08:33:50 +02:00
Ouss4
6eb6d31c32 Fix nxstyle complaints 2020-05-06 21:56:40 -06:00
Ouss4
d56c613b7d arch/avr,renesas,risc-v: The *_getsp function was moved to a header 
file, remove it from the different source files that used to implement
it to avoid redefinitions.
 2020-05-06 21:56:40 -06:00
Ouss4
a4dd967440 arch/: Implement up_tls_info() for the rest of the architectures. 2020-05-06 21:56:40 -06:00
Ouss4
1e3ec6ecd0 arch/: Implement Thread Local Storage for the rest of the architectures. 
The change consisted on modifying *_usestack.c and *_createstack.c
 2020-05-06 21:56:40 -06:00
Xiang Xiao
3e00d182d2 Fix nxstyle issue 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-05-06 20:53:11 -06:00
Xiang Xiao
94bb2e05bb syslog: Code outside libc shouldn't call nx_vsyslog directly 
since nx_vsyslog is the implementation detail

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-05-06 20:53:11 -06:00
Yang Chung-Fan
6b1f94ee49 arch: x86_64: real-mode bootstrap code should jump to 1M 2020-05-06 08:35:09 -07:00
Yang Chung-Fan
ffa2027226 arch: x86_64: Add option to disable interrupt controller initialization 2020-05-06 08:35:09 -07:00
Yang Chung-Fan
c63c8a3841 arch: x86_64: Add real-mode bootstrap stub 2020-05-06 08:35:09 -07:00
Yang Chung-Fan
9ab6b92ad7 arch: x86_64: move the disable multiboot2 marco around to retain labels 2020-05-06 08:35:09 -07:00
Yang Chung-Fan
235d905001 arch: x86_64: remove leftover debug output 2020-05-06 23:33:46 +08:00
Masayuki Ishikawa
4ca19e7e74 arch: k210: Set CPU clock based on PLL0 settings 2020-05-05 17:21:32 -07:00
Gregory Nutt
bda24f09c2 libs/libc/tls/tls_getinfo.c: Add tls_get_info() 
Move the logic to get TLS information from an inline function to a normal function.  For the unaligned case, it is probably too large to be inlined.

Also fixes some minor things from review of previous commits.
 2020-05-05 18:56:33 +01:00
Abdelatif Guettouche
b7e7fba732 TLS_UNALIGNED (#2) 
* Implement the TLS_UNALIGNED
 2020-05-05 18:56:33 +01:00
Pierre-Olivier Vauboin
8d763d37ab arch/arm/src/stm32h7/stm32_oneshot: fix style issues 2020-05-05 11:53:58 -06:00
Pierre-Olivier Vauboin
d96565a765 arch/arm/src/stm32h7: add support for oneshot timer 
The code is ported from arch/arm/src/stm32
 2020-05-05 11:53:58 -06:00
Brennan Ashton
093aa040eb x86_64: Fix /dev/random rdrand implementation 
rdrand was checking the wrong return value for the intrinsics
so it would block forever.  The read function was also not returning
the actual number of bytes read.

This was tested by running the rand example application
NuttShell (NSH) NuttX-9.0.0
nsh>rand
Reading 8 random numbers
Random values (0x101584f70):
0000: 019a172df7d539f2df8550362e2d3f74 9b467c51ebe30b9f6510e540e34fabcc ...-..9...P6.-?t .F|Q....e..@.O..

Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
 2020-05-05 18:54:47 +08:00
Yang Chung-Fan
521e6354b6 arch: x86_64: fix style of intel64_lowsetup.c 2020-05-05 02:03:34 -07:00
Yang Chung-Fan
8b86fae8d3 arch: x86_64: Check only XSAVE and rename __eanble_sse3 to __enable_sse_avx 2020-05-05 02:03:34 -07:00
Yang Chung-Fan
2936f72651 arch: x86_64: revoke lower 128MB mapping later, ldmxcsr require 32-bit address 2020-05-05 02:03:34 -07:00
Brennan Ashton
aea90e7cf0 Clean code to match nxstyle requirements 
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
 2020-05-04 08:32:22 -06:00
Brennan Ashton
2405901bf2 Use mempy to perform type punning for setting gdt entry 
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
 2020-05-04 08:32:22 -06:00
Brennan Ashton
4c24d91b4a Surpress unused rtcb variable 
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
 2020-05-04 08:32:22 -06:00
Brennan Ashton
19afc57eef Fix null pointer reference in x86_64 rng 
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
 2020-05-04 08:32:22 -06:00
Brennan Ashton
a9871f584a Resolve linking issues with x86_64 port 
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
 2020-05-04 08:32:22 -06:00
Masayuki Ishikawa
11bbe3997e arch: x86: Add hlt instruction to save power in qemu_idle.c 2020-05-04 07:13:30 -06:00
raiden00pl
f03ed73f91 arch/arm/src/stm32/stm32_adc.c: remove obsolete warnings 2020-05-03 15:57:49 -03:00
raiden00pl
534ba2cc18 arch/arm/src/stm32/stm32_adc: add setup and shutdown operations to the low-level interface 2020-05-03 15:57:49 -03:00
raiden00pl
b3a1aef773 arch/arm/src/stm32/stm32_adc.c: cosmetics 2020-05-03 15:57:49 -03:00
raiden00pl
5857c48b2e arch/arm/src/stm32/stm32_adc.c: setup/shutdown ADC instance only once 2020-05-03 15:57:49 -03:00
raiden00pl
e2a3266857 arch/arm/src/stm32/stm32_adc: add interface to configure EXTSEL/JEXTSEL from low-level ops 2020-05-03 15:57:49 -03:00
Gregory Nutt
1bab5b6813 arch/arm/: Rename up_intstack_* to arm_intstack_* 
The naming standard at https://cwiki.apache.org/confluence/display/NUTTX/Naming+FAQ requires that all architecture-private functions begin with the name of the arch, not up_.

This PR addresses only these name changes for the ARM-private functions up_instack_base() and up_instack_top() which should be called arm_instack_base() and arm_instack_top().

There should be no impact of this change (other that one step toward more consistent naming).

Normal PR checks are sufficient
 2020-05-03 14:48:40 -03:00